JPH0332152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a playback speed control device for a recording medium recorded in PCM.

When recording PCM signals on disk, constant linear velocity (CLV) is preferred over constant angular velocity (CAV) recording.
Records can record more information. CLV
In the case of recording, since the rotational speed of the disk differs between the inner and outer circumferences of the disk, a synchronization signal is recorded to rotate the disk at an equal linear speed, and the period of the synchronization signal read from the disk is constant. Control as follows. By the way, in order to read the synchronization signal from the disk, the rotation speed must be close to the normal number to be able to determine the synchronization signal.

Therefore, the problem was how to start the disk rotation.

As an example of the prior art, there is a method in which the read position (radial position) of the disk is read with a potentiometer, a normal rotation speed is determined, and the disk is controlled to a target rotation speed. This method requires a potentiometer that determines the reading position and a rotational speed detector that determines the disk rotational speed, which has the disadvantage of complicating the structure. Another conventional technique is to detect, for example, the maximum pulse width from among the read signals and control disk rotation so that this maximum pulse width becomes the regular pulse width. However, even with this method, a circuit is required to count the length of the maximum pulse width with a counter, compare it with the pulse width count reference value of the regular rotation speed, and output a voltage according to the difference and feed it back to the disk motor. Therefore, this circuit generally has poor accuracy. Therefore, once the synchronization signal is within a detectable range, it is necessary to switch to a regular loop that measures the period of the synchronization signal, compares it with a reference value, and outputs a voltage according to the difference. Therefore, in this method, it is necessary to provide two loops, a loop for starting the disk and a loop for steady rotation, resulting in a complicated configuration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reproduction speed control device in which the circuit configuration is reduced by partially sharing the circuits of the starting loop and the steady rotation loop.

The present invention is a reproducing device that reproduces data by controlling the rotational speed of a motor 2 using a signal read from a recording medium 1 on which digital data including a synchronization signal is recorded, synchronization period value generating means 3, 4, 21, 18, 1 for detecting and generating a value corresponding to the period of the detected synchronization signal;
2, a specific pulse width detector 16 that detects the pulse width of a specific pulse in the read signal, and converts the output of the specific pulse width detector into the synchronization signal period during normal operation/specific pulse during normal operation. calculation means 17, 1 for generating a value corresponding to the value multiplied by the pulse width of
0, 4, 21, 18, 12. Within the predetermined range in which the synchronization signal is detected, the motor control means 4, 19, 2 for controlling the rotational speed of
0, 15, 7, and are provided.

The output of the specific pulse width detector is converted by the calculation means so that the output of the synchronous period value generation means and the output of the calculation means are equal during normal operation, so these outputs are used to control the rotational speed of the motor. control means can be made available to the public.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In Figure 1, numeral 1 is a digital audio disk.In order to increase the recording density, signals are recorded using CLV (Constant Liner) where the linear velocity is constant regardless of the position on the inner or outer circumference of the disk.
Velocity) method is adopted. Therefore, the number of rotations of the motor 2 must be changed depending on the read position of the disk.

Reference numeral 3 denotes a synchronizing signal detection and reproducing circuit, which detects the synchronizing signal contained in the signal read from the disk and outputs only the synchronizing signal pulse. This part also has the function of generating a pulse at the position where the synchronizing signal should originally be to supplement the missing synchronizing signal due to a scratch on the disk or the like. The reproduction range of the synchronization signal generated by the synchronization signal detection and reproduction circuit 3 is limited due to the recording modulation method.

The modulation method shown in FIG. 2 will be explained as an example.
The details of the modulation method will be omitted, but in this method, the standard clock frequency is 4.3218MHz, so information is recorded in pulses with a width of 3T to 11T, with 1/4.3218M as the clock period (expressed as T). ing. The synchronization signal is defined as a continuous pattern of "H" and "L" of 11T and 11T or "L" and "H", and is recorded every 588T. Therefore, the synchronization signal is 4.3218MHz/588=7.35KHz. Among the read signals, 3T, 4T, 5T...10T, 11T signals must be counted and accurately distinguished using a clock signal, but in order to distinguish between 10T and 11T signals, 11T
The signal must be 10.5T or higher, and the synchronization signal frequency must be within ±0.5/11, or ±4.5%, of the normal frequency. Therefore, when the synchronizing signal frequency is other than ±4.5%, the synchronizing signal detection and reproducing circuit 3 becomes unable to identify the synchronizing signal and stops signal reproduction.

Reference numeral 6 denotes a digital frequency-voltage converter (hereinafter referred to as an F-V converter), which is composed of a reference clock signal generation circuit 12, a reference value 14 of a counter 11, a subtraction circuit 13, and a D/A converter 15. There is. The regenerated synchronization signal output from the synchronization signal detection and regeneration circuit 3 is input as a gate signal to the counter 11 via a 1/10 frequency divider of 21, and the clock signal 12 is counted to detect the synchronization signal frequency divider. The calculator 13 calculates the difference from the reference value, the D/A converter 15 generates a voltage according to the difference, the amplifier 7 amplifies it to the required loop gain, and the output voltage of the amplifier 7 is fed back to the motor. By controlling the rotation speed, the speed at which signals are read from the disk is kept constant.
5 is a pseudo synchronization signal generation circuit for starting the motor.

As described above, the synchronizing signal detection and reproducing circuit 3 does not operate unless the synchronizing signal frequency is within ±4.5% of the normal value, so it does not output a synchronizing signal at startup. Therefore, the purpose of the pseudo synchronization signal generation circuit 5 is to generate a pseudo synchronization signal to bring the rotation speed close to normal until the synchronization signal detection and regeneration circuit 3 starts operating. 4 is a switching device, which uses a discriminator 22 to determine whether or not a synchronization signal has been detected, which selects side A at startup and side B during normal operation.
can be switched to the side.

The operation of the pseudo synchronization signal generation circuit 5 will be explained below. As already explained, this method consists of signals with a pulse width of 3T to 11T, and the maximum pulse width
The synchronization signal is a 11T "H""L" or two consecutive "L""H" pattern, and the interval between the synchronization signals is 588T. Therefore, even if the synchronization signal cannot be detected, detect and find the maximum pulse width, and multiply this interval by 588/11, that is, the synchronization signal period during normal operation/the pulse width of the specific pulse during normal operation. The period of the synchronization signal can be found by The pseudo synchronous signal generating circuit 5 is a concrete example of this, and 8 is a maximum pulse width detector. In this maximum pulse width detector 8, at least T
The pulse width is counted using pulses narrower than the interval of , and the maximum pulse width value within a certain period of time is determined. Reference numeral 9 denotes a calculation machine which multiplies the value obtained by the maximum pulse width detector 8 by 588/11 to predict the synchronization signal interval. Reference numeral 10 denotes a pulse generator which uses the value obtained by the arithmetic unit 9 as a frequency division ratio and divides the pulses obtained by counting the above-mentioned pulse width to generate a pseudo synchronization signal.

The operating principle has been explained above, but when implementing the signal reproduction speed control device shown in FIG.
%), the count value of the counter 11 needs to be 5000 or more, and a 13-bit counter and a 13-bit subtraction circuit are required, making the circuit scale still too large for LSI implementation. An example in which this is improved will be described below as a second embodiment.

FIG. 3 is a block diagram showing a second embodiment of the invention. The configuration of FIG. 3 is similar to the example and configuration shown in FIG. 1, but the characteristics of the components differ. The difference is that the counter 8 shown in FIG. 1 is replaced with a counter 16 with a limiter in FIG. In FIG. 3, the calculation is performed using a limiter function calculator 17 that limits the calculation value by the counted value of the limiter counter 16, and the synchronization signal period counter shown in FIG. The reason is that the counter 18 is a repeating type that repeatedly decreases and counts. Figure 4 summarizes the differences in functionality.
16, 17, 18 in Fig. 4 are 16, 17, 18 in Fig. 3,
The functions of 18 counters are shown.

Components in FIG. 3 with the same numbers as in FIG. 1 have the same functions as in FIG. 1. PCM in which information signals and synchronization signals are recorded using the recording modulation method described above.
The signal read from the disk 1 is input to a synchronizing signal detection and reproducing circuit 3, where only the synchronizing signal is taken out, and is inputted to the F-V converter 6 via a switch 4 and a 1/10 frequency divider 21. Here, the synchronization signal frequency is 7.35KHz as mentioned above, and the reference signal generator 1
The oscillation frequency of 2 is 4.3218MHz. The 1/10 frequency divider 21 is used to increase the detection accuracy of the synchronization signal period measurement by the counter 18.
The output frequency will be 735Hz. When the period of 735 Hz is counted by the 4.3218 MHz of the reference signal generator 12, the number of counts is 5880, and when the period is counted by the counter 11 in Fig. 1, the relationship between the synchronizing signal period and the number of counts is as shown in Fig. 5 a, and the number of stages of the counter as 13
Steps are required. However, as mentioned above, the frequency range of the output of the synchronization signal detection and regeneration circuit 3 is ±4.5%, so the usable range of the counter is ±4.5% of the 5880.
5615-6145 and only requires 530 Dynamic Cleansing. Therefore, it is sufficient that the number of counters is 530 or more, and a resolution of 9 bits is sufficient. Therefore, the number of bits in the counter 18 is reduced from the number of bits in the counter 11 in FIG. 1, and counting is performed as shown in FIG. If it is wider than the playback range, there is no problem. In order to minimize the number of bits in the counter 18, it is necessary to set the initial value so that the center of the count value is at the target center value. In this embodiment, the minimum number of bits of the counter 18 is 9 bits, so the count number is 1024, and in order to set the center value to 512, the initial value is 1024 - {5880 - 512 - (1024 × 5)}
= 776 is good.

The counter method described above is shown in FIG.
If the counter 11 shown in FIG. 1 requires 13 bit stages, it can be realized with 9 stages and the number of circuit elements can be reduced. In addition, the standard value 14,
While the subtraction circuit 13 also required 13 bits, the subtracter 19 and the reference value 20 only need a 9-bit configuration, allowing the circuit scale to be reduced significantly. The D/A converter 15 outputs a voltage according to the output of the subtracter 19, and by feeding this back to the motor 2, the reading speed can be controlled to be constant.

Next, the time when the motor is started will be explained. The pseudo synchronization signal generating circuit 5 shown in FIG. 1 generates a pseudo synchronization signal according to the maximum pulse width. If this pseudo synchronization signal period is measured using the counter characteristics shown in Figure 5a,
Although the period can be measured accurately and there is no problem, if the counter 18 with a reduced number of bits is used to count, the period of the pseudo synchronization signal may exceed the range D as shown in FIG. 5B. The count value in this case is not the original count value, and a malfunction will occur. In order to prevent this, the circuit must be configured so that when the period of the pseudo synchronization signal outputted by the pseudo synchronization signal generator 5 exceeds the range D, it becomes the minimum value or the maximum value of the range D.

This restriction is performed by the arithmetic unit 17, the characteristics of which are shown in FIG. This arithmetic unit multiplies 588/11, but since a digital multiplier requires a large circuit scale, it uses ROM (Read Only).
Memory) or PLA (Programmable Logic
It is a good idea to use an Array) to create a table. It is easy to make the output of this ROM or PLA the characteristics of the arithmetic unit 17 in FIG. 4, and the circuit scale can be reduced. Furthermore, in order to reduce the scale of this ROM or PLA, the first counter 8 is provided with an upper limit value for the count value of the counter, like the detector 16 in FIG. Setting an upper limit on the count value can be easily achieved by reducing the number of stages of the counter to the required number of bits and enabling the counter when the contents of the counter overflow.

As described above, the counter 18 shown in FIG. 3 is a 9-bit repeating type as shown in FIG. 4, the counter 16 is provided with a limiter as shown in FIG. By setting the frequency range of the signal to be within the dynamic range of the counter 18, it has become possible to significantly reduce the overall circuit scale without impairing the functionality of the system shown in FIG.

As explained above, in the present invention, by sharing the circuit configuration of the startup loop and the steady loop of the CLV disk, it has become possible to significantly reduce the circuit scale. Furthermore, the dynamic range of the F-V converter counter is a repeating type that is wider than the synchronization signal detection and reproduction range, the counter for detecting the maximum pulse width of the pseudo synchronization signal generation circuit is equipped with a limiter, and the arithmetic unit is equipped with a limiter. Dexterity ROM or
The circuit scale of the PLA, FA converter counter, reference value, and subtraction circuit can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is an EFM signal waveform diagram, Fig. 3 is a block diagram showing another embodiment of the present invention, Fig. 4 is a functional comparison diagram of the components of Figs. 1 and 3, and Fig. 5 is an F- FIG. 3 is a diagram showing the operating principle of a V converter counter. 1...PCM disk, 2...motor, 3...
Synchronous signal detection reproducing circuit, 4... switch, 5...
Pseudo synchronous signal generation circuit, 6...F-V converter, 7
...Amplifier, 12...Reference signal generator, 15...
D/A converter, 21... 1/10 minute cycle, 16... Maximum pulse width detector with limiter, 17... Arithmetic unit with limiter, 18... Repetition type counter, 19...
...Subtractor (8bit), 20...Reference value (8bit).

Claims (1)

[Scope of Claims] 1. A reproducing device that reproduces data by controlling the rotational speed of a motor using a signal read from a recording medium on which digital data including a synchronization signal is recorded, wherein the synchronization signal is derived from the read signal. a synchronization period value generating means for detecting the period of the detected synchronization signal and generating a value corresponding to the period of the detected synchronization signal; a specific pulse width detector for detecting the pulse width of a specific pulse in the read signal; and the specific pulse width. a calculation means for generating a value corresponding to the output of the detector multiplied by the synchronization signal period during normal operation/the pulse width of the specific pulse during normal operation; A reproduction speed control device comprising: control means for controlling the rotational speed of the motor according to the output of the synchronization period value generation means, and according to the output of the calculation means outside the predetermined range.