JPH0427017Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a digital audio disk reproducing device that detects a defect in a disk and changes the gain of a tracking servo circuit.

(Prior art) Conventional digital audio disk (DAD)
In a playback device (abbreviated as ), if there are defects or dust on the disc during playback, the pickup will jump and correct tracking will not be performed. For this reason, it is necessary to detect defects and dust and reduce the tracking ability of the pickup at that location, that is, to reduce the gain of the tracking servo circuit while maintaining stability.

Therefore _, conventionally, the detection output D _IN from a defect detection circuit for detecting a defect in the disk is supplied to a shift register 1 as shown in FIG. 7, and a frequency generator ( below
The output from the shift register 1 is supplied to the cascaded D flip-flop circuits 3, 4 and 5, and the output from the shift register 1 is supplied to the cascaded D flip-flop circuits 3, 4 and 5. The outputs of 4 and 5 are supplied to the OR gate 6, and the defect detection output D _IN is delayed by one rotation of the disk up to the D flip-flop circuit 4.
A signal D _OUT for reducing the gain of the tracking servo circuit by extracting the outputs of the flip-flops 3, 4, and 5 via the OR gate 6 and expanding them to a predetermined range including the defect detection output delayed by one rotation of the disk. is obtained as shown in FIG. In other words, one revolution of the disk is divided into n parts, the position of the flaw on the track when the flaw detection signal is output is memorized, and the gain of the tracking servo circuit is lowered in advance around the same position in the next revolution. There is.

(Problems to be Solved by the Invention) In order to change the gain of the tracking servo device using the conventional device as described above, one revolution of the disk is divided into n parts and addresses are assigned.

However, in order to divide one rotation of the disk into n parts,
The output from the FG circuit is multiplied by N (n=N×, where the frequency of the output signal from the FG circuit per revolution of the disk) is obtained to obtain a clock pulse, and one rotation of the disk is divided into n sections using this output. There is.

However, in order to obtain the clock signal from the FG signal, an analog multiplier circuit is used, but since the rotational speed of the disk is a constant linear speed and the output period of the FG circuit also changes depending on the track position, the configuration of the multiplier circuit is There was a problem that made it complicated.

(Means for Solving the Problems) In order to solve the above problems, the present invention is constructed as follows.

The rotational speed of a digital audio disk driven at a constant linear velocity is detected by a frequency generator, the output signal frequency of the frequency generator during one rotation of the disk is multiplied by N, and when a defect in the disk is detected, the multiplied output is In the digital audio disk reproducing apparatus, the detected defect signal is delayed by one rotation period of the disk, and the gain of the tracking servo amplifier is reduced over a predetermined range including the delayed detected defect signal. a counting means for counting one cycle period of the output signal of the frequency generator in pulse width units; a dividing means for dividing the count value of the counting means by a multiplication ratio N; The frequency of the output signal of the frequency generator is adjusted to N by a multiplier equipped with a correction means for correcting the difference between the output signal of the generator and the division result one cycle before.
It was configured to multiply.

(Function) The rotation speed of the disk is detected by the FG circuit. The period for one rotation of the disk during the FG output from the FG circuit is counted in units of pulses of a predetermined width, and this counted value is divided by the multiplication ratio N. As a result, the division result corresponds to the period of the frequency signal obtained by multiplying the FG output by approximately N. This value is corrected by 1/N of the difference from the value of the FG output one cycle before.

Therefore, for example, when a disk is driven to rotate at a constant linear velocity, as in a DAD playback device, and information is picked up sequentially from the inside, one cycle of the FG output for one rotation of the disk increases sequentially. , the difference between the value obtained by multiplying the one-cycle period by 1/N and one period of the multiplied signal one period before the FG output is corrected by 1/N, so that the period of the multiplied signal is also the same as the period of the FG signal. As a result, the value is multiplied. Moreover, this multiplication can be performed by digital circuits such as counting means, dividing means, correction means, etc., which simplifies the structure.

(Example of idea) The present invention will be explained below with reference to examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 11 is a retriggerable counter, which has a preset clock pulse CK ₀ (its frequency is set to be higher than the output signal frequency of the FG circuit, for example, 100 times or more).
For example, it counts down, and when the counted value reaches zero, it outputs a carry signal (borrow signal) C, and then presets the output of a latch circuit 15, which will be described later. The count value of the retriggerable counter 11 is reset to the latch circuit 12 at the rising edge of the output signal of the FG circuit.
The latch output is supplied to a divider circuit 13, which divides the output of the latch circuit 12 by a multiplier N (N=8 in this example) of the output frequency of the FG circuit. The division circuit 13 supplies the addition circuit 14 with
The latch output of the latch circuit 15 one latch clock before is added and the latch output is newly latched into the latch circuit 15. This new latch output is preset in the retriggerable counter 11 upon generation of the carry output.

The operation of one embodiment of the present invention configured as described above will be explained.

The output from the FG circuit is as shown in Figure 2a. On the other hand, the retriggerable counter 11 is shown in FIG.
If the clock pulse CK ₀ is counted as schematically shown in , and if the ratio of the output frequency of CK ₀ and FG at this point is 100, the borrow output _CK is generated when α ₀ (=12,100/8). Similarly, clock pulse CK ₀
When the next rising edge of the output of the FG circuit is reached, the output latched by the latch circuit 12 is, for example, [Δ="9"]. (=multiplication number)". Therefore, the division becomes [Δ/8=9/8=(1+1/8)], and "1" is output from the division circuit 13. If it is assumed that 8 multiplication has been performed immediately before this, the latch output of the latch circuit 15 is "12", and the latch output of the latch circuit 15 is ["12" + "1"], and "13" is the next one. It will be preset to the triggerable counter. Therefore, α ₀ will be changed from “12” to “13”.

As described above, the clock signal CK changes from the state shown in FIG. 2c to the state shown in FIG. can get.

By using the clock signal CK obtained as described above as the clock signal CK in FIG. The signal frequency is 12 cycles as shown in Figure 3a, and the multiplication number is as shown in Figure 3b.
As shown in Fig. 3, when N = "8" and the number of bits of shift register 1 is "94" bits, the defect signal D _IN generated at the third pulse position in Fig. 3c is as shown in Fig. 3d. The output signal D _OUT is obtained with a delay of one rotation from the OR gate 6. This relationship is the 8th
This is the same as the case shown in the figure.

In addition, in a DAD playback device, the tracks are scanned from the inner circumference of the disk at a constant linear velocity and reach the outer circumference, so the output signal frequency of the FG circuit increases sequentially.
4 was used, but if the track was scanned from the outer periphery,
If the signal reaches the inner circumferential side, a subtraction circuit may be used instead of the addition circuit 14.

In addition, when scanning is switched to the inner circumferential side and the outer circumferential side, as shown in Fig. 4,
An addition/subtraction circuit 16 is provided in place of the addition circuit 14, and a determination circuit 17 is provided to determine whether the output of the counter 18 is greater than or equal to the multiplication number "N". Just let them choose subtraction. When the output of the counter 18 is greater than or equal to the multiplication number "N", the output of the division circuit 13 is added, and when it is less than the multiplication number "N", the output of the division circuit 13 is subtracted from the output of the latch circuit 15.

Next, other embodiments of the present invention will be described.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention, which is an example in which a microcomputer is used.

21 is an FG circuit, which outputs the output signal FG from the FG circuit 21 and the defect detection signal D _IN from the defect detection circuit 22.
is supplied to the flip-flop 23 to set the flip-flop 23, and this set output _IN is input to the microcomputer 24 for reading. Further, a signal indicating that the DAD reproducing device is in normal operation, that is, in an operation other than a search operation, fast forward operation, etc., is supplied as a reset signal _TEP .

On the other hand, the microcomputer 24 outputs an output that reduces the gain of the tracking servo amplifier 25.
Output D _CON . Furthermore, it outputs a signal synchronized with the fall of the defect detection signal D _IN , that is, a reset signal D _INCL synchronized with the rise of the set output _IN , and resets the flip-flop 23 with the reset signal D _INCL . Output _CON corresponds to output D _OUT .

In another embodiment of the present invention configured as described above, when the defect detection routine is executed, initial settings such as clearing the memory area are performed as shown in FIG. 6 (step a), and following step a, One period T ₁ of the FG signal output from the FG detection circuit 21
For example, the pulse signal (period
T ₂ ) to divide one period of the FG signal (T ₁ ) into the period
Counting is performed at _T2 , and the counted value _C0 is temporarily stored in the storage area of the microcomputer 24 (step b). If the FG signal frequency corresponding to one rotation of the disk in step b is 12 cycles, this corresponds to counting one period of FIG. 3a in a period _T2 in step b.

Count value in step b following step b
_C0 is 1/N and temporarily stored in the storage area of the microcomputer 24 (step c). If the multiplication ratio is now “8”, step c is C ₁ ←
The processing is C ₀ /8. In step c, _C1 is the period when the FG signal is multiplied by 8, that is, Fig. 3b.
The state is such that one cycle of the clock pulse CK shown in Figure 1 is shown in units of cycle _T2 .

Following step c, dropout control processing is performed (step d) which performs the same function as the circuit shown in FIG. 7 except for the multiplier circuit 2. That is, when the state of the set output from the flip-flop 23 is read and the output _IN is detected,
When the output _IN is read, [(f×NC ₁ ) −
During the period from [C ₁ ] to [(f×NC ₁ )+C ₁ ], the output D _CON is kept at a low potential, and the gain of the tracking servo amplifier 25 is reduced. This state is as shown in FIGS. 3c and 3d. Furthermore, when a period _C1 has elapsed since the detection of the output D _IN , a reset signal D _INCL is output, and the flip-flop 23 is reset to prepare for the next defect detection. The timing of generation of the reset signal D _INCL is as shown in FIG. 3e. Therefore, even if there is a defect in successive adjacent lot numbers, the same effect as above will apply. On the other hand, when no defects exist, the output _IN is not input to the microcomputer 24, and the gain of the tracking servo amplifier 25 is not reduced.

Following step d, a correction is made to C ₁ =C ₀ /N stored in step c (step e). In other words, FG for one rotation of the disk
The frequency of the signal increases as the disk rotates. Therefore, the FG at the first rotation of the disk
The rise of the signal does not necessarily coincide with the rise of the (N+1)th pulse of the clock pulse having a period of C ₁ =C ₀ /N, and an error of ΔC occurs during this time. Therefore, in step e
A correction of C ₁ ←C ₁ +ΔC/8 is made to prepare for the next generation of the defect detection signal. After step e, it is checked whether the defect detection signal D _IN is generated (step f). When the occurrence of the defect detection signal D _IN is detected in step f, the process is executed again from step a, and the defect detection signal D IN is detected in step f.
If the occurrence of D _IN is not detected, go to step d again.
is executed.

(Effects of the invention) As explained above, according to the invention, the FG signal is multiplied by a digital circuit consisting of a counting means, a division means, and a correction means including addition and subtraction, so that the structure is simplified. Furthermore, even if the period of the FG signal changes, it can be easily followed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIGS. 2 and 3 are timing diagrams showing the configuration of an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a modified example of one embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention. FIG. 6 is a flowchart for explaining the operation of another embodiment of the present invention. FIG. 7 is a block diagram showing gain control of a tracking servo amplifier. FIG. 8 is a timing diagram for explaining gain control in FIG. 7. 1...Shift register, 3, 4 and 5...D
Flip-flop circuit, 11... Retriggerable counter, 12 and 15... Latch circuit, 13...
...Division circuit, 14... Addition circuit, 16... Addition/subtraction circuit, 21... FG circuit, 22... Defect detection circuit,
23...Flip-flop, 24...Microcomputer, 25...Tracking servo amplifier.

Claims (1)

[Scope of utility model registration request] The rotational speed of a digital audio disk driven at a constant speed is detected by a frequency generator, and the rotation speed of said disk 1 is detected by a frequency generator.
The output signal frequency of the frequency generator during rotation is multiplied by N, and when a defect in the disk is detected, the detected defect signal is delayed by one rotation period of the disk based on the multiplied output, and the delayed detection is performed. In a digital audio disk playback device that reduces the gain of a tracking servo amplifier over a predetermined range including a defective signal, a counter that counts one cycle period of the output signal of the frequency generator in units of pulses of a predetermined width. means, a dividing means for dividing the count value of the counting means by a multiplication ratio N, and dividing the result of the division by the dividing means by 1/N of the difference between the result of division one cycle before the output signal of the frequency generator. A multiplier equipped with a correction means for correcting the output signal frequency of the frequency generator
A digital audio disc playback device characterized by multiplication.