JPH0646477B2 - CD processing device signal processing circuit - Google Patents

Description

The present invention relates to a signal processing circuit of a CD (compact disc) reproducing device, and more particularly to storing symbol data read from a CD in a RAM and further storing the symbol data. The present invention relates to a signal processing circuit that reads out deinterleaved symbol data and controls the rotation speed of a disk motor based on the amount of data stored in a RAM.

(B) Conventional technology In the CD system, an error correction system called CIRC (Cross Interleave Reed Solomon Code) is used, and 24 information symbols (8 bits) are provided by 6 samples for each of the right channel and the left channel. And a total of 32 symbols of 8 parity symbols (8 bits) are created. An 8-bit subcode is added to these 32 symbols, and these are EFM-modulated and recorded on the disc as one frame together with a 24-bit hum sync signal. Recording on the disk is performed by a constant linear velocity (CLV) method.

The signal processing circuit in the CD reproducing device decodes the EFM signal read from the disc to create an 8-bit symbol, sequentially stores the symbol in the RAM, and reads the symbol stored in the RAM. performs C ₁ error correction and C ₂ error correction by CIRC circuit for each frame Te, operation for storing the corrected symbol again RAM, the corrected symbol is read from the RAM is applied to the DA converter operation And is doing.

Further, in the CLV system, the disc motor is controlled by a servo circuit so that the disc has a constant linear velocity. That is, the phase of the signal obtained by dividing the synchronizing signal created by the PLL circuit based on the EFM signal by the dividing circuit and the signal obtained by dividing the reference signal from the reference oscillator by the dividing circuit are compared,
The disk motor is controlled so that they match. However, if the servo of the disk motor becomes inaccurate due to dropout of the EFM signal or the like, the linear velocity of the disk becomes unstable and jitter occurs in the EFM signal.
These jitters can be absorbed by the RAM within a certain range, but if the range is exceeded, the jitter cannot be absorbed.

Therefore, conventionally, the amount of data stored in the RAM is detected, and the division ratio of the frequency dividing circuit that divides the synchronization signal created based on the EFM signal is increased or decreased according to the amount of storage, or the reference signal is divided. By increasing or decreasing the division ratio of the dividing circuit
It was controlling the disk motor. As a result, RA
The disk motor servo can be performed so as not to exceed the jitter absorption amount of M.

The above technique is described in JP-A-59-90262.

(C) Problems to be Solved by the Invention However, conventionally, an arithmetic circuit for calculating a difference between a write address and a read address of an address counter that controls the address of the RAM in order to detect the amount of data accumulated in the RAM is provided. It is necessary and has the drawback of increasing the number of elements.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and R
A first counter for determining an AM write address;
A second counter that determines the read address of the RAM, a third counter in which the contents of the second counter (or the first counter) are preset, and a clock pulse is applied to the third counter to make it count. A fourth counter that counts the number of clock pulses until the contents of the first counter (or the second counter) match, and a count value of the fourth counter is within a predetermined range. The servo circuit includes a control circuit for increasing or decreasing the frequency division ratio of a frequency dividing circuit and presetting a predetermined value in the first or second counter when the frequency is out of a predetermined range.

(E) Operation According to the above means, the first counter is the write request pulse 32LP created based on the synchronization signal of the EFM signal.
The second counter counts up and specifies the write address, and the second counter counts up and specifies the read address according to the reference clock pulse from the crystal oscillation circuit. For example, it is increased by "6" area). Therefore, if the count value of the second counter is preset in the third counter by the preset pulse PS generated at a certain timing and then the clock pulse COMPCL is applied to the third counter to start counting, If the disk is rotating, the coincidence between the first counter and the third counter is detected by the six clock pulses COMPCL. That is, when they match, the jitter absorption amount of the RAM can be determined by the count value of the fourth counter, and the control circuit increases or decreases the frequency division ratio of the frequency divider circuit of the servo circuit based on the count value of the fourth counter. When the value is out of the predetermined range, a predetermined value is preset in the first counter and R
The write and read addresses of AM are returned to normal positions.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. First
The counter (FCTRH) (1) designates an address area of a RAM (not shown) in which 24 information symbols and 8 parity symbols for one frame, which are double-tone modulated from the EFM signal, are designated. It consists of Further, the counting input force CL of the first counter (1) is
The carry output of the counter (FCTRL) (2) that counts the write request pulse 32LP generated every time one symbol is extracted from the EFM signal is applied.
That is, the first counter (1) specifies the upper address of the RAM for writing symbols for one frame and
(2) designates a lower address in which one symbol is written in the address area. Here, the write request signal 32LP is set to the PLL so as to be synchronized with the EFM signal.
A synchronization signal PLCK (4.
To be created on the basis of 3218MH _z), the jitter of the EFM signal, jitter occurs in the count of the counter (2) and the first counter (1).

On the other hand, the second counter (XCTR) (3) is made up of 7 bits and designates an address area in which one frame is stored in order to read one frame of symbols written in the RAM. A clock pulse φ _2M generated from a reference clock pulse oscillated by a crystal oscillating circuit (not shown) is applied to the count input CL of the second counter (3).
(2.1609MM _z) for counting the 49-ary counter (49
CTR) (4) continued hexadecimal counter (TnSR) (5)
Carry output is applied. That is, the timing of processing the symbol signal of one frame is 49 timings t
_{It is} composed of timing frames T _{1 to} T ₆ each consisting of ₀ to t _48, and when the processing of one frame is completed, the second counter (3) counts up by “1” and the count is based on the crystal oscillation circuit. Therefore, it is extremely accurate.

The third counter (COMPCTR) (6) is a 7-bit presettable counter, the 7-bit output of the second counter (3) is applied to a preset input terminal, and the preset control input P has a timing signal T ₅ and the signal SI generated at the first timing t ₀ of each timing T _{1 to} T ₆
The preset pulse PS output from the AND gate (7) to which NT is applied is applied, and further, the clock input CL
Includes the timing signal T ₅ and the timings t _{0 to} t _48.
Pulse SYNDCL output in synchronization with the timing of
AND gate (8) output pulse COMPC
L is applied. Fourth Counter (CLCTR) (9)
Is a 4-bit counter that counts the clock pulse COMPCL applied to the third counter (6) and counted. The reset pulse R is applied with the preset pulse PS and the clock input CL is applied with the clock pulse COMPCL. To be done.

Further, the 7-bit output of the first counter (1) and the 7-bit output of the third counter (6) are applied to the coincidence detection circuit (10), and the count values of the respective counters (1) and (6) are A match is detected. The detection output DET of the coincidence detection circuit (10) and the output of the fourth counter (9) are applied to the control circuit (11).

By the way, in the embodiment shown in FIG.
A difference of "6" frames is provided between the write address to and the read address from the RAM. That is, when the disk is rotating at a normal linear velocity, the count value of the first counter (1) is always larger than the count value of the second counter (3) by "6". Therefore, if the third counter (6) counts six clock pulses COMPCL, the coincidence detection circuit (10) should output the coincidence detection output DET, and the fourth counter (9) at that time. The count value of should be "6". Therefore, the control circuit (1
When the coincidence detection output DET is output, 1) determines the count value of the fourth counter 9 and increases or decreases the frequency division ratio of the frequency dividing circuit 12. Specifically, as shown in FIG. 2, a fourth counter
When the count value of (9) is "5" to "7", it is determined that the disk is rotating normally, and the frequency division ratio is not increased or decreased.
When the count value of the fourth counter (9) is in the range of "2" to "4", the control signal (+) for increasing the frequency division ratio is output because the rotation of the disk is slow, and , If the count value of the fourth counter (9) is between "8" and "10",
Outputs a control signal (-) to reduce the frequency division ratio, assuming that the disk has rotated faster. Further, when the count value of the fourth counter (9) is out of the range of "2" to "10", it is considered that the rotation of the disk is completely out of synchronization, and the muting signal MUTE is output. At the same time, the initial set pulse PS “6” is output.

The control signals (+) and (-) of the control circuit (11) are applied to the frequency dividing circuit (12) forming the servo circuit of the disk motor. The frequency dividing circuit (12) is a divider for counting the synchronizing signal PLCK of the EFM signal, and the frequency dividing output PLCCKPD is applied to the phase detecting circuit (13) and clock pulse φ _4M (4. 3218MH _z) is a comparison of output XDIVPD phase a dividing circuit for dividing (14). The frequency division ratio of this frequency divider circuit (14) is 1/588.
The division ratio of (12) is 1/588 when the control signals (+) and (-) are not applied. That is, 1 of the EFM signal
The number of bits is equal to the number of frames, and phase comparison is performed for each frame, and the disc motor is controlled by the output of the phase detection circuit (13). Meanwhile, the control signal from the control circuit (11)
When (+) is output, the frequency dividing ratio of the frequency dividing circuit (12) is 1/589, the disk motor is controlled in the direction of increasing rotation, and when the control signal (-) is output, the frequency dividing circuit (12) The dividing ratio of) becomes 1/587, and the rotation of the disk motor is controlled to slow down. This control is performed once every 128 frames.

On the other hand, the initial set pulse PS “6” output from the control circuit (11) is output from the “0” detection circuit (15) that detects that the count value of the second counter (3) has become “0”. The detection output DET "0" is applied to the AND gate (16), and the output of the AND gate (16) is the first counter (1).
Applied to the preset control input P. That is, when the count value of the fourth counter (9) is out of the range of "2" to "10", the second counter (3) is set to "0" by the initial set pulse PS "6". When this happens, "6" is preset in the first counter (1).
Therefore, at this time, the write address to the RAM and the read address from the RAM are forcibly pulled to the normal address position. Further, at this time, since it is doubtful that the symbol stored in the RAM is accurate, the control circuit is sent to the circuit for sending the symbol to the DA conversion circuit.
By applying the muting signal MUTE from (11), muting is performed for 128 frame periods to prevent noise generation.

In the circuit shown in FIG. 1, as shown in FIG. 2, the signal is output at the timing t ₀ of the timing T ₅ among the timings T _{1 to} T ₆ for performing the signal processing of one frame. The count value of the second counter (3) is preset in the third counter (6) by the preset pulse PS
The clock pulse COMPCL generated by the pulse SYNDCL output at the timing T ₅ is counted by the third counter (6) and the fourth counter (9), and the first counter (1) and the third counter (1) The state of the RAM can be determined by the count value of the fourth counter (9) when the count values of (6) match.

(G) Effect of the Invention As described above, according to the present invention, an arithmetic circuit for calculating the write address to the RAM and the read address from the RAM is not necessary, and the remaining amount of the RAM can be determined only by a simple counter. There is an advantage that the number is greatly reduced. Further, when the rotation of the disk motor is significantly out of synchronization, the generation of noise is prevented and the address for accessing the RAM can be pulled into a normal state.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation. (1) …… first counter, (2) …… counter, (3) …… second counter, (4) …… 49-base counter, (5) …… hexadecimal counter, (6) …… Third counter, (9) ... Fourth counter, (10) ... Match detection circuit, (11) ... Control circuit, (12) ...
… Division circuit, (13) …… Phase detection circuit, (14) …… Division circuit, (15) …… “0” detection circuit.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Kazuhiro Kimura 180 Sakata, Oizumi-cho, Gunma-gun Ojizumi-cho, Higashi Kyoyo Electric Co., Ltd. Sanyo Denki Co., Ltd. (56) Reference JP-A-57-164465 (JP, A) JP-A-60-177471 (JP, A) Actually developed Shou-60-12856 (JP, U)

Claims (1)

[Claims] 1. Symbol data demodulated from an EFM signal read from a disk is stored in a RAM, and the RAM is stored in the RAM.
In the signal processing circuit of the CD reproducing device, which reads the symbol data from the disk and deinterleaves the data, and corrects the rotation speed of the disk motor based on the amount of data stored in the RAM. 1 counter, a second counter for determining the read address of the RAM, a third counter in which the contents of the second counter (or the first counter) are preset, and a clock for the third counter. A fourth counter that counts the number of clock pulses until the content of the first counter (or the second counter) matches when a pulse is applied; and the count value of the fourth counter is within a predetermined range The operation to set the frequency division ratio of the frequency divider circuit built in the disk motor servo circuit to the reference value or increase or decrease within the predetermined value from the reference value That operation was carried out, characterized by comprising a control circuit for presetting a predetermined value in the first counter or the second counter when outside the predetermined range C
A signal processing circuit of the D playback device.