JPH02302963A - Information reproducing device - Google Patents

Abstract

PURPOSE:To obtain an information reproducing device in which a lead-in range is wide and which is highly accurate and, simultaneously, highly stable by providing a remainder means to detect a relative speed error between an information recording carrier and a reproducing head from a reproduced information signal. CONSTITUTION:A reproducing head 2 reads an information signal from an information recording carrier 1 in which the information signal divided into a prescribed unit is recorded on an information track, and outputs the reproduced information signal. A remainder means 3 detects remainder components between a unit, by which the reproduced information signal is divided, and the unit of the reference to be specified beforehand. A control means 4 changes a relative speed between the reproducing head 2 and the information track according to the output of the remainder means 3. Thus, by using all edges of the reproduced information signal, the relative speed error between the reproducing head and information track can be detected, and the relative speed error can be speedily corrected over the range of a wide speed error.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information reproducing device for reading information signals from an information recording carrier such as a disk or tape on which digitally modulated information is recorded.

BACKGROUND OF THE INVENTION In recent years, many devices have been developed that apply digital modulation technology to recording and reproducing audio and images.

Examples include compact discs and digital VTRs. The most important technical feature of these digital recording and reproducing devices is that the information recorded on the medium is encoded to correct errors during reading.

Such digital codes generally have a period that is an integral multiple of the basic unit representing the minimum period called a bit clock, and the run length (edge inversion period) is generally limited to a certain range.

Now, in order to extract information from a disk or tape on which digital codes are recorded as described above at the recording period, it is necessary to detect an error in the scanning speed between the playback head and the information recording carrier and eliminate this error. It is necessary to control it like this. As examples of such control, the following two methods are common.

The first method is to extract two consecutive bit clocks using a phase-locked loop (hereinafter simply referred to as PLL), and then synchronize the frequency and phase with the crystal oscillation reference clock so that the period of this bit clock is constant. The relative scanning speed between the reproducing head and the information recording carrier is controlled so that they match (for example, Japanese Patent Laid-Open No. 59-3749).

In the second method, the maximum period in the reproduced information signal is detected and the relative speed is controlled so that the period is constant (for example, Japanese Patent Publication No. 14424/1983).

Problems to be Solved by the Invention All of these methods have the following problems to be solved.

In the first method, first of all, it is not possible to activate the blade itself.

That is, at startup, the above-mentioned PLL free-runs and outputs a signal whose average frequency is approximately the same as the normal frequency. For this reason, it becomes impossible to detect the deviation between the normal scanning speed and the actual scanning speed, and it becomes impossible to generate the starting force.

This is because the retractable range of the above PLL is usually limited to a range of 5% or less of the normal scanning speed.
This is an essential issue in PLL. Secondly, it impairs the stability of the relative speed control system. That is, PLL
As is clear from the fact that the input/output characteristics of 2 are expressed as second-order lag elements, there is a phase lag. This phase delay causes problems such as causing unnecessary vibrations during startup, etc., and prolonging the settling time.

Furthermore, in the second method, there is a problem in that dirt or defects on the recording medium cause the above-mentioned relative speed to go out of order. In other words, the lack of information signal from the reproducing head due to the above-mentioned defects or the like is mistakenly recognized as the longest cycle. For this reason, there is a problem in that control is disturbed because an attempt is made to match a period, which is much larger than the longest period of the information signal, with the reference period. Secondly, even if there are no defects as described above, there is a problem that accurate control characteristics cannot be obtained. That is, the longest period included in the information signal is the one with a small appearance function. For example, the E used in compact discs
In the case of FM modulation, it is at most 2 to 3%. Therefore, for the remaining 98% to 97% of the information signal, it is impossible to detect a deviation in relative velocity, so there is a problem that even if the relative velocity is disturbed in this 98% to 97% section, it cannot be corrected.

In view of the above problems, the present invention provides an information reproducing device that has a wide pull-in range, is highly accurate, and is highly stable.

Means for Solving the Problems In order to solve the above problems, an information reproducing apparatus of the present invention reads an information signal from an information recording carrier on which an information signal divided into predetermined units is recorded on an information track, and reproduces reproduced information. a playback head that outputs a signal; a remainder means that detects a surplus component between the unit into which this playback information signal is divided and a predetermined reference unit; and control means for changing the relative speed between the information tracks.

Operation: With the above-described configuration, the information reproducing apparatus of the present invention can detect the relative velocity error between the reproducing head and the information track using all edges of the information signal read from the reproducing head.

Embodiment Hereinafter, an information reproducing apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an information reproducing apparatus according to a first embodiment of the present invention, and FIG. 2 is an operational waveform diagram of each main part of FIG. 1.

First, the general operation of this embodiment will be explained.

In FIG. 1, an information recording carrier 1 has an information track containing a digital code that has been subjected to EFM conversion (8-14 conversion) and has a run length of 3T to 11T, which is used for compact discs, laser discs with digital audio, etc. It is recorded on la. Here, IT is the period of one bit clock. The reproducing head 2 irradiates the information track 1a with a laser beam and generates an information signal S from the reflected light.
Play i. Note that the method and means by which the reproducing head 2 follows the information track 1a and reproduces the information signal St are already known and different from the essence of the present invention, so they will not be described in further detail.

The remainder means 3 includes a reference signal generating means 32 that outputs a reference clock signal Sck, a head amplifier 31 that receives the reproduced information signal Si and converts it into a binary information signal Sd, and a head amplifier 31 that is synchronized with the reference clock signal Sck and converts it into a binary information signal Sd. A double-edge differentiator circuit 33 that outputs an information pulse signal Sp with a width of one clock cycle each time the signal Sd rises and falls, a remainder calculation circuit 34 that measures the period of the information pulse signal Sp, and the output of the remainder calculation circuit 34 is held. It is composed of a holding circuit 35. The control means 4 also includes a full adder 41 which receives the output of the holding circuit 35 at its A terminal, and a first register 42 which receives the output Da of the full adder 42 and latches this Da in accordance with the information pulse signal Sp. , this first register 4
a second register 43 that converts the output of 2 into a fixed period;
A digital-to-analog converter (hereinafter referred to as a D/A converter) 44 receives the output of this second register and converts it into an analog voltage, and receives the output of the D/A converter 44 and outputs it to the drive circuit 46. A drive circuit 46 outputs a drive signal to a motor 47, and a motor 47 rotates the information recording carrier 1.

The operation of the information reproducing apparatus of this embodiment configured as described above will be explained below. FIG. 2 is an operational waveform diagram of each main part in FIG. 1, and corresponds to each part in FIG.

The reference signal generation source 32 outputs a clock signal Sck and a latch signal Sr of a constant period using crystal oscillation or the like. The period τ of this clock signal Sck is τ=T/8.

The period of the latch signal Sr is 588T.

On the other hand, the information signal Si read out from the information recording carrier 1 by the reproducing head 2 is transmitted to the head amplifier 31 by 2
Values are shaped and output as an information binary signal Sd. This information binary signal Sd is input to the both edge differentiating circuit 33. This both edge differentiating circuit 33 is connected to the first D flip
A flop (hereinafter referred to as F.F.) 301 is synchronized by a clock signal Sck, and this first DF.
The Q terminal output S1 of F is input to the D terminal of the second DF-F2O3, and is further delayed by one clock period τ. The Q output S2 of this second DF-F2O3 and the first DF-F
The Q output S1 of 2O3 is input to the exclusive OR circuit 303 and output as an information pulse signal Sp with a pulse width of τ.

This information pulse signal Sp is transmitted to the reset terminal (
(R terminal shown) and a set terminal (S terminal shown) of the third TF-F2O3. On the other hand, clock signal S
ck is input to the T input terminal of the first TF-F. As a result, the remainder calculation circuit 34 functions as a 3-bit up counter with an initial value of "4". Since the period τ of the clock signal Sck is T/8 as described above, the value of the remainder calculation circuit 34 is as shown in FIG.
The starting point is ``4'', and the values range from ``0'' to ``7'' in the IT cycle.

ll- Now, the value of this remainder calculation circuit 34 is the information track 1a.
and the reproducing head 2 (in other words, the rotational speed error of the motor 47).

That is, when the information signal Si is read by the reproducing head 2, it is modulated by the rotational angular velocity ω of the motor 47. Therefore, the period t of the reproduced information signal is t=KTω/ω0 (1) where the rotational frequency at the time of information writing is ωO.
It can be expressed as However = 3. 4. ..., 11.

On the other hand, the rotational angular velocity ω can be expressed as ω=ωθ+δ (2). Here, δ represents the rotation error.

Therefore, by substituting equation (2) into equation (1), t becomes t=KT+KTδ/ω0...
・(1) It becomes l. In this way, the run length t of the reproduced information signal Si is indeterminate and child 1It depending on the information signal.
Contains a component called KT, which is impossible to use. Therefore E.F.M.
It is clear that if the run length KT due to conversion is removed, only the second term of equation (1) is left, and data proportional to the rotation error δ can be obtained.

Now, if we measure t using the period τ of T=8τ and the initial value “4”, the measured value will be L=8+8+δ
/ω0+4 ... is given by (3).

When we perform the remainder calculation of t on this equation (3) with 8, which corresponds to the basic unit IT, as the modulo, the result is d=8 δ/ωo+4...(4)
And, 0≦d≦7, and it is possible to obtain an output proportional to the rotation error δ,
This input/output relationship has the characteristics shown in FIG. 4(a). The characteristic shown in Figure 4(a) is so-called offset binary, so by taking the most significant bit from the inverted Q output, it can be made into a two's complement number, which has the equivalent function of subtracting 4 from d. can be realized. This input/output characteristic is shown in Figure 4 (
It can be expressed as b).

The average run length of EFM is approximately 5T, so K
Assuming =5, from equation (4), 1δ1≦0.1ωo...(5)
Therefore, speed errors can be detected within an average range of 10%.

This corresponds to more than twice the pull-in range of the PLL. Furthermore, even if there is a defect such as a scratch on the information recording carrier 1, as is clear from FIG. 7” value.

In this manner, the remainder calculation circuit 34 detects the remainder component between the period of the information signal Sl divided into predetermined units, which are integral multiples of the bit clock, and the reference unit of the EFM modulation method, which is called the bit clock period. By detecting this surplus component, the rotation error of the motor 47 is detected.

Now, the value of the remainder calculation circuit 34 obtained in this way is used as an information pulse signal by a holding circuit 35 composed of the third DF-F2O3, the fourth DF-F2O3, and the fifth DF-F2O3. It is held every period t of Sp and output as speed error data De. This velocity error data I)e is cumulatively added at a period t by an integrating circuit consisting of a full adder 41 and a first register 42, and noise caused by jitter is removed.

Thereafter, the output of this integrator is held in the second register 43 for each synchronization signal S'r output from the reference signal generation source 32, converted into a constant period, and then converted into an analog signal by the D/A converter 44. It is output as an error signal Se. This analog error signal Se causes the motor 47 to generate a driving torque via the phase compensation filter 45 and the driving circuit 46.

A series of loops consisting of the information recording carrier 1, the reproducing head 2, the remainder means 3 and the control means 4 are connected to the motor 4.
7 speed control loops are constructed.

By the action of this speed control loop, the speed error between the information recording carrier 1 and the reproducing head 2 is controlled to be zero.

As described above, according to this embodiment, speed errors can be detected over a wide range of 10% on average by measuring the period of the information signal si and calculating the remainder with this measured value modulo the period of the pit clock. , a wide range of control is possible. Furthermore, since the information recording carrier is less susceptible to defects such as scratches, speed errors can be detected stably.

In this embodiment, an integrator consisting of a full adder 41 and a first register 42 is used; however, even if the first register 42 is reset every time the second register 43 latches, the essential difference will still be made. There isn't.

Furthermore, although the period of the clock signal Sck has been described as T/8, it may be T/4 or T/16. Furthermore, generally T/M (M>2 natural number)
However, nothing essentially changes.

FIG. 5 is a block diagram of an information reproducing apparatus showing a second embodiment of the present invention, and FIG. 6 is an operation waveform diagram of each main part in FIG.

In FIG. 5, the information recording carrier 1, the reproducing head 2 and the control means 4 are the same as the information recording carrier 1 in the embodiment of FIG.
, the reproduction head 2 and the control means 4, and the explanation thereof will be omitted. Further, a head amplifier 31, a reference signal generation source 32, and a both edge differentiating circuit 3 constituting the remainder means 3a.
3 is also the same as the embodiment shown in FIG. 1, and its explanation will be omitted.

Now, the differences between this embodiment and the embodiment shown in FIG. 1 are as follows.

34a is a remainder calculation circuit, which is similar to the remainder calculation circuit 3 in FIG.
4, a fourth TF-F310 whose T input terminal is connected to the Q output terminal of the third TF-F2O3, and a fifth TF-F310 whose T input terminal is connected to the output of this fourth TF-F310.
F311, a sixth 7rF F312 whose T terminal input is the output of this fifth TF FCl2, and this sixth T
7th TF-F that uses the output of FF312 as T-terminal input
313 has been added.

36 is a lower limit detection circuit, which includes a two-manpower inverting AND circuit (hereinafter abbreviated as NAND) 315 and a two-manpower NAND circuit 31.
．． It consists of a reset set flip-flop (hereinafter abbreviated as R8F-F) consisting of E3 and NAND317, and the inverted Q output of the third TF-F"306 and the fifth T
The Q output of F-F311 is input to NAND315. In addition, 37 is an upper limit detection circuit, which is a 4-person NAN
R consisting of D318, NAND319 and NAND320
Consists of 8F/Fl and inverter 321,
Inverted Q output of third TF-F30E3, fourth TF-F
The Q output of 310, the Q output of 5th TF-FC12, and the Q output of 7th TF-F313 are 4-man power NAND31
8 is entered.

Further, the holding circuit 35a is connected to the third DF- in FIG.
F2O3, fourth DF-F2O3, fifth DF-F2O
3 is replaced with a DF-F with a set terminal and a reset terminal to create a sixth DF-F 307 aN seventh DF
-F308a and an eighth DF-F309a, the output of the lower limit detection circuit 36 is connected to each reset terminal, and the output of the upper limit detection circuit 37 is connected to each set terminal.

Now, the operation of the information reproducing apparatus of this embodiment configured as described above will be explained, focusing on the changed parts.

As explained in the embodiment of FIG.
The run length t is defined as an integral multiple of IT as the smallest unit. The range in which such an integer multiple relationship is established is the case where the run length t of each code is in the following range.

KT-0,5T≦t<KT+0゜5T Here, since K is 3≦≦11, the minimum value tmin and maximum value tmax of the run length t of the reproduction information signal Si are tmln=2
．． It is given by 5T tmax = 11.5T.

Therefore, t<2.5T...(6
) or t>11.5T...(7)
As is clear from the relationship in equation (1), the run length t in the range of is generated when the rotational frequency ω of the motor 47 is
This is a case in which -18 = significant deviation from the rotational frequency ω0 during information recording.

That is, equation (6) indicates that the motor 47 is in the runaway state, and equation (7) indicates that the motor 47 is in the starting state. The lower limit detection circuit 36 detects the range of equation (6),
The one-limit detection circuit 37 detects the range of equation (7).

Now, in the lower limit detection circuit 36, the information pulse signal Sp
The logic is inverted via the inverter 314, and the NAND
317. On the other hand, the output S3 of NAND315
is input to NAND31B. Here, the third T
Inverted Q output of F-F2O3 and fifth TF-F311
It is 2.5T after the information pulse signal Sp becomes L that the Q outputs of both become H. I want to, NAN
The output S3 of the D315 becomes L for the first time 2.5T after the information pulse signal sp is generated. Therefore, NAND31 becomes L after 2.5T from the input of the information pulse signal Sp.
7 output S5 can be obtained.

This S5 is supplied to the holding circuit 35a.

Similarly, in the second limit mountain inspection circuit 37, the third TF/F2
Inverted Q output of O3, Q output of fourth TF-F310, Q output of fifth TF-F311, and seventh TF-F31
The reason why both Q outputs of 3 are H is that the information pulse signal Sp
This is 11.5T after the current becomes L. therefore,
The output S4 of the four-man power NAND318 is the information pulse signal S
It becomes L for the first time 11.5T after p occurs. Therefore, the output S6 of the NAND 320 which becomes L after 11.5T from the input of the information pulse signal Sp can be obtained.

The output of this NAND 320 has its logic inverted by an inverter 321 and is supplied to the holding circuit 35a. By these operations, the sixth DF-F307a and the seventh
Q output of DF-F308a and eighth DF-F30
The Q output of 9a becomes "-4" while the signal S5 is H, regardless of the input to the D terminal, and becomes "+3" while the signal S7 is H, regardless of the input to the D terminal. Therefore, the output of the holding circuit 35a can obtain input/output characteristics as shown in FIG.

As described above, according to this embodiment, the output can be maintained at full acceleration when the motor 47 is started, and can be maintained at full deceleration when the motor 47 runs out of control. Therefore, more stable speed control can be performed than in the embodiment shown in FIG.

In addition, in the following explanation, an example has been described in which the embodiment is implemented using a digital circuit, but an analog circuit may also be used.

Further, although the case where EFM digital codes are recorded has been described, it functions in exactly the same way even if codes such as 8-10 conversion or MFM are used.

Furthermore, the field of application of the present invention is not limited to devices that reproduce disk-shaped information recording carriers using optical heads, but can also be applied to devices that reproduce magnetic disks. In addition, when the information recording carrier is a tape, essentially the same operation can be obtained by replacing the rotational speed control of a rotating head motor or the rotational control of a capstan motor or reel motor for tape feeding. be able to.

In addition, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist of the invention.

Effects of the Invention As described above, the present invention provides redundant means for detecting the relative velocity error between the information recording carrier and the playback head from the playback information signal, so that the playback head can be detected by using all edges of the playback information signal. The relative speed error between the information track and the information track can be detected, and the relative speed error can be quickly corrected over a wide range of speed errors, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the input/output relationship of the main surplus means in the embodiment of FIG. 1, and FIG. 5 is a diagram showing another embodiment of the present invention. FIG. 6 is a block diagram of the information reproducing apparatus in the example, FIG. 6 is an operation waveform diagram of the main part of the embodiment of FIG. 5, and FIG. 7 is a diagram showing the input/output relationship of the remainder means in the embodiment of FIG. 5. DESCRIPTION OF SYMBOLS 1... Information recording carrier, 2... Playback head, 3...
... Surplus means, 4... Control means.

Claims (3)

[Claims] (1) reading an information signal from an information record carrier on which an information signal divided into predetermined units is recorded on an information track;
a playback head that outputs a playback information signal; a remainder means that detects a surplus component between a unit into which this playback information signal is divided and a predetermined reference unit; An information reproducing apparatus comprising: control means for changing the relative speed between a reproducing head and the information track. (2) A playback head that reads out an information signal from an information recording carrier on which an information signal having a cycle that is an integral multiple of a predetermined unit cycle is recorded, and obtains a reproduced information signal; a reference period generating means for generating a reference period; a remainder calculation means for measuring the period of the reproduction information signal according to the reference period signal and detecting a remainder component modulo the unit period; and an output of the remainder calculation means. An information reproducing apparatus comprising: a holding means for holding the information for a predetermined period; and a control means for changing the relative speed between the reproducing head and the information track in accordance with the output of the holding means. (3) having a period that is an integral multiple of a predetermined unit period;
and a reproducing head for obtaining a reproduced information signal by reading out an information signal from an information recording carrier on which an information signal having upper and lower limits of the period is recorded, and a reference period generator for generating a reference period signal proportional to the unit period. means, a remainder calculation means for measuring the period of the reproduction information signal according to the reference period signal to obtain a period measurement signal, and detecting a remainder component of the period measurement signal modulo the unit period; holding means for holding the output of the arithmetic means, lower limit detection means for detecting that the period measurement signal exceeds a first value proportional to the lower limit, and second value for which the period measurement signal is proportional to the upper limit. upper limit detection means for detecting that a value has been exceeded; setting means for setting the output of the holding means to a predetermined value according to the outputs of the upper limit detection means and the upper limit detection means; and the output of the setting means. An information reproducing apparatus comprising: control means for changing the relative speed between the reproducing head and the information track in accordance with the information reproducing apparatus.