JPH0459699B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for reproducing a disc such as a compact disc on which a PCM audio signal is recorded.

Background Art and Problems There are known signal detection methods for PCM audio disks, such as optical and capacitive. By the way, there are two methods for recording audio PCM signals on a disk: a method of recording at a constant angular velocity and a method of recording at a constant linear velocity. From the viewpoint of increasing the recording density, recording at a constant linear velocity is preferable. A disc on which recording is performed at a constant linear velocity still needs to be reproduced at a constant linear velocity.

As an example of a rotation control method that keeps the linear velocity of the disk constant during playback, a method was previously proposed that uses a playback signal from the disk to perform rotation control that keeps the linear velocity of the disk constant. .

To explain an example of the device proposed earlier,
In this case, the following points are taken into consideration:

When recording audio PCM signals,
When recording in baseband that does not rely on carrier modulation methods such as AM modulation or FM modulation, run length limited code is usually used.
code) modulation method is used. This modulation method uses the minimum inversion interval (i.e., the minimum period during which the signal is inverted) between two data transitions for data "0" or "1".
In addition to increasing Tmin and increasing recording efficiency,
The maximum inversion interval (maximum period during which a signal is inverted) Tmax is shortened to facilitate self-clocking on the reproduction side.

In the future, the device detects the deviation of the maximum or minimum reversal interval from the standard value of the linear velocity, and uses this information as information to perform speed servo.

In this case, taking advantage of the fact that a modulated output with consecutive maximum inversion intervals Tmax does not appear in normal modulation, a bit pattern in which the maximum inversion intervals Tmax are continuous twice is used as a frame synchronization signal. Therefore, considering that this frame synchronization signal always appears during one frame period, the maximum inversion interval is
Control so that Tmax becomes the reference value.

For example, in the case of an EFM signal, the maximum inversion interval
Tmax is 11T _C (T _C is channel clock time)
It is said that

FIG. 1 shows an example in which the previously proposed reproducing apparatus is applied to a disc reproducing apparatus using an optical signal detection method.

In the figure, 1 is a photodetector from which a reproduced PCM signal S _P having a roughly sinusoidal waveform is obtained. This signal S _P is supplied to the waveform conversion circuit 3 through the amplifier 2, which converts the recording signal "1"
A signal So corresponding to "0" (Fig. 2 A) is obtained,
It is led out to the output terminal 4. This signal So is also
This signal is supplied to an edge extraction circuit 5 consisting of a differentiating circuit or the like, and pulses PI (FIG. 2B) of the rising and falling edges of this signal So are obtained.

This pulse PI is supplied to the base of the reset transistor 6T of the integrating circuit 6. That is,
In this integrating circuit 6, a current I flows from a constant current source 6A to a charging/discharging capacitor 6C, this capacitor is charged, and the charging voltage rises with a constant slope. When the pulse PI is supplied to the transistor 6T, the transistor is turned on by the pulse PI, and the charging voltage of the capacitor 6c is instantly discharged. Therefore, from this integrating circuit 6, a sawtooth wave voltage whose peak level corresponds to the length of the inversion interval of the signal So is generated.
SA (Figure 2C) is obtained.

This sawtooth wave voltage S is supplied to a peak hold circuit 8 through a buffer amplifier 7. That is, the output voltage of buffer amplifier 7 is
Capacitor 8C is charged through D, and resistor 8R
It is discharged with a time constant determined by this capacitor 8C, and the time constant of this discharge is several times to 10 times the repetition period of the data frame of the reproduced signal.
Since it is selected to be approximately twice as large, the peak value of the sawtooth wave voltage SA is held.

Here, since the frame synchronization signal appears once per period of the data frame, the output signal PH of the peak hold circuit 8 (Fig. 2D) has a level corresponding to the length of the maximum inversion interval Tmax in the reproduced signal. . Therefore, the level of the signal obtained from the peak hold circuit 8 when the inversion interval is exactly 11T _C is taken as the speed reference voltage E _S , and this speed reference voltage E _S and the output signal PH of the peak hold circuit 8 are
By detecting the level difference between the linear velocity and the linear velocity during recording, it is possible to detect the amount of deviation of the reproducing rotational speed from the linear velocity during recording.

Therefore, in this case, the output PH of the peak hold circuit 8 is supplied to the comparison circuit 7, and this comparison circuit 7
The difference from the speed reference voltage _ES is detected at . and,
The output signal of the comparator circuit 7 controls a spindle motor 10 that rotates the disk.

In this way, the disk is rotated at a constant linear velocity using the reproduced signal.

However, in this case, if the reproduced signal is lost due to scratches on the disk, the pulse PI will no longer be present at the output of the edge extraction circuit 5 during this period. When this signal loss period exceeds 11T _C ,
Since the capacitor 6C of the integrating circuit 6 continues to be charged, the peak hold circuit 8 is charged as shown in FIG. 2D.
The output voltage PH will become significantly higher. As a result, there was a risk that the motor would lose control and run out of control. In addition, when performing high-speed access to find the beginning of a desired song, etc., the pick-up crosses multiple tracks, and when this crosses, a signal-deficient section occurs, and in this case, the same problem as above occurs. A problem arises.

OBJECTS OF THE INVENTION It is an object of the present invention to enable a disk to be stably driven at a constant linear velocity even if a period longer than the maximum reversal interval occurs due to lack of signals as described above.

SUMMARY OF THE INVENTION In the present invention, the length of the reversal interval of a reproduced signal is measured by counting clocks having a frequency sufficiently higher than the highest frequency of the reproduced signal within the reversal interval. Then, the maximum value of the measured count value of the reversal interval within a certain period is latched, and the minimum value of the latched maximum values for a period sufficiently longer than the above-mentioned certain period is latched, and this minimum value is used to drive the spindle motor. The spindle motor is driven by the difference between the voltage and the reference voltage.

In this way, even if a signal loss occurs, if the correct maximum inversion interval of 11T _C in the reproduced signal is detected even once in a period sufficiently longer than the above-mentioned fixed period, the detected value can be compared with the reference voltage value. Since the spindle motor is driven by the output, this motor will not run out of control.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. 3, taking as an example the case of the above-mentioned optical signal detection type disc playback device.

In this example, the reversal interval of the reproduced PCM signal is digitally detected using a counter, and the drive signal for the spindle motor is obtained by digital signal processing.

That is, the edge pulse PI from the edge extraction circuit 5 is delayed by a certain amount of time shorter than the minimum value of the edge interval by the delay circuit 11, and then sent to the counter 1.
2 reset terminal. Further, a clock signal having a frequency sufficiently higher than the highest frequency of the reproduced PCM signal is supplied from the clock generator 13 to the clock terminal of the counter 12. Therefore,
This counter 12 counts the number of clocks from one edge to the next, that is, the number of clocks included within the reversal interval. Then, the count value A is latched in the latch circuit 14 before the counter 12 is reset by the edge pulse PI from the edge extraction circuit 5. Then, the maximum value of this count value A within a certain period _P1 , in this example, the maximum value within a period equal to the repetition period T _F of the reproduction frame synchronization signal during normal reproduction, is determined by the latch circuit 15 and the magnitude comparison circuit 16.
It is detected by the latch circuit 17 and latched by the latch circuit 17.

That is, after the pulse SF of period T _F passes through the input terminal 18 and is slightly delayed by the delay circuit 17,
This pulse SF is supplied to the latch circuit 15, and the latch circuit 15 is cleared by this pulse SF. and,
The latch output B of the latch circuit 15 and the latch output A of the latch circuit 14 are compared in the magnitude comparison circuit 18, and when the count value becomes A>B, the latch circuit 1
The latch output A at that time is latched at 5. Immediately before this latch circuit 15 is cleared next time, the latch output B at that time is latched in the latch circuit 19 by the pulse SF. In this way, the count value C of the maximum edge interval within the period _P1 is latched in the latch circuit 19.

Next, the minimum value of the count value C within the period P ₂ which is longer than the maximum value of the possible signal absence period by at least the above-mentioned fixed period P ₁ , in this example, 10 times the period T _F is determined by the latch circuit 20 and It is detected by the magnitude comparator circuit 21, and the value E is detected by the latch circuit 2.
It is latched at 2.

That is, a pulse SR with a period 10 times the period T _F is passed through the input terminal 23 and after being slightly delayed in the delay circuit 24, is supplied to the latch circuit 20, and the latch circuit 20 is set by this pulse SR. Ru. Then, the output D of the latch circuit 20 and the output C of the latch circuit 17 are compared by the magnitude comparison circuit 21, and when the count value becomes C<D, the output C at that time is latched in the latch circuit 20. Immediately before this latch circuit 20 is next set by the delayed pulse of the pulse SR, the latch output D at that time is set to the latch circuit 20 by the pulse SR.
It is latched at 2. In this way, this latch circuit 2
2, the minimum count value E within the period _P2 among _the maximum edge intervals within the period P1 is latched.

The count value E obtained in the latch circuit 22 in this way is determined by the maximum inversion interval in the reproduction signal from the reference count value generation circuit 26 in the comparison circuit 25.
11T _C is compared with a reference count value equal to the count value of the counter 12, and the comparison output is sent to the spindle motor 2 through the drive circuit 27.
8 to control the speed of this motor 28.

During normal playback, if there is no signal loss due to a disk defect, etc., there is always a frame synchronization signal with a maximum inversion interval of _11TC within the period _P1 , and there is no interval longer than this, so the latch circuit The count value C latched in the latch circuit 22 is always the count value of the edge interval of this frame synchronization signal, and the same is true for the count value E latched in the latch circuit 22. Therefore, the motor 28
is speed controlled so that the edge interval of this frame synchronization signal becomes the maximum inversion interval value _11TC . In other words, the disk is controlled to rotate at a constant linear velocity.

In this state of rotation with constant linear velocity,
When a signal loss occurs due to a defective disk, etc., the signal loss period is normally greater than 11T _C , so the count value C latched by the latch circuit 17 is a measurement count of the length of this signal loss period. Becomes a value. However, since the count value E latched by the latch circuit 22 is the minimum value of the count value C within the long period _P2 , if the period _P2 is longer than the signal absent period by more than the period _P1 ,
This count value E becomes the count value of the edge interval of the frame synchronization signal. Therefore, even if a lack of signal occurs, the motor 28 will not be controlled so that the maximum reversal interval is _11TC , and the motor 28 will drive stably.

The above fixed period P ₁ and a sufficiently longer period P ₂
is selected as appropriate; however, during normal playback, period P ₁ is approximately 1 to 10 frame cycles, and data loss due to a disk defect, etc. is approximately 1 msec at most, so period P 1 is selected as appropriate. ₂ is 10
The value is selected to be approximately several tens of frame period periods.

Note that when the speed of high-speed access such as finding the beginning of a song is relatively slow, for example, when the access time from the innermost track to the outermost track is about 3 seconds, the period P ₁
and P ₂ may be the same as during normal playback, but when the access time from the innermost circumference to the outermost circumference becomes fast, e.g. about 1 second, the period P ₁ must be selected as follows. .

In other words, when performing high-speed access, the pick-up crosses multiple tracks, and when it crosses it, a signal loss period occurs, but as the access time becomes faster as described above, the period of appearance of this signal loss period becomes shorter than the frame during normal playback. It is shorter than the period of the synchronization signal. Then, latch circuit 1 of the example shown in the figure
The count value C latched at 7 will always be the count value of the length of the signal absence period within the period _P2 , and therefore the count value E latched by the latch circuit 22 will also be the value of the signal absence period. , the motor 28 is controlled so that this signal absence period is _11TC . Therefore, when performing such high-speed access, the period _P1 is selected to be shorter than the period of appearance of the signal-absent period.
Practically, in the example of FIG. 3, the signal supplied from the input terminal 18 may be switched between normal playback and high-speed access. In this case, the period _P2 may be switched to a shorter period during high-speed access than during normal playback, but there is no problem even if it is the same as during normal playback.

In the above example, the motor 28 is driven by the difference between the reference count value from the comparator circuit 25 and the count value E which is the output of the latch circuit 22, but instead of driving by the difference like this, When the count value E is larger than the reference value, the rotation speed of the motor 28 may be increased, and when it is smaller than the reference value, the rotation speed of the motor 28 may be reduced.

Effects of the Invention This invention does not directly use the detected value of the maximum reversal interval in the reproduced signal to control the linear velocity at a constant speed, but uses the minimum value of the detected value of the maximum reversal interval over a long period of time to control the linear velocity. Since it is controlled, even if there is a lack of signal due to a defect in the disk, the rotational speed of the disk remains stable without being disturbed, and no runaway occurs.

Moreover, since the speed control circuit of this invention is configured digitally, it is possible to eliminate the need for adjustment.
This has the effect of making it easier to convert to digital ICs.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of an example of the essential parts of the previously proposed disc playback device, Fig. 2 is a waveform diagram for explaining the same, and Fig. 3 is a system diagram of an example of the main parts of the device of this invention. . 5 is an edge extraction circuit, 12 is a counter for measuring the reversal interval, 13 is a clock generator, 17 is a first latch circuit, 22 is a second latch circuit, 25
2 is a comparison circuit, 26 is a reference count value generation circuit, 2
8 is a spindle motor.

Claims (1)

[Claims] 1 Modulated with run-length limited code
In a device that reproduces a disc on which PCM signals are recorded at a constant linear velocity, the interval at which the reproduced PCM signal is inverted is
a counter for counting and measuring clocks with a frequency sufficiently higher than the highest frequency of the signal; a first latch circuit for latching the maximum value of the measured count value of the counter for each fixed period; a second latch circuit that latches the minimum value of the count values latched in the first latch circuit during the period, and a second latch circuit that latches the minimum value of the count values latched in the first latch circuit; A disc playback device configured to drive a spindle motor for driving the disc.