JPS6062889A - Controller for motor - Google Patents

Abstract

PURPOSE:To control the rotation of a motor without digitally demodulating a data synchronizing signal by providing a comparison signal generator for generating a comparison signal of different frequencies corresponding to the output of a speed detector. CONSTITUTION:The output of a speed detector 2 is inputted to a comparison signal generator 6. When the speed of a recording medium D is slower than the prescribed value. a frequency signal lower than a reference frequency signal is outputted; when faster, a frequency signal higher than the reference signal is outputted; and when the prescribed speed, a frequency signal equal to the reference signal is outputted as a comparison signal SR. A comparator 8 for comparing the signal SR with the reference frequency SS is provided, and a motor 12 is controlled by the output of the comparator.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a control device for a motor for driving a recording medium such as a disk.

In conventional technical information recording discs, such as optical video discs, FMi tone signals are recorded as bits arranged in a spiral pattern on the surface of the disc. In addition to recording video information, this type of disc records audio sub-information as a PCM signal by taking advantage of its broadband characteristics, and is being actively developed as a Wagyu Zuru FCM disc. In this case, the digital data is modulated using an appropriate digital I modulation method such as 8/1.
It is conceivable to record data on a disk using 4-modulation (converting 8-bit data to 14-bit data, called EFM modulation). In addition, conventionally, recording and reproduction of information recording disks such as video discs, PCM discs, and f-screen discs are performed by keeping the rotational speed constant, so the linear recording density is determined by the linear recording density at the innermost circumference. Due to this limitation, it is necessary to have several times more margin at the outermost periphery, which results in waste.

For this reason, there are information recording discs in which the rotational speed is varied between the outer and inner peripheries so that the linear velocity remains constant, and efforts are being made to extend the recording time or make the disc smaller. If the linear velocity is not constant (Z), the rotational speed must be constantly and continuously changed as the shaft moves from the outer periphery to the inner periphery or from the inner periphery to the outer periphery.

By the way, there are various types of PCM signal formats, but generally there is one that consists of a data synchronization signal and a data section. The 1u frame shown in FIG. 2 is composed of data synchronization bits and data bits. The data synchronization signal is used as a comparison signal for a motor control circuit for continuously changing the rotational speed of a disk whose linear velocity is constant, and as a signal for defining the starting point of the data portion. By the way, when playing a signal recorded using a digital modulation method using a disk with a constant linear velocity, digital demodulation is performed using a phase-locked loop (PLL), etc. Unless the rotation speed reaches a predetermined number, the double cylinder on the device (data synchronization signal, data) cannot be generated. Therefore, it is extremely difficult to control the rotational speed of the motor with high accuracy using the data synchronization signal.

Now, in the prior art, a technique for comparing a reproduced PCM signal with a reference frequency signal and controlling the rotation of a motor using the comparison output is disclosed in Japanese Patent Laid-Open No. 71856/1983.

C. Problems to be Solved by the Invention The present invention provides a novel motor control device that controls the rotation of a motor without digital demodulation and without using the reproduced PCΔ1 signal as in the prior art. be.

2. Means for solving the problem: A speed detection circuit that detects whether the recording medium is running at a predetermined speed, and a black frequency corresponding to the output of this speed detection circuit. A comparison signal generation circuit for generating a comparison signal is provided.

From this comparison signal generation circuit, when the speed of the recording medium is slower than a predetermined speed (L is a frequency signal lower than the reference frequency signal, a higher frequency signal when j!l! A frequency signal equal to the frequency signal is output as a comparison signal.A comparison circuit is provided to compare the comparator with a reference frequency, and the motor is controlled by the output of this comparison circuit. .

E. Operation When the running speed of the recording medium is slow, a comparator circuit with a frequency lower than the reference frequency is compared with the reference frequency, and a signal to increase the motor rotation speed is output from the comparator circuit. If the motor rotation speed is fast, the comparison circuit outputs a signal to lower the motor rotation speed. Thus, the rotational speed of the motor is controlled so that the traveling speed of the recording medium becomes a predetermined speed.

Embodiment FIG. 1 shows a block diagram of a motor control device according to the present invention. The signal 8 recorded on the disk (1) is reproduced by the pickup (1) and input to the rotational speed detection circuit (2). In the rotation speed detection circuit (2), it is detected whether or not the disk (D) is running at a predetermined speed based on the raw signal, and a signal is sent to the comparison signal generation circuit (3). Outputs a control signal (SC).

The comparison signal generation circuit (3) generates comparison signals (SR) of different frequencies in response to the control signal (8C). This comparison signal (8n) and reference signal (8g) are connected to the comparison circuit (8).
It is compared in. The reference signal '1j (88) is a high IE+-
#-Z > 1-Ir? h tlsu-76)5JJ
Assume that the frequency of the reference signal (Ss) is 7.35KIiZ. This frequency is the frequency of the data synchronization signal when the disk is rotating at a normal rotational speed.

The comparison signal and the reference signal are compared in the phase comparator (8), and the error output is applied to the motor signal through a low-pass filter circle, thereby controlling the rotation of the motor (121) and controlling the rotation of the motor (121) to a specified level. That is, the pickup (1), comparison signal generation circuit (3), phase comparison circuit (8), crystal oscillation circuit (9), frequency divider QOI,
The low-pass filter 01) and the motor (2) constitute a PLL (03), and the rotation of the motor (12+) is controlled stably and accurately.

Below, the rotation speed detection circuit (2) and comparison signal generation circuit (
3) will be explained in detail.

In this embodiment, one frame consists of 588 channel bits, of which 4 channel pits are allocated to data synchronization signals. The data synchronization signal includes one cycle of pulses of 11 channel bits (see FIG. 2). Digital data is recorded in the EFM scale as mentioned above. In the EFM scale, 8 data bits of data are converted to 14 channel bits of data, but the number of data that can be expressed with 8 bits is Since the amount of data that can be expressed with 14 bits is naturally large, some restrictions can be placed on 14 channel bit data.For example, suppose 14 channel bit data is recorded using the NRZ 1 method. When the signal inversion interval is 6 channel bits or more and 11 channel bits or less, it is possible to impose a constraint (1J).

Thus, in this embodiment, it is assumed that the maximum signal inversion interval is recorded in 11 channel bits.

The rotational speed of the disk is detected by focusing on this maximum signal inversion interval of 111J.

The details of the rotational speed detection circuit (2) are shown in FIG. As mentioned above, the pattern of the data synchronization signal is determined as shown in Figure 2, and the data is EFM modulated and converted into N
If recording is performed using the ILZI method, the maximum signal inversion interval of the signal reproduced by the pickup (1) will be 11 channel bits. Therefore, the maximum signal inversion interval is measured using a counter (19!(20)) using a pulse with a frequency of 4.3218M1iz outputted from the crystal oscillation circuit (9) as a clock pulse.

The data synchronization signal, that is, the frequency of one frame, is as described above.
7.35KllZ, and one frame has 588 channel bits, so the frequency of the pit clock is 35KllZ.
K[lX588=4.3218MHz.

The counter (19) measures the maximum signal inversion interval of the H level, and the counter (19) is used to measure the maximum signal inversion interval of the H level, and the signal reproduced by the pickup (1) is applied to the counter (211) through the inverter (211).
is used to measure the maximum signal inversion interval at L level. That is, counter 09) (3) is in the reset state when the L level signal is applied to the reset terminal, and the counter is in the H
When level 1 is reached, count clock pulses. Now, assuming that the maximum signal inversion interval of H level is being measured by counter 09), the outputs of counter (4) (QA, QB, QcQD) are all "0" and the output of the synand gate (support). is “1”.

Now, if the rotational speed of the disk is below a predetermined speed, the maximum signal (the inversion interval is longer than in the normal case), and the counter 09) measures "11". That is, QA, QC
, QD high output "1", the output of Nantes Gate (23) becomes "O++". Therefore, the output of Nantes Gate (Incorporated) becomes "1°", and the retriggerable one-shot σ cut circuit ( 2)) is triggered and its output (8C) becomes H level.

On the other hand, if the rotational speed of the disk is faster than the predetermined speed, the maximum signal inversion interval will be shorter than in the normal case, and the counter a9) will not measure 11". The output remains "1" and the output of the Nant gate is "O++". Therefore, the one-shit circuit (25+ is never triggered and its output (
8c) becomes L level.

From the output side of the one-shot circuit, a signal (8C) indicating whether the rotational speed of the disk is faster or slower than the normal rotational speed can be obtained.

Furthermore, the metastable period of the one-shot circuit (25) is 136μ.
It shall be at least seconds. In other words, the period (1/7,35
101 seconds = 166 microseconds) or more.

Next, the comparison signal generation circuit (3) will be explained.

In this embodiment, a comparison signal (SR) is created based on the reproduced data synchronization signal. The signal recorded on the disk (D) is reproduced by the pickup (1) (see waveform a in FIG. 4) and input to the FM demodulation circuit (4). Then, this circuit (4) produces an FM signal as shown in the waveform (b) in Figure 4.
Demodulation Shinshichi is obtained. In the case of FM demodulation, J
A demodulated signal (b) of fJ+ can be obtained. By the way, since the data synchronization part has a low frequency in the middle of the reproduced signal,
The demodulated signal has the lowest voltage level, and the frequency of the data part is higher than that of the data synchronization part. The kR signal level becomes higher than the voltage level of the data synchronization section. However, as explained earlier, there is a signal having the same frequency as the data synchronization part in the data part, so that part has the same voltage level as the data synchronization part. Such demodulated signal (
When the signal b) is input to the synchronization separation circuit (5), the low voltage level portion is clamped, and a synchronization signal as shown in waveform (0) in FIG. 4 is obtained. This synchronization signal (C) includes a true synchronization signal and a false synchronization signal.

Now, the synchronization signal (C) is applied to the comparison signal generation circuit (6). In this circuit (6), a synchronization signal (0) and a comparison signal (d
) is created. This relationship is shown in Figure 5 (A) CB )(
C).

FIG. 5(A) shows a case where the disk rotation speed is slower than the predetermined rotation speed. Now, focusing on one synchronization signal (C1),
The pulse signal (C2) that first appears after a predetermined interval (1) apart from the fall of the synchronization signal (C1) is defined as a comparison signal -19 (d2). The predetermined interval (l1i) is defined as the distance from the falling edge of the synchronizing signal to the approximate center position of the next synchronizing signal at a location where the disk is running at a normal speed (second (see figure). Next, the synchronization signal (C3) that first appears after being separated by (1) from the synchronization signal (C2) detected in this manner is defined as a comparison signal (d3). In the following, (1) will include a synchronizing signal (shown as (c)), but its frequency is slower than the regular frequency, and this is used by a comparison circuit that constitutes a phase-locked loop (PLL). If (8) is input, the PLL will operate to increase the rotation speed of the disk.

FIG. 5(B) shows a case where the disk is rotating at a predetermined rotational speed. in this case,.

In the same way as in the case of FIG. 5(A), the first synchronization signal (C) that appears after leaving (1■) can be used as the comparison signal ((1). Then, this comparison signal (d) corresponds to the true synchronization signal (e), and its frequency matches that of the regular one.

FIG. 5(C) shows a case where the disk rotates p faster than the predetermined rotation speed. All synchronization signals (C) are on this side 1
(Therefore, it includes the true synchronization signal υ and the false synchronization signal) as the comparison signal (d). Such a comparison signal 'J°(d) will be higher than the normal frequency. Therefore, if this is input to the PLL, the PLL will operate to slow down the rotational speed of the disk.

The comparison signals (d) and (sR) shown in fc FIG. The comparison signal is created by the comparison signal creation circuit (6).

Details of the comparison signal generation circuit (6) are shown in FIG. Now, assuming that the rotational speed of the disk is slower than the predetermined speed, the output (Sc) of the rotational speed layer detection circuit (2) is at the above-mentioned normal (2) level. Since this output is input to the AND gate □□□ via the inverter α), the AND gate (retain) is not driven, and when other conditions are met, the AND gate (support) is driven. . Now, the crystal oscillation circuit (9
) output clock pulse (frequency 4.3218
When the counter (291) that counts ``M1iZ'' counts ``576'' which corresponds to <111 as described above, the Q1 output becomes ``11'' and the flip-flop (hereinafter F, F
) (support) j is set, and the Q output (C2) is 11
It becomes II. This C2 output is applied to the reset terminal (it) and data input terminal (D) of the D type F, F (Ill). Therefore, the D type F, F (II) is not in the driving state, and the clock input Data is read in response to the rising edge of the clock input applied to the terminal (T).
Since the signal (C) is applied to the T terminal via the inverter ((support)), data (C2) is read in response to the fall of the synchronization signal (C2), and the C3 output becomes "HII".

Since the C3 output is the reset input for F and E (30), the C2 output of F and FΦ immediately becomes "L 11" and D.
Type F, F (311 is reset and C3 output is immediately L)
''. Also, the counter @) is also reset by the C3 output of ``H''. On the other hand, the synchronization signal (C2) is ``R''.
”, the AND gate (all three inputs of 2J are 11
11, so the synchronization signal (C2) is an AND gate example,
It is output as a comparison signal (d2) via OR gate C331'. Now, from this point on, counter @1 again
starts the d1 number from pa0''.

When "576" is counted and the Q1 output becomes "■", F-Ff;IJ is set and the Q2 output ends up as H'. As previously explained, this "573" indicates the position where the next true synchronization signal exists when the disk is rotating at a normal rotational speed. And 1
When the first synchronization signal (03) that appears after the distance of
The comparison signal (d3) is output via the OR game (33). In this way, the synchronization signal that first appears after being separated by 1 inch from one synchronization signal is output as the comparison signal (8R). Note that the pulse of "573" is 162 μsec (=1/4.3218×573 μsec). The above will be more clearly understood by referring to FIG. 7(A).

Next, when the rotational speed of the disk is at a predetermined speed (the output (8c) of the rotational speed detection circuit (2) is H level)
I will explain about it. In this case, the sequence is shown in FIG. 7(B). When the counter counts "576"' and the Q2 output becomes If 11, the synchronization signal (0) is already "H1".
1, and this synchronization signal is always a true synchronization signal (see FIG. 2). Therefore, the AND gate □□□) is created based on this synchronization signal (C),
or game) (comparison 4H4ft output via 33i
The cycle (d') matches the regular synchronization signal cycle of 166 μsec. Also, when the Q2 output starts up, it is already “It”.
The synchronization signal (0) that is ++ is D type F, F (34
1, and its output (Q4) becomes "H'".

Next, if the rotational speed of the disk is higher than the predetermined speed, the output (8c) of the rotational speed detection circuit (2) is at the L level as described above. Therefore, when the AND gate fin is in a drivable state and a synchronization signal (0) is generated, this is output as a comparison signal (d) via the AND gate (5) and the OR gate (marked). That is, all synchronization signals ((
j) are all comparison signals ((1).

In addition to the signal (8c) indicating the rotational state of the iron and disc as described above, the synchronization signal (comparison signal (80) created by (3)) is applied to A of the switch means (7). It will be applied to the comparator circuit (8) via the side contact.

Thus, in PLL Q3), the rotational speed of the disk is controlled to be constant at a predetermined linear speed.

Now, after the disk reaches a predetermined rotational speed, accurate demodulation of digital data becomes possible.

That is, first, a data synchronization detection circuit digitally detects a synchronization signal. This can be done, for example, by demodulating the synchronous clock from the NRZI reproduction signal generated from the pickup using a PLL and further detecting a specific pattern of the synchronous signal. Further, the EFM demodulation circuit 05) converts the data into 8-bit data of 91 originals, and then applies it to the digital processing circuit α6) to perform processing such as detecting and correcting data errors. Thereafter, it is converted into an audio signal (analog signal) by a DA converter Q7). Since the details of these circuits are outside the scope of the present invention, their explanation will be omitted.

By the way, when the disk reached a predetermined rotational speed and a constant linear velocity was achieved, it became possible to digitally detect the data synchronization signal (later, the motor was controlled using this digitally detected synchronization signal, and the hexagonal This is advantageous because if the playback data synchronization signal is lost due to dropout or the like, this loss cannot be compensated for using an analog detection method that uses the FM demodulation circuit (3), but it is possible to compensate for this loss by using a PLL, for example. This is because, in the digital detection method, when the reproduced data synchronization signal is lost, it is possible to generate a compensation data synchronization signal that compensates for this, and by using this, stable and accurate motor control becomes possible. Therefore, in this embodiment, when the predetermined rotational speed detection circuit U mark detects that the disk has reached the normal rotational speed,
The switch means (7) is switched to the B side, and the synchronization signal O) output from the data synchronization detection circuit α0 is connected to the comparison signal 9 (SR).
The configuration is such that the voltage is applied to PLL03).

As mentioned above, when the rotational speed of the disk is a predetermined speed, F, F(
The output (Q4) of 34 becomes "■", and this Q4 output is applied to a predetermined rotational speed detection circuit, a specific example of which is shown in FIG. This circuit consists of a retriggerable one-shot circuit (its metastable MFit is 166 μsec or more) and an integrating circuit (a).

Therefore, as long as the disk maintains its normal rotational speed, the one-shot circuit (35) is continuously triggered and its integral output remains at a predetermined level. This becomes an instruction signal indicating a predetermined rotation of the disk.

Incidentally, even when the rotation of the disk has not reached the predetermined rotation, the synchronization signal (C) may become "If If" by chance before the counter @) counts '573'. In this case, if the Q4 output becomes "11 If", the one-shot circuit (35) will be triggered.

However, since such a state does not occur continuously, the integrated output never reaches the predetermined level at the normal rotation speed.

According to the present invention described above, the rotation of the motor can be controlled without digitally demodulating the data synchronization signal. Furthermore, it is detected whether the running speed of the recording medium is faster than a predetermined speed or not, and based on this detection, a comparison signal with a frequency that is slower, faster, or equal to the reference frequency is created, and this comparison signal is Since the motor is controlled based on the comparison output between the reference signal and the reference signal, the motor can be controlled accurately with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a motor control device according to the present invention, FIG. 2 is a configuration diagram of a frame, FIG. 6 is a diagram showing a rotation speed detection circuit, FIGS. 4 and 5 are operation waveform diagrams, and FIG. The figure shows a comparison signal generation circuit and a predetermined rotational speed detection circuit, and FIG. 7 is an operation waveform diagram of the comparison signal generation circuit. (2) is a rotational speed detection circuit, (3) is a comparison signal generation circuit, and (8) is a comparison circuit. Applicant Sanyo Electric Co., Ltd. Representative Patent Attorney Shizuo Sano

Claims (1)

[Claims] (1) A speed detection circuit that detects whether the recording medium is running at a predetermined speed, and a comparison signal generator that generates comparison signals of different frequencies in response to the output of this speed detection circuit. and a comparison circuit for comparing the comparison signal with a reference signal, and controlling a motor for driving the recording medium based on the output of the comparison circuit.