JPS59124065A - Rotation control circuit of digital audio disk player - Google Patents

Abstract

PURPOSE:To make a coarse adjustment of rotation control over a spindle motor speedily and stably by accelerating the spindle motor when the same signal succeeds by <=3 bits in a reproduced signal and decelerating the motor when the same signal suceeds by >=12 bits. CONSTITUTION:The succession range of the same signal in the format of the reproduced signal is specified between 3 and 11 bits. Therefore, when the rotation of the spindle motor is slow, information recorded as an expanded signal consisting of 11 bits at a maximum is reproduced and the counted value of a counter 4 attains to 12, so that an output signal F is outputted from an output port P2. Consequently, the output signal K of an adding circuit 9 rises to generate an acceleration command. When the rotation becomes fast, on the other hand, the reproduced signal A is reproduced all in a shortened state, so the counted value of the counter 4 does not attain to 12 and the signal F goes down to L. Consequently, the signal K of the circuit 9 drops to generate a deceleration command. The signal K is passed through an LPF10 and supplied as a coarse adjustment signal L to a spindle motor driving circuit.

Description

TECHNICAL FIELD The present invention relates to a digital audio disc player, and more particularly to a rotation control circuit for a spindle motor provided to rotate a disc at a constant linear velocity.

BACKGROUND TECHNOLOGY Digital audio disc players play back discs on which digitized audio signals and synchronization signals are optically recorded at a constant linear velocity at a high density, and have the excellent feature of providing high-fidelity playback. have. Here, the signal format recorded on the disk is determined, for example, as shown in FIG. One frame is made up of a fixed number of bits (for example, 588 bits), and these frames are continuously recorded on the same disk at a constant linear velocity. The signal format in each frame is divided into a synchronization section A and an information section B, and the synchronization section A is positioned at the beginning of each frame.

Furthermore, the synchronization part A is composed of 22 bits as shown in Fig. 1, and the first 11 bits are consecutive non-
When , continuous<11 focus becomes °゛1'',
If the first 11 bits are “1” consecutively, the continuation <11
The bits are set so that they become 01' consecutively. In this case, the first 11 bits are set to be opposite to the last bit of the previous frame, and in this way, the predetermined unit bits (11 pintos) are set to be either "0" or "1". The format in which ``''' is continuous is limited to this synchronization part A in one frame.In other words, the information part B is 11 in any case.
It is configured so that a format in which "1" continues in bits when "On" does not occur.In addition, the information part B always keeps "1" for 3 or more bits in order to prevent conversion to direct current when there is no signal. The signal or log signal is a continuous signal, and therefore, the information portion B is represented as a continuous signal only over the range of 3<B≦11 pits.

With a digital audio disc configured in this way, a high-fidelity reproduction signal can be easily obtained by optically reading and demodulating the digital information on the disc at a constant linear velocity.

In this case, the most important thing for high-fidelity playback is:
The purpose of this method is to control the rotation of the spindle motor according to the position of the pickup so that the rotation of the disk during reproduction is accurately kept at a constant linear velocity.

Here, the rotation control of the spindle motor is performed by two systems: a coarse adjustment system and a fine adjustment system, and the coarse adjustment system performs control using a signal obtained by F-V conversion of the spectrum of the reproduced signal. The fine adjustment system is controlled using the phase comparison output between the bit clock generated in synchronization with the data included in the reproduced signal and the crystal-accurate reference clock, allowing fine adjustment within the range of ±1 factor relative to the reference rotation. are doing.

The coarse adjustment system and fine adjustment system control signals thus generated are added together and then supplied to a motor drive circuit to control the spindle motor. The difference in rotation of the spindle motor when reproducing the inner circumference of the disc and when reproducing the outer circumference is 2.
As a result, the control range has become extremely wide.

However, in the spindle motor control circuit configured as described above, the spectrum of the reproduction signal supplied from the pickup is used to adjust the rotation speed of the spindle motor to within 10 coefficients of normal rotation. The spectrum varies depending on the content of data included in the reproduced signal, and as a result, coarse adjustment may not be possible quickly. In addition, in order to accurately synchronize the sampling clock signal generated in the fine adjustment system with the reproduced signal, a sampling clock generation circuit with a phase-locked loop configuration is used. The lock loop can only synchronize with the reproduced signal when the rotation is within ±10% of the normal rotation, so if the coarse adjustment system is unstable as described above, the sampling clock cannot be generated. There are various problems such as

DISCLOSURE OF THE INVENTION Accordingly, an object of the present invention is to provide a rotation control circuit for a digital audio disc player that can quickly and stably perform coarse adjustment in rotation control of a spindle motor.

In order to achieve such an object, the present invention specifies that in the playback signal format of a digital audio disc, the range in which the same signal continues is specified as 3 bits or more and 11 bits or less, as described above. Focusing on this, the spindle motor is accelerated when the reproduced signal contains a signal with a continuous range of the same signal of less than 3 bits, and when the continuous range of the same signal contains a signal with a continuous range of 12 bits or more. The method performs coarse adjustment control by decelerating the spindle motor.

Therefore, in the rotation control circuit of a digital audio disc player having a coarse adjustment system configured in this way, the rotation speed of the spindle motor can be roughly adjusted regardless of the content of data in the playback signal. In addition, coarse control of the number of rotations can be performed accurately and stably.

△ In addition, in the present invention, since the rotation speed of the spindle motor can be quickly adjusted to within 10% of the normal rotation speed by rough adjustment control, the phase of the sampling clock generation circuit that generates the sampling clock signal is It has various excellent effects, such as improved application of Ronokgaap and the rapid stabilization of rotation of the spindle motor.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 2 is a circuit diagram showing an embodiment of a rotation control circuit for a digital audio disc player according to the present invention. In the figure, 1 is a reference clock signal B (4, This is an AND gate that outputs 3218MHz). 2 is a falling detection circuit that detects the falling edge of the reproduced input signal A; 3 is a rising edge detection circuit that detects the rising edge of the reproduced input signal A; 4 is a counter with a 5-bit configuration; The reference clock signal B' supplied from AND gate 1 after being cleared by
When reaching = 3, an output is generated from output capo-)P+, and n
-12, output is generated from P2. 5 is outputted to the output signal generated from the output port P1 of the counter 4, and is also output to the rising edge detection circuit 3.
a flip-flop circuit reset by the output of 6
is a NOR gate that generates an output when the reproduced input signal A and the cent output signal of the flipping circuit 5 are both "L", and when the continuous part of the reproduced signal A is less than 3 bits long of the reference clock signal B. generates output.

7 is a monostable multivibrator circuit triggered by the output signal of the NOR gate 6, 8 is a monostable multivibrator circuit triggered by the output signal generated from the output port P2 of the counter 4, and 9 is Mi[constant multivibrator circuit 7]. This is an adding circuit that adds and outputs a signal generated from the reset output terminal of the monostable multivibrator circuit 8 and a signal generated from the set output terminal of the monostable multivibrator circuit 8, and is connected between the output terminal of the monostable multivibrator 7 and the ground. It is composed of voltage dividing resistors 9a and 9b connected in series to the resistors 9a and 9b, and a loop prevention diode 9C connected between the output terminal of the monostable monomultivibrator 8 and the connection point X of the resistors 9a and 9b. The potential at this connection point X is used as the addition output. 10 is a low-pass filter that smoothes the output of the adder circuit 9 and sends out a coarse adjustment signal.

In the circuit configured in this way, when the playback operation is started, the clear signal OLS is supplied during the period until the pink-up focus system is stabilized and the signal can be reliably read. The monostable multivibrator circuit 7 is in a reset state. in this case,
Since the monostable multivibrator circuit 7 supplies the reset signal enable to the adder circuit 9 as an output, the adder circuit 9 divides the "H" output of the monostable multivibrator circuit 7 through resistors 9a and 9b. and output it. and,
The output signal of this adder circuit 9 is sent out as a coarse adjustment signal via a low-pass filter 10, and is added to a fine adjustment system signal (not shown) to be supplied as a motor control signal to a spindle motor and drive circuit (not shown). Ru. Then, as the rotation of the spindle motor increases and the above-mentioned claw system becomes stable and the reproduction signal A is output from the pickup, the clear signal CLs is cut off.

Next, when the reproduced signal A shown in FIG. 2(a) is supplied, the rising edge detection circuit 3 and the falling edge detecting circuit 2 detect the rising and falling edges of the reproduced signal A, and detect the rising edge and the falling edge of the reproduced signal A. ) The output signals C and D shown in (C) are generated, the flip-flop circuit 5 is reset by the output signal C, and the counter 4 is cleared by the output signal R.

On the other hand, the AND gate 1 is opened only during the "H" period of the reproduced signal A, and supplies the reference clock signal B at the reference bit rate to the counter 4.

Therefore, the counter 4 sequentially counts the reference clock signal B when it is supplied from the AND gate 1, and this count value n
When n=3, an output signal E is generated from the output capo P+, and when n-12 is reached, an output signal F is generated from the output capo P2. Then, at n-3, the output signal E
is generated, the flip-flop circuit 5 is turned on, so its set output signal G is inverted to IIH'' at time t2 in FIG. 3(d-). Here, the rotation of the spindle motor is If it is slow, the recorded signal specified as a continuous signal in the range of 3 to 11 bits is reproduced as a signal whose time is extended as shown in Fig. 2(a).As a result, the reproduced signal All the "H" periods of A are longer than the 3-bit period of the reference clock signal B, and accordingly, the reproduced signal A becomes nHl and the reference clock signal B becomes 3 bits.
Every time a bit is counted, an output signal E is generated from the counter 4 and a flip-flop circuit 5 is set. and,
Since this flip-flop circuit 5 is reset by the output signal C generated from the rise detection circuit 3 every time the next reproduction signal A rises, the set output signal G is as shown in FIG. 3(d). “L” of the envious reproduction signal A
All the signals become "H" during the ° period. As a result, the output signal H of the NOR gate 6, which detects the condition in which the reproduced signal A and the cent output signal G of the flip-flop circuit 5 are both "L", is in the "L" state as shown in FIG. 3(e). continue.

That is, the fact that the output signal H of the NOR gate 6 is in the "L" state indicates that all the "H" periods of the reproduced signal A are equal to or longer than the 3-bit period of the reference clock signal B.

The fact that all "H" periods of the reproduced signal A are 3-bit periods of the reference clock signal B means that the rotational speed of the spindle motor does not exceed a predetermined linear velocity.

In this way, when the output signal H of the NOR gate 6 continues to be in the "L" state, the monostable multivibrator circuit 7 continues to be in the reset state, and its output signal is in the 1H" state as shown in FIG. 2(f). Continue.

Here, if the rotation of the spindle motor is slow, the information recorded as a signal of up to 11 bits will be extended and reproduced as shown between time points t1 and t4 in FIG. 2(a). As a result, counter 4 is set at time t3.
At this point, the count value n reaches 12, and accordingly, the output signal F from the output port P2 becomes as shown in Fig. 2 (g
) is generated as shown in When the output signal F is generated, the monostable multivibrator circuit 8 is triggered, and the output signal J becomes Hn from the set output terminal Q for a predetermined time T1 as shown in FIG. 3(k). occurs in In this case, the set time T of the monostable multivibrator 8 may be set at least one bit time of the reproduced signal A, and can be arbitrarily set in relation to the control sensitivity. Therefore, during the period tl, the output signal of the monostable multivibrator circuit 7 is "flH" and the output signal J of the monostable multipipe rake circuit 8 is "L".
Therefore, only the output signal (■) is supplied to the adder circuit 9. As a result, the adder circuit 9 divides the output signal (■) by the resistors 9a and 9b, and this divided voltage value vl
is output as an output signal as shown in FIG. 2(i). Then, when time t3 is reached, the output signal J of the monostable multivibrator circuit 8 is supplied to the adder circuit 9 as a speed increase command signal. In the adder circuit 9, since the output signal J is supplied to the connection point X via the diode 9C,
The voltage value of the addition output signal increases to 2 as shown in FIG. 3(1) between time points t3 and t5.

By performing such an operation every time continuous reproduction signal A is supplied over a period of 12 bits or more,
Each time the output signal of the adder circuit 9 rises, a speed increase command is issued. The output signal of the adder circuit 9 is smoothed by a low-pass filter 10 and generated as a coarse adjustment signal, which is supplied to a spindle motor drive circuit (not shown) to perform speed increase control. Then, when there is no continuous part in the reproduced signal A over a period of 12 bits or more, the monostable multivibrator 8 is no longer triggered, so the adder circuit 9 inputs only the output signal of the monostable multivibrator 7 and voltage value v
The normal operation of sending out the output signal K of 1 is restored.

Next, when the linear velocity of the disk becomes faster, the linear velocity increases, and as shown in FIG. 4(a) between time points tl and t2, a continuous portion of less than 3 bit period occurs in the reproduced signal A. . As a result, the output signal E is no longer generated from the counter 4 between time points t1 and t2, and the output signal E is no longer generated at time point t.
The reference clock signal B is generated at time t4 when three clocks are counted during the generation period of the next reproduction signal generated from 3.

Therefore, the flip-flop circuit 5 at least at time t1
A reset state is shown during the period from ~t to l, and during this period, the output signal G generated from the set output terminal Q becomes "L" as shown in FIG. 4(d). As a result, the output signal H of the NOR gate 6, as shown in FIG. That is, it becomes "H" between time points t2 and t3. When the output signal H becomes 'H', the monostable monomultivibrator circuit 7 is triggered, and a predetermined signal is generated as shown in FIG. 4(f). For time T2, the output signal becomes "L" and a deceleration command is issued. In this case, the operating time T2 of the monostable multivibrator circuit 7 may be at least one bit time of the reproduced signal A, and its length can be arbitrarily set in relation to the required control sensitivity.

On the other hand, the count value n of the counter 4 cannot reach 12, perhaps because the reproduction signal A is reproduced in a shortened state, perhaps in a state where the linear velocity of the disc is high as described above. Accordingly, the output signal F generated from the output capacitor P2 continues to be in the "L" state as shown in FIG. 4(b). Therefore, the output signal J of the monostable multivibrator circuit 8 triggered by the output signal F also continues in the 1Ln state as shown in FIG.

As a result, the adder circuit 9 has both output signals, and J is from time t2 to
IIL'' during time t5, the addition output signal also decreases to the voltage value vo as shown in FIG. 4 (1), and a deceleration command is issued. The output signal is smoothed by a low-pass filter 1o, and then supplied as a rough adjustment signal to a spindle motor drive circuit (not shown) to perform deceleration control and maintain the linear velocity at a predetermined constant value. can be adjusted to

Next, when the monostable monomultivibrator circuit 7 is triggered during the operation period of the monostable multivibrator 8, the output signal J becomes l'H'' and the output signal becomes l'L'', and accordingly, A state where the speed increase command and the deceleration command are issued at the same time occurs, especially when the operation time of the monostable multivibrator circuit 8 is set to be long. In this case, the output signal J is supplied to the connection point X via the diode 9c and is pulled to ground via the resistors 9a and 9b, so that the output signal is lowered and priority is given to deceleration. On the other hand, when the output signal is IH'', the output signal J is °'
In the case of "L", the diode 9c prevents recirculation.

Therefore, in a circuit configured in this way, the information recorded on the disk is represented only by a continuous signal of 3 bits or more and 11 bits or less, and the continuous part of the reproduced signal is expressed as 12 bits. If it detects that the time is longer than the time, it sends out a speed-up signal, and if the continuous part is less than 3 bit times, it sends out a deceleration signal.
Unlike the conventional method, this system is not affected by fluctuations in the data contained in the reproduced signal at all.

In the above embodiment, a case was explained in which the reference clock signal B was made to match the bit rate of the recording signal, but each continuous signal period in the reproduced signal A can be measured in relation to the counter. For example, if the reference clock signal B is 8.6436MH2, the output capo P+ of the counter 4 will send out the output signal E when the count value n reaches 6, and the output capo P2 It is only necessary to change the output signal F to generate the output signal F when the count value n reaches 24.

As explained above, the rotation control circuit of the digital audio disc player according to the present invention issues a deceleration command when the continuous period of the reproduced signal is less than a predetermined 3 bit period, and If the predetermined 11-bit period is exceeded, a speed increase command is issued to perform rotation control to keep the linear velocity constant. Therefore, it is completely unaffected by data fluctuations in the reproduced signal as in the past, and this has the excellent effect of quickly and stably controlling the rotation of the spindle motor to maintain a constant linear velocity. has.

[Brief explanation of the drawing]

Fig. i is a diagram showing the signal format of a digital audio disc, Fig. 2 is a circuit diagram showing an embodiment of a rotation control circuit for a digital audio disc according to the present invention, and Figs. 3(a) to ( 1), Figure 4(a)-(1)
2 is an operational waveform diagram of each part of the circuit shown in FIG. 2. FIG. 1...AND gate, 2...fall detection circuit, 3...
Rise detection circuit, 4... Counter, 5... Norinob flop circuit, 6... NOR gate, 7, 8... Monostable multivibrator circuit, 9... Adder circuit, 10...
...Low pass filter. (f) l ”Pi Figure 3 (9) F”L”-11111111111 (h)
T”L” Figure 4

Claims (1)

[Claims] a counter that counts the number of reference clock signals in each continuous period of the reproduction signal supplied from the pickup; and a counter that is reset at the rising edge of the reproduction signal and output when the counter counts 3 bit periods during recording. a flip-flop circuit that is set by a signal that is set by a signal, a gate circuit that detects a positive state of the flip-flop circuit at the end of a continuous period of the reproduced signal, and a predetermined period triggered by the output of this gate circuit. a first monostable multivibrator circuit that cuts off the output signal over a predetermined period of time, and is triggered by a signal output when the counter counts a 12-bit period during recording to generate an output signal over a predetermined period; a second monostable multivibrator circuit, an adder circuit that adds and outputs the output signals of the first and second monostable multivibrator circuits, and a coarse adjustment signal that smoothes the output signal of the adder circuit. 1. A rotation control circuit for a digital audio disc player, comprising a low-pass filter.