JPH0670739B2 - Line pixel number search method - Google Patents

Description

The present invention relates to a method for searching the total number of pixels in one horizontal scanning period of a digital video signal.

[Prior Art and Problems to be Solved by the Invention] When a printer or the like is connected to a display device used in computer graphics or the like to make a hard copy of a display image, the printer is compatible with each display device. You must adjust each setting value of. At this time, the display device 1
The value of the total number of pixels (hereinafter referred to as the number of line pixels) during the horizontal scanning period must be input, but this value may be unknown. Here, the total number of line images is a number obtained by dividing one horizontal scanning period (one line period) by one pixel (pixel) period, and during one line period when it is assumed that pixels also exist during the blanking period. Is the total number of strokes. Even if the number of effective pixels that can be displayed on one scanning line of the screen of the display device is the same, the horizontal scanning frequency or the ratio of the effective scanning period to the blanking period may differ depending on the display device. / Line) is not always the same.

If the line pixel count is unknown, its value must be measured. For example, a method of measuring and calculating one horizontal scanning cycle and the cycle of one pixel of a digital video signal with an oscilloscope, or creating a digital video signal in which the logical states of adjacent pixels are all different and using this signal with a counter A method such as counting is conceivable, but it is extremely complicated and not practical.

Therefore, it is an object of the present invention to provide a line pixel number search method for automatically obtaining the value when the line pixel number of a digital video signal is unknown.

[Means for Solving the Problems] According to the line pixel number searching method of the present invention, first, one horizontal scanning period (1
A clock signal having a period obtained by equally dividing the line period) by the search variable is generated. That is, since the total number of the clock signals in one line period is equal to the search variable, the value of the search variable may be adjusted to be equal to the number of unknown line pixels. Next, the clock signal is sampled according to the transition of the digital video signal to detect either the first state or the second state. Here, it is assumed that alphanumeric characters or figures are displayed on the display device, and that a sufficiently large number of video signal transitions are present substantially randomly within one screen. The first state of the sampling result means that one of the high-level state and the low-level state of the clock signal is sampled at least once by the transition of the image signal somewhere during one screen period, and the second state. Means that one of the high level state and the low level state of the clock signal could not be sampled even once in all transitions to the image signal of the entire screen of the display device, that is, the entire sampling of the entire screen. It means that the value was the other of the high level state and the low level state. When the number of line pixels and the total number of clock signals in one line do not match, it is assumed that many video signal transitions exist in one screen substantially randomly.
It is considered that the sampling result is always in the first state.
This is the basic idea of the present invention. Next, the sampling operation is performed each time the relative delay time of the clock signal and the digital video signal is delayed by one unit. When the relative delay time exceeds a predetermined time, the search variable is increased. The relative delay time and the search variable are changed until the second state is detected, and the search variable when the second state is detected is equal to the number of line pixels.

Further, according to the present invention, similarly to the above-described method, the clock signal is generated based on the search variable, and the transition of the digital video signal is performed every time the relative delay time of the clock signal and the digital video signal is delayed by one unit. According to the above, the clock signal is sampled to detect either the first state or the second state. The relative delay time when the sampling result changes from the first state to the second state is the first delay time. After that, each time the relative delay time is further delayed by one unit, the clock signal is sampled according to the transition of the digital video signal to detect either the first state or the second state. The relative delay time when the sampling result changes from the second state to the first state is defined as the second delay time. If the relative delay time exceeds the range of the predetermined delay time during the process of obtaining the first and second delay times, the value of the search variable does not match the unknown line pixel number. , Increment the value of the search variable by 1. The above procedure is repeated, and the value of the search variable when both the first and second delay times are obtained within the predetermined time is taken as the number of line pixels to be obtained.

Further, according to the present invention, the reference value determined according to the difference between the first delay time and the second delay time is compared with the value of the search variable at that time, and if the search variable is smaller than the reference value, the search is performed. The variable is further increased and the search process is continued. A search variable larger than the reference value is the number of line pixels to be obtained. This reference value is set to a value larger than half the number of line pixels.

[Operation] According to the line pixel number search method of the present invention, the clock signal based on the search variable is sampled to sample the clock signal based on the search variable in response to the transitions of a large number of digital pixel signals that are present substantially randomly within one screen. The fact that the first state is detected when the phase relationship between the pulse of the pixel signal and the pulse of the clock signal is not proper or when the number of line pixels and the total number of clocks in one line do not match Are using. Therefore, the number of line pixels can be easily obtained by detecting the second state.

A first delay time when the sampling result changes from the first state to the second state and a second delay time when the sampling state changes from the second state to the first state are obtained, and these first and second delay times are obtained. The search variable is set to the number of line pixels. Thereby, the measurement accuracy can be further improved.

The difference between the first and second delay times has a substantially constant ratio with respect to one pixel period and has a substantially constant correlation with the number of line pixels. Therefore, the reference value determined by this value is compared with the value of the search variable. As a result, the number of line pixels can be reliably obtained.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 3 is a block diagram of an embodiment of an apparatus suitable for utilizing the line pixel number searching method of the present invention. This embodiment is applied to a copying apparatus for binarized digital video signals (video signals represented by black and white only).

A digital video signal is supplied to the input terminal 10 from an arbitrary video signal source such as a computer graphic terminal. This video signal is a “high” (logic “1”) or “low” (logic “0”) monochrome binary signal. However, a color signal composed of a plurality of different discontinuous levels may be used, in which case the plurality of levels are "1" or "0".
It is forcibly divided into either. The period of one pixel (pixel) of the video signal changes up to about 8 to 30 nanoseconds depending on the connected display device. This video signal is supplied to the variable delay circuit 16 via the amplifier 12 and the comparator 14. The variable delay circuit 16 is a circuit in which a plurality of delay elements are connected in series and an output terminal of each delay element is selected according to the delay setting signal D. The variable delay circuit 16 is a phase adjusting unit that adjusts the relative phase between the video signal and a sampling clock signal described later.

The video signal from the input terminal 10 is also supplied to the sync separation circuit 18 to separate the vertical sync signal and the horizontal sync signal. The horizontal pulse generation circuit 20 generates horizontal pulses in phase with the horizontal sync signal in response to the horizontal and vertical sync signals from the sync separation circuit 18 or the external horizontal sync signal and the vertical sync signal from the external sync terminals 22 and 24. To do. Note that the amplifier 12 may be provided with a direct current reproducing function, and the horizontal sync signal separated by the sync separation circuit 18 may be supplied to the amplifier 12.

The horizontal pulse from the horizontal pulse generator 20 is supplied to a phase locked loop (PLL) circuit 26 to generate a sampling clock signal SC synchronized with this horizontal pulse. PLL circuit 2
Reference numeral 6 is a circuit of a conventional type composed of a phase comparator 28 including an integrator on the output side, a voltage controlled oscillator (VCO) 30 and a frequency divider 32, and serves as a clock signal generating means. The frequency of this sampling clock signal SC is the search variable (value of the division ratio data) input from the latch 40 to the divider 32.
Depends on That is, the sampling clock signal having a period obtained by equally dividing the period of the horizontal synchronizing signal by the value of the search variable is generated. When this clock signal is adjusted properly,
That is, when the search variable becomes equal to the number of line pixels, one clock period corresponds to one pixel period of the video signal.

The main controller 34 as a control means is a microprocessor, RO
It is composed of M, RAM, etc. and controls the entire apparatus of FIG. Further, the ROM stores programs corresponding to the flowcharts of FIGS. 1 and 2, and the microprocessor executes these programs. Each data from the main controller 34 is latched in the latch circuits 36, 38 and 40. The latch circuit 36 supplies the latched data to the digital-analog converter (DAC) 42 and supplies the threshold voltage to the comparator 14. The latch circuit 38 latches the delay time setting data D to control the delay time of the variable delay circuit 16 and also latches a signal described later. In this embodiment, when the value of the delay time setting data D changes in the range of integer values of 0 to 63, the delay time of the variable delay circuit 16 is changed in the range of 0 to 63 nanoseconds in units of 1 nanosecond. . That is, one nanosecond is one unit of delay time. The latch circuit 40 latches the search variable (frequency division ratio data) for the frequency divider 32 and controls the operation of the frequency divider 32. By changing this search variable, the frequency of the sampling clock signal can be changed, which is used in the line pixel number searching method of the present invention described later.

The latch circuit (D-type flip-flop) 44 which is the first sampling means has an OR gate at its data terminal D.
The output signal of the variable delay circuit 16 is received via 46,
The clock terminal receives the sampling clock signal SC from the PLL circuit 26 via the OR gate 48. The OR gate 48 controls the control signal C from the latch circuit 38.
Also receive.

The latch circuit (D-type flip-flop) 50 which is the second sampling means has an OR gate 48 at its data terminal D.
Output, and the reset terminal R receives the latch signal from the latch circuit 38. Further, the NOR gate 52 inverts the logical sum of the output signal of the OR gate 46 and the Q output signal of the latch circuit 50 via the inverter 54, and the latch circuit 50.
Supply to the clock terminal. The latch circuits 44 and 50
Is D when a rising transition occurs on the clock terminal.
Latch (sampling) the pin level. It is preferable that the latch circuits 44 and 50 have the same characteristics (especially, the same propagation delay time) in the same integrated circuit.

The inverter 56 is energized according to the output signal of the main controller 34, inverts the / Q output signal of the latch circuit 50 (that is, supplies the Q output signal) to the main controller 34.

The sub controller 58 controls a circuit for processing the output signal of the first sampling means in response to an instruction from the main controller 34. These circuits include shift register 60, memory 62, interface 64, and the like. The shift register 60 captures the / Q output signal of the latch circuit 44 via the OR gate 68 as serial data and outputs it as parallel data in response to the sampling clock signal via the OR gates 48 and 70. To do. Sub-controller 58 controls the conduction and non-conduction of OR gates 68 and 70. The memory 62 stores the parallel data from the shift register 60 and outputs the parallel data to the interface 64 according to the address signal and the write / read control signal from the sub controller 58. The interface 64 interfaces between the memory 62 and the printer 66.

FIG. 4 is a waveform diagram showing an example when the frequency relationship and the phase relationship between the digital video signal V and the sampling clock signal SC are adjusted to be substantially optimal. Each section shown by a broken line is one pixel period and corresponds to the cycle of the clock signal. Since the rising transition of the sampling clock signal is approximately in the center of each pixel period, the latch 44 of FIG. 3 can reliably sample the video signal V in response to the sampling clock signal SC. In the case of such an optimum relationship, the rising transition of each pixel signal of the video signal V must be the clock signal SC.
Note that the "low" state of If the phase relationship between the video signal and the sampling clock signal is wrong, or if the number of line pixels and the total number of clock signals on one line are not equal, many pixel signal transitions are present in one screen substantially randomly. If so, the sampling clock signal SC is considered to be in the “high” state at the rising transition of the pixel signal somewhere. The present invention is based on the above facts, and the time of the rising transition of the pixel signal of somewhere is the clock signal of somewhere.
The state in which the SC is in the “high” (logic “1”) state is defined as the first state, and the rising transition points of all pixel signals in one screen are “low” (logic “0”) in the clock signal SC. )) State is defined as a second state. That is, the first state is a state in which the phase or frequency relationship between the pixel signal and the clock signal is not desirable, and the second state represents a state in which the phase and frequency relationship between the two can be appropriate. The first and second states are determined by the main control circuit 34 reading the state of the Q output of the latch 50 shown in FIG. 2, as described later.

FIG. 1 is a flow chart showing a basic embodiment of the present invention.
After the start, in block 100, an initial value is set to the search variable PIXEL which is the value of the frequency division ratio of the frequency divider 32 via the latch 40 of FIG. This initial value may be set manually from the outside or automatically by the main control circuit 34, but it is always set to a value smaller than the desired line pixel number. The initial value of this search variable is preferably a number larger than 1/2 of the value of the number of line pixels to be obtained, which will be described later. In the next block 102, the delay amount D of the variable delay circuit
Is initialized to 0. In the next block 104, the state of C of one input terminal of the OR gate 48 is set to "0" via the latch 38 of FIG. 3, and the clock signal SC is set to the latch circuit 50.
And the clock signal is sampled in accordance with the rising transitions of a large number of pixel signals that are present substantially randomly within one screen. The Q output terminal of the latch 50 is connected to the input terminal of the OR gate 52, and when the Q output becomes "1", the supply of the pixel signal to the latch 50 is cut off. Therefore, if the Q output becomes "1" even once in many sampling operations, the state is latched. The main control circuit 34 reads the state of the Q output from the / Q output terminal via the inverter 56. At this time, if the state of Q is “1”, the state variable P is set to “1”, and this P = “1” is defined as the first state. 1
As a result of sampling the clock signal with all the pixel signals for the screen, when Q does not become "1" even once, P = "0"
And this is defined as the second state. Next decision block 10
At 6, it is determined whether P = “0”. Line pixel count and 1
If the total number of clock signals in the lines does not match or the phase relationship between them is not appropriate, it can be expected that P = “1”. The reason is that if a large number of pixel signal transitions exist in one screen in a substantially random manner, P = “0”
It is considered that it is only when the search variable matches the number of line pixels. Therefore, P = “1”
If it is (first state), a decision block 108 decides whether or not the value of the relative delay amount D is larger than a predetermined value (in this case 63).
If the value of D is 63 or less, the value of D is incremented by 1 in block 110,
The processes 104 to 110 are repeated. If the value of D exceeds 63 in block 108, the value of search variable PIXEL is incremented by 1 in block 112, and the process is returned to block 102. That is, the value of D is changed from 0 to 63 with respect to the value of one search variable, and when P = "0" (second state) is not detected in the value, the search variable is increased by 1 and the search process is advanced. To go. When P = “0” is detected in block 106, the value of the search variable at that time is regarded as equal to the desired number of line pixels, and the process ends in block 114. In the above process, when the search variable has a value that is an integer fraction of the number of line pixels to be obtained, that value may be mistaken for the number of line pixels. Therefore, it is desirable that the initial value of the search variable be a value larger than half the number of line pixels. In many cases, the number of effective display pixels that can be displayed on one scanning line of the screen is known, and since this condition is satisfied, this number of effective display pixels may be used as the initial value of the search variable.

2A to 2F are flowcharts showing another embodiment of the line pixel number searching method of the present invention. FIG. 2A is a main routine, and after starting, block 120 sets an initial value to the search variable PIXEL. Next, the delay time search subroutine 122 determines the first and second delay times D1 and D2. First delay time
D1 is a relative delay time when the result of sampling the state of the clock signal according to the rising transition of the pixel signal changes from the first state to the second state every time the variable delay circuit 16 is sequentially delayed by one unit. Represents the value of D, the second
The delay time D2 represents the value of the relative delay time D when the relative delay time D is further increased after the delay of D1 and changed from the second state to the first state. These first and second delay times D1
And D2 are found, the search variable PIXEL has become equal to the number of line pixels, and the search process ends at block 124. In the delay time search subroutine 102, if the value of the relative delay time D exceeds the predetermined range (63 in this case), the process immediately jumps to block 125 (reference A), and block 126 sets the search variable PIXEL of the search variable PIXEL. The value is incremented by 1 and it is determined in a decision block 128 whether or not the PIXEL value is equal to or less than a predetermined upper limit value (here, 4096). If the PIXEL value exceeds the upper limit value, an unsearchable error message is displayed in block 129. If not, the process returns to block 122, and the above process is repeated until the values of D1 and D2 are obtained within the predetermined range in block 122.

FIG. 2B is a flowchart showing the processing of the delay time search subroutine 122 of FIG. 2A. First, in block 130, the delay amount D of the variable delay circuit 16 is initialized to 0. Next, in the relative phase detection subroutine 132, when the clock signal SC is sampled at the rising transition of the pixel signal V while the value of D is fixed, the sampling result is the first state (P
= “1”) or the second state (P = “0”). In the next decision block 134, it is determined whether or not the state detection variable P is "0". If P = "0", the process proceeds to block 136 of the delay and set subroutine. This delay and enactment subroutine 136 does not calculate the second delay time D2, but is substantially the second delay time search subroutine 14 described later.
Performs the same processing as 0. That is, the delay time D of the variable delay circuit 16 is sequentially increased from the second state of P = “0”, and P =
The value of D is set to the 1st state which becomes "1". As will be described later, if the value of D exceeds 63 during this process,
Immediately after processing, jump to join block 125 of Figure 2A. In decision block 134, it is determined that P = “1”, or in block 1
When P = “1” is set in 36, the process proceeds to the first delay time search subroutine 138. The first delay time search subroutine 118 sequentially delays the value of D from the first state of P = “1”, and the first delay time that is the value of D when the second state of P = “0” is reached. Find D1. Next, the process proceeds to the second delay time search subroutine 140, in which the value of D is further delayed sequentially from the second state of P = "0" and the value of D when changing to the first state of P = "1". The value of the second delay time D2 is obtained. Thereafter, processing returns from block 142 to the main routine of FIG. 2A. As will be described later, if the value of D exceeds a predetermined range of 63 during the processing of the first and second delay time search subroutines 138 and 140, the processing immediately jumps to the combined block 125 of FIG. 2A.

FIG. 2C is a flow chart showing the processing of the relative phase detection subroutine 132 of FIG. 2B. First, at block 144, the latch 50 of the D flip-flop of FIG. 3 is reset via the latch 38. In the next block 146, the vertical sync signal (V
The input terminal C of the OR gate 48 is set to "0" according to the sync signal), and the clock signal SC is input to the D terminal of the latch 50.
To supply. Therefore, the latch 50 is driven by D in response to each rising transition of the pixel signal supplied from the OR gate 46.
Start sampling (latch) of the state of the clock signal at the input terminal. In the next block 148, the main control circuit 34
Activates the inverter 56 to read the Q output of the latch 50. Here, the Q output terminal of the latch 50 is connected to the input terminal of the OR gate 52, and when the Q output becomes “1”, the transition of the pixel signal is not supplied to the latch 50.
It should be noted that if the state of the clock signal SC becomes "1" at some point of the rising transitions of many pixel signals, that state is latched. In the next block 150, it is judged whether the state of the Q output of the latch 50 is "1", and Q =
If “1”, in block 152, P = representing the first state
Set to "1". When P = “1” is set,
This means that the clock signal is in the "1" state at some point of the rising transitions of many pixel signals. When P = “0” in block 130, block 1
At 34, it is determined whether or not the next V sync signal is detected, and unless the next V sync signal is detected, the processes of blocks 148 and 150 are repeated. Upon detection of the next V sync signal, processing proceeds to block 156 to set P = “0” representing the second state. When P = “0” is set, the clock signal is sampled at all rising transitions of a large number of pixel signals existing in one screen, but the clock signal is “1” once at the sampling point. It means that the condition was not reached. In block 152 or 156, P = "1" or P = "0" is set, and the process is returned from the block 158 to the original routine. As will be described later, this relative phase detection subroutine is also used in the first and second delay search subroutines and the delay and setting subroutine.

FIG. 2D shows the first delay time search subroutine 138 of FIG. 2B.
6 is a flowchart showing the processing of FIG. First, the relative delay time of the variable delay circuit 16 is set via the latch 38 based on the value of D. The next relative phase detection subroutine 162 performs exactly the same processing as the subroutine already described in FIG.
When the state or the second state is detected, P = “1” or P =
"0" is set respectively. At the next decision block 164, P
= “0”, block 16 if P = “1”
The value of D is incremented by 1 at 6, and the processing of blocks 160 to 166 is repeated as long as the value of D at block 168 is 63 or less. If the value of D at block 168 exceeds 63, the process immediately jumps to join block 125 of FIG. 2A. When P = “0” in block 164, the value of D at that time is set to the first delay time D in block 170.
Set to 1. Processing returns from the next block 172 to the original routine.

FIG. 2E shows the second delay time search subroutine 140 of FIG. 2B.
6 is a flowchart showing the processing of FIG. The processing of this subroutine is similar to the first delay time search subroutine of FIG. 2D, and the difference is that the decision block 178 determines whether P is “1” and P = “0”. As long as the value of D is incremented by 1 (block 180), unless the value of D exceeds 63, block 1
The processes of 74 to 180 are repeated, and when the value of D exceeds 63, the process immediately jumps to the combining block 125 of FIG. 2A. Block 1
When it is determined at 78 that P = “1”, the value of D at that time is set to the second delay time D2 at block 184, and the process is returned from the block 186 to the original routine. As described above, the second delay time search subroutine of FIG. 2E performs substantially the same processing as the delay and setting subroutine 136 of FIG. 2B.
The only difference is that in the delay and setting subroutine 136 of FIG. 2B, the block 184 for setting the value of the second delay time D2 is omitted.

FIG. 2F is a part of a flow chart showing a procedure to be added to the line search method of the present invention. In the flow chart of FIG. 2A, decision block 188 is placed between subroutine 122 and end block 124.
Insert. In this decision block 188, the search variable PIXEL
Is compared with the reference value E / (D2-D1). Here, the constant E is an experimentally determined constant, and E /
The reference value of (D2-D1) is selected to be at least larger than half the number of line pixels. If this condition is not satisfied, the process immediately proceeds to the combining block 125 in FIG. 2A, and if this condition is satisfied, the search variable is set to the line pixel number, and the process ends. Here, even when the search variable has a value that is an integer fraction of the number of line pixels, the value of (D2-D1) is always 1 pixel period as long as a large number of pixel signal transitions exist at random. On the other hand, it has a substantially constant ratio and has a substantially constant correlation with the number of line pixels. Therefore, it is easy to select the value of E / (D2-D1) to a value larger than 1/2 of the number of line pixels within the range of the target display device. By inserting this decision block 188, it is possible to eliminate the need to limit the initial value of the search variable.

FIG. 5 is a waveform diagram showing the timing relationship between the sampling clock signal SC and the pixel signals V1 to V4 of the digital video signal. The pixel signals V1 to V4 correspond to the case where the relative delay time D is sequentially increased with respect to the sampling clock signal SC, but the sampling clock signal SC and the pixel signals V1 to V4 shown here are Note that it does not represent a pulse, but rather any unspecified pulse in a number of pulses. That is, V1
The specific pulse of is not delayed and becomes the pulse shown in V2, but when the pulse train of the relationship shown by SC and V1 is relatively delayed, any unspecified one in the pulse train It is shown that the relationship between the pulse and the unspecified clock pulse SC becomes as shown by V2. That is, each pixel signal of V1 to V4 does not correspond to the pixel at the same position on the screen. The precondition of the present invention is that a large number of pixel signal transitions exist in one screen in a substantially random manner. When the sampling result of the latch 50 is in the first state (P = “1”), the relationship between the clock signal and the pixel signal is incorrect. Because,
When the number of line pixels and the total number of sampling clock signals SC in one line are not equal, as long as the rising transitions of a large number of pixel signals are present at random in one screen, at least one of the transition times Is inevitably expected to be in the "high" state of the clock signal (ie, P = "1"). At this time, in the method of FIG. 1, the relative delay time is increased so that P = P
If it does not become "0", the search variable is increased, the search process is continued, and the search variable when P = "0" is set as the number of line pixels.

At block 132 of FIG. 2B, when P = "0" is detected,
The relationship between the clock signal SC and the rising transition points of all pixel signals is as shown by V1 in FIG. At this time,
It is highly possible that the number of pulses of the sampling clock signal in one line and the number of line pixels match, and the phase relationship is also appropriate. When P = “0”, the delay and setting subroutine 136 sequentially delays the pulse train of the pixel signal with respect to the clock signal to forcibly establish the phase relationship (P = “1”) such as V2. After that, the pulse train of the pixel signal is further delayed, and the phase relation (P = P = P3) at which the rising transition points of all the pixel signals in one screen are indicated by V3.
The relative delay time D is set to be "0"), and the value is set as the first delay time D1. After that, the relative delay time D
Is delayed, and the value of D is set so that the timing of any rising transition of the pixel signal has the relationship of V4 (P = “1”), and the value is set as the second delay time D2. In this way, when D1 and D2 are obtained, the search variable at that time
The value of PIXEL is the number of line pixels. In order to obtain the number of line pixels with high accuracy, it is necessary that an image is displayed on a screen to a certain extent or more, and transitions of a large number of pixel signals should be present substantially randomly. However, experimentally, even if the image was not displayed on the entire screen, it was possible to completely match the number of line pixels of the search variable simply by randomly displaying alphanumeric characters over one line or more. . In contrast,
If the total number of sampling clock signals SC in one line does not match the number of line pixels, the phase relationship between the two cannot be constant, so be sure to change at any one pixel signal transition in one screen. It is expected that P = “1”. Therefore, in that case, it is considered that the values of D1 and D2 cannot be obtained even if the value of D is changed within a predetermined range. Therefore, if the value of D exceeds 63 during the process, the second A
Jumping to block 125 in the figure, in block 126, the search variable is incremented by 1 to proceed with the search. However, even when the value of the search variable becomes a value obtained by dividing the obtained number of line pixels by an integer, the search variable may be erroneously recognized as being equal to the number of line pixels. Therefore, the initial value of the search variable should be set to a value that is larger than half the number of line pixels to be obtained.
However, by adding the decision block 118 shown in FIG. 2F, the limitation of the initial value of this search variable can be eliminated. Data of an appropriate constant E for determining the reference value may be stored in the ROM and read as needed.

Although the predetermined range of the value of D is 0 to 63 (0 to 63 nanoseconds),
The variable delay range is determined according to one pixel period (about 8 to 30 nanoseconds) determined by the number of line pixels of the target display device and the horizontal scanning period, and is not limited to this value. It is generally sufficient that the predetermined variable delay range is about twice the maximum pixel period.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein,
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the present invention. For example, in this embodiment, each pixel signal has one bit, but in the case of a signal of a plurality of bits for representing a halftone or a color, similar processing may be performed for the bit having a large change. In addition, it is needless to say that the polarity of transition and whether to use positive logic or negative logic for each digital signal can be freely set at the time of design.

[Effect of the Invention] According to the line pixel number search method of the present invention, even if the line pixel number and the effective pixel number of the display device are unknown, by sampling the clock signal according to the image signal,
The number of line pixels of the display device can be automatically measured.

[Brief description of drawings]

FIG. 1 is a flow chart of a basic embodiment of the line pixel number searching method of the present invention, and FIGS. 2A to 2F are flow charts showing other embodiments of the line pixel number searching method of the present invention. FIG. 4 is a block diagram of an image copying apparatus suitable for applying the method of the present invention, and FIG. 4 is a waveform diagram showing an example of a suitable phase and frequency relationship between a sampling clock signal and a video signal,
FIG. 5 is a waveform diagram showing the relative relationship between the clock signal and the image signal for explaining the line pixel number searching method of the present invention.

Claims (3)

[Claims] 1. A line pixel number searching method for searching the total number of pixels in one horizontal scanning period of a digital video signal, comprising: (a) a clock signal having a cycle obtained by equally dividing one horizontal scanning period by a search variable. (B) changing the relative delay time of the clock signal and the digital video signal and the search variable, sampling the clock signal according to the transition of the digital video signal, and at least 1 in one screen period. The first state in which the two sampling values are one of high level and low level,
Alternatively, it is detected whether or not all the sampling values during the one screen period are the second state which is the other of the high level and the low level, and (c) the value of the search variable when the second state is detected is the above. A method for searching the number of line pixels, which is the total number of pixels. 2. A line pixel number searching method for searching the total number of pixels in one horizontal scanning period of a digital video signal, comprising: (a) a clock signal having a cycle obtained by equally dividing one horizontal scanning period by a search variable. The clock signal is generated in response to a horizontal synchronizing signal, and (b) the clock signal is sampled in response to the transition of the digital video signal, and at least 1 in one screen period
Detecting a first state in which one sampling value is one of a high level and a low level, or a second state in which all the sampling values during the one screen period are the other of the high level and a low level; ) The procedure (b) is executed every time the relative delay time of the clock signal and the digital video signal is delayed by one unit, and the first result when the sampling result changes from the first state to the second state The delay time is calculated. (D) The procedure (b) is executed every time the relative delay time is further delayed by one unit, and the second result when the sampling result is changed from the second state to the first state The delay time is calculated. (E) In the middle of the steps (c) and (d), if the relative delay time exceeds the range of the predetermined delay time, the search variable is incremented by 1, and (f) the step Repeat (a) to (e) In return, the value of the search variable when both the first and second delay times are obtained within the predetermined time is the total number of pixels in one horizontal scanning period of the digital video signal. Pixel count search method. 3. When the search variable is larger than a reference value determined according to the difference between the first and second delay times, the value of the search variable is set to the total number of pixels in one horizontal scanning period of the digital video signal. 3. The line pixel number searching method according to claim 2, wherein