JP3427298B2 - Video signal conversion device and LCD device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion device and an LCD (Liquid Crystal Display) device, and more particularly, to a sampling clock frequency of an A / D conversion means for converting an analog video signal into a digital video signal and Video signal converter capable of optimizing phase in a short time and L equipped with the video signal converter
Regarding a CD device.

[0002]

2. Description of the Related Art FIG. 16 is a block diagram showing an example of a conventional LCD device. The LCD device 500 includes, for example, a video amplifier 20 that amplifies an input analog video signal from a personal computer and outputs an output analog video signal, and an A / A that converts the output analog video signal into a digital video signal.
It includes a D converter 21, an LCD panel drive circuit A for driving the LCD panel P according to a digital video signal, and an LCD panel P for displaying an image.

Further, the LCD device 500 includes a PLL (Phase-Locked Loop) unit 4 for generating a sampling clock K to be supplied to the A / D converter 21, and a prescaler value p for instructing the frequency of the sampling clock K.
And a sampling clock control unit 51 that supplies a phase value φ that commands the phase of the sampling clock K to the PLL unit 4, and the horizontal period Th shown in FIG. 17A is measured and shown in FIG. 17B. A horizontal period / horizontal display period measuring unit 52 for measuring a horizontal display period (waveform period effective for image display within the horizontal scanning period) Td.

The video amplifier 20 and the A / D converter 2
1, the PLL unit 4, and the sampling clock control unit 51
And the horizontal period / horizontal display period measuring unit 52 configure a video signal conversion device 501.

The operation of the sampling clock controller 51 is as follows (1) to (5). (1) The sampling clock control unit 51 acquires the horizontal resolution i corresponding to the horizontal synchronizing frequency fh and the vertical synchronizing frequency fv. For example, the horizontal synchronization frequency fh is 35.
The horizontal resolution i is "800" when the vertical synchronizing frequency fv is 1 kHz and the vertical synchronizing frequency fv is 56 Hz. (2) The sampling clock control unit 51 acquires the horizontal cycle Th and the horizontal display period Td. Then, the initial value of the prescaler value p is p = i × {Th / T
d} and set in the PLL unit 4. For example, the horizontal resolution i is 800 and the horizontal period Th is 28.49.
μs, when the horizontal display period Td is 22.792 μs, p
= 1000. The PLL unit 4 generates the sampling clock K for the number of times of the prescaler value p within the period of the horizontal cycle Th, but the A / D converter 21
Because the edge sampling is performed, the horizontal display period Td
There is no guarantee that the number of samples in will equal the horizontal resolution i. (3) The sampling clock controller 51 counts the number of sampling clocks within the horizontal display period Td. If the number of sampling clocks HD is different from the horizontal resolution i, a new prescaler value p is set to p = p '× {i /
HD} and set again in the PLL unit 4.
p'is a prescaler value before resetting. For example, when p ′ is 1000, the horizontal resolution i is 800, and the sampling clock number HD is “801”, p = 99
It becomes 8. (4) Even after resetting to a new prescaler value p,
If the sampling clock number HD is different from the horizontal resolution i, the process (3) is repeated to reset the prescaler value p. (5) If the number of sampling clocks HD is different from the horizontal resolution i even after the resetting of the prescaler value p is performed a prescribed number of times, the phase value φ is set so that the phase of the sampling clock K is sequentially shifted by a minute amount. To do. Then, by repeating this operation, the prescaler value p and the phase value φ when the sampling clock number HD becomes equal to the horizontal resolution i are set as optimum values.

[0006]

In the conventional video signal converting apparatus 501, the prescaler value p is adjusted so that the number of sampling clocks in the horizontal display period Td is equal to the horizontal resolution i, and the prescaler value p is adjusted several times. If it fails, the phase value φ is changed, and the prescaler value p is adjusted again so that the number of sampling clocks in the horizontal display period Td becomes equal to the horizontal resolution i, but this method requires a large number of repetitions. Therefore, there is a problem that it takes a long processing time until the optimum prescaler value p and the phase value φ are determined. Therefore, an object of the present invention is to convert an analog video signal into a digital video signal, which is A /
An object of the present invention is to provide a video signal conversion device and an LCD device capable of determining the optimum sampling frequency and phase of the D conversion means in a short time.

[0007]

According to a first aspect, the present invention relates to a video amplification means (20) for amplifying an input analog video signal and outputting an output analog video signal, and the output analog video signal being a digital video signal. A / D conversion means (21) for converting into a signal and its A / D conversion means (2
Sampling clock generating means (4) for generating a sampling clock (K) to be supplied to 1), and a sampling clock number (H) during a period when the output analog video signal or the digital video signal is higher than a slice level.
A horizontal display period counter (8) for counting D), and the slice level at the time of phase adjustment is slightly smaller than the maximum level of the output analog video signal or the digital video signal, or the output analog video signal or the digital video signal Horizontal display period count adjusting means (5) for adjusting at least one of the maximum level and the bottom level of the slice level and the output analog video signal or the digital video signal so as to be slightly higher than the bottom level of Sampling clock control means for detecting the count value of the horizontal display period counter for a plurality of candidates for the frequency and phase of the sampling clock (K) and determining the frequency and phase of the sampling clock (K) based on the count value. (5) with Providing a video signal converter (101), characterized in. In the video signal converter (101) according to the first aspect, the sampling clock (K)
Sampling clock (K) based on the count value of the horizontal display period counter for multiple candidates of frequency and phase of
The horizontal display period counter counts the number of sampling clocks (HD) during the period when the output analog video signal or digital video signal is higher than the slice level. And when adjusting the phase,
At least one of the slice level and the maximum level and the bottom level of the output analog video signal or the digital video signal is such that the slice level is slightly smaller than the maximum level of the output analog video signal or the digital video signal or slightly larger than the bottom level. Is adjusted. Therefore, as will be described in detail in the embodiments of the invention, a state in which the video signal cannot be properly sampled due to the "rounding" of the rising and falling of the video signal is referred to as a change in the count value of the horizontal display period counter. It becomes possible to detect, and the optimum sampling frequency and phase of the A / D conversion means (21) can be determined in a short time.

In the above structure, "slightly" means
Considering the drift of the power supply, 0.1 V or more is preferable. In consideration of the accuracy of phase adjustment, a voltage corresponding to ± 1 unit of phase adjustment, that is, 2 units of the amplitude of the output analog video signal or digital video signal (the period of the sampling clock K is divided into M When adjusting, it is preferably less than (amplitude / M) × 2). Here, M is preferably a multiple of “2” for the convenience of digital processing.

According to a second aspect, the present invention comprises an LCD panel (P), an LCD panel drive circuit (A), and the video signal conversion device (101) according to the first aspect. An LCD device (100) is provided. In the LCD device (100) of the second aspect, the optimum sampling frequency and phase of the A / D conversion means (21) for converting an analog video signal into a digital video signal can be determined in a short time, so that it can be displayed on the screen. The display accuracy in the horizontal direction can be increased.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in more detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 1 is a configuration block diagram showing an LCD device 100 according to an embodiment of the present invention. The LCD device 100 includes a video amplifier 20 for amplifying an input analog video signal (R signal, G signal, B signal) sent from a personal computer and outputting an output analog video signal, and an output analog video signal for a digital video signal. A / D to convert to (r signal, g signal, b signal)
It comprises a converter 21, an LCD panel drive circuit A for driving the LCD panel P according to a digital video signal, and an LCD panel P for displaying an image.

Further, the LCD device 100 detects the maximum level of the PLL unit 4 for generating the sampling clock K to be supplied to the A / D converter 21 and the maximum level of the digital video signal and outputs the detected maximum level to the CPU 5. Circuit 3
And a bright value that commands the bottom voltage of the output analog video signal and a contrast value that commands the amplitude of the output analog video signal to the video amplifier 20 so as to match the input to the A / D converter 21. In addition, the prescaler value p for instructing the frequency of the sampling clock K and the phase value φ for instructing the phase of the sampling clock K are supplied to the PLL unit 4 and the slice level value for instructing the slice level to the comparison / synthesis circuit 2 is supplied. Comparing / synthesizing the CPU 5 and the enable signal E set to "1" during the logical OR period of the r signal, the g signal, and the b signal of the digital video signal above the slice level, and "0" in the other periods. A circuit 2 and a horizontal circuit for counting the sampling clock K during the period when the enable signal E is "1". The indicated period counter 8, the first horizontal period counter 7 that counts the number of sampling clocks K in the horizontal period (Th in FIG. 3), and from the fall of the synchronization pulse of the horizontal synchronization signal Hsync to the start of the horizontal display period. A horizontal back porch counter 9 for counting the number of sampling clocks K in a horizontal back porch (Tb in FIG. 3; corresponding to the horizontal display start position) and a crystal oscillator 10 for generating a clock pulse S (for example, 20 MHz). When,
A second horizontal cycle counter 11 that counts the number of timekeeping pulses in the horizontal cycle and a vertical cycle counter 12 that counts the number of timekeeping pulses in the vertical cycle are provided.

The video amplifier 20 and the A / D converter 2
1, a PLL unit 4, a maximum level detection circuit 3, a CPU
5, the comparison / combination circuit 2, and the horizontal display period counter 8 constitute a video signal conversion device 101.

As the transmission method of the digital video signal, a serial transmission method for serially transmitting digital data of each color of r, g, and b for each pixel may be adopted, or digital data of a plurality of pixels may be adopted. A parallel transmission method for transmitting in parallel may be adopted.

FIG. 2 is a conceptual diagram of the horizontal resolution table 6 incorporated in the CPU 5. Horizontal resolution table 6
Stores the horizontal resolution i for each horizontal synchronization frequency fh and vertical synchronization frequency fv.

FIG. 3A is a waveform diagram of the vertical synchronizing signal Vsync. FIG. 3B is a waveform diagram of the horizontal synchronization signal Hsync. FIG. 3C is a conceptual diagram showing the existence period of the digital video signal in which the waveform period effective for image display is shown as a shaded area. FIG. 3D is a conceptual diagram of the enable signal E. FIG. 3E is a conceptual diagram of the sampling clock K.

FIG. 4 and FIG. 5 show a video signal conversion apparatus 1
11 is a flowchart showing a sampling frequency and phase adjustment processing by 01. FIG. In step S1 of FIG. 4, the clock phase number n indicating the phase of the sampling clock K is initialized to "0". In step S2, the second horizontal cycle counter 11 counts the time counting pulse S to measure the horizontal cycle Th. For example, the horizontal cycle Th is 28.4.
9 μs. Further, the vertical cycle counter 12 counts the time counting pulse S to measure the vertical cycle Tv. For example, the vertical cycle Tv is 17.85 ms. In step S3, the horizontal synchronizing frequency fh (= 1 / Th) and the vertical synchronizing frequency fv (= 1 / Tv) are calculated. In the above numerical example, the horizontal synchronization frequency fh is 35.1 kHz. The vertical synchronization frequency fv is 56 Hz. In step S4, the horizontal resolution i corresponding to the horizontal synchronizing frequency fh and the vertical synchronizing frequency fv is read from the horizontal resolution table 6 (see FIG. 2). In the above numerical example, “800” is read out as the horizontal resolution i. In step S5, the prescaler value p corresponding to the horizontal resolution i read in step S4 is retrieved from the prescaler initial value table (not shown) in which the initial value of the prescaler value p for each horizontal resolution is stored in advance. It is set in the PLL unit 4 (this setting causes the sampling clock K to be output from the PLL unit 4). The initial value of the prescaler value p corresponding to the horizontal resolution i = 800 is, for example, “1000”.
Is.

In step S51, the maximum level value is read. In step S52, at least one of the slice level value, the brightness value, and the contrast value is adjusted so that the slice level is slightly lower than the maximum level value or slightly higher than the bottom value. 8 to 14 for the significance of steps S51 and S52.
Will be described later with reference to.

In step S6, the phase value φ = 0 is set to PL
Set to L part 4. The phase value φ = 0 means, for example, the phase at which the sampling clock K falls at the same time as the fall of the sync pulse of the horizontal sync signal Hsync.

Referring to FIG. 5, in step S7, the first horizontal cycle counter 7 counts the number of sampling clocks HC within the horizontal cycle Th. Further, the horizontal display period counter 8 obtains the count value HD of the sampling clock K while the enable signal E is "1". In step S8, the prescaler value p is calculated by p = i × {HC / HD} and set in the PLL unit 4. For example, when the horizontal resolution i is 800, the number of sampling clocks HC in the horizontal cycle Th is "1000", and the count value HD of the horizontal display period counter 8 is "799", p = 1001. In step S9, an OK consecutive number counter nok for counting the number of times the count value HD of the horizontal display period counter 8 consecutively matches the horizontal resolution is initialized to "0". Further, an NG number counter nng that counts the number of times that the count value HD of the horizontal display period counter 8 does not match the horizontal resolution is initialized to "0".

In step S10, the horizontal display period counter 8 obtains the count value HD of the sampling clock K while the enable signal E is "1". Step S11
Then, if the count value HD of the horizontal display period counter 8 is equal to the horizontal resolution i, the process proceeds to step S12, and if not, the process proceeds to step S15.

In step S12, if the OK continuous number counter nok is not "4" or more, the process proceeds to step S13.
If it is "4" or more, the process proceeds to step S14. Step S13
Then, the OK continuous number counter nok is incremented by "1", and the process returns to step S10.

In step S14, the phase value φ being set is determined to be "OK", and the prescaler value p and the phase value φ being set "OK" are stored. Then, step S19
Go to.

In step S15, the NG number counter nng
If is not "8" or more, the process proceeds to step S16, "8"
If so, the process proceeds to step S18. In step S16,
A new prescaler value p is calculated by p = p '± 1 (p' is a prescaler value before resetting), and is reset in the PLL unit 4. That is, if the count value HD <horizontal resolution i, the prescaler value p = p '+ 1, and if the count value HD> horizontal resolution i, the prescaler value p = p'-
Set to 1. For example, when p ′ = 1000 and i = 800, if HD = 799, then p = 1001 and HD = 80.
If 1, p = 999. In step S17, OK
The continuous number counter nok is initialized to "0", the NG number counter nng is incremented by "1", and the step S
Return to 10.

In step S18, the phase value φ being set is determined to be "NG", and the prescaler value p and the phase value φ "NG" being set are stored. Then, step S19
Go to.

In step S19, it is determined whether or not the clock phase number n ≧ 15. If n <15, step S2
0, and when n ≧ 15, the process proceeds to step S22.
In step S20, the clock phase number n is set to "1".
Increment only. In step S21, the phase value φ that shifts (delays) the sampling clock K by n / 16 with respect to the cycle is set in the PLL unit 4.
Then, the process returns to step S7.

In step S22, the above step S1
4, the optimum prescaler value p and phase value φ are determined from the results obtained in S18 and set in the PLL unit 4. That is, in step S14, the phase value φ is "O".
The group of clock phase number n (clock phase number n = 15) that has the largest number of consecutive determinations with K ”
, And n = 0 is regarded as continuous), the prescaler value p and the phase value φ corresponding to the one having the intermediate clock phase number n (the smaller one when there are two intermediate numbers) are optimal. The value. For example, when the result as shown in FIG. 6 is obtained, the prescaler value “1” corresponding to n = 12 is obtained.
000 "and the phase value φ (= 12/16 period delay) are determined as optimum values. Further, when the result that there are two consecutive rows of" OK "as shown in FIG.
The prescaler value “1000” and the phase value φ (= 11/16 cycle delay) corresponding to the longer n = 11 in the “OK” column are determined as optimum values.

The CPU 5 sends an image display position control signal to the LCD panel drive circuit A based on the count value of the horizontal back porch counter 9 to always display an image at a fixed position.

Next, the significance of steps S51 and S52 in FIG. 4 will be described with reference to FIGS. In the description of FIGS. 6 and 7, one cycle of the sampling clock K is divided into 16 (clock phase numbers 0 to 15) to adjust the phase, but for convenience of description, in FIGS. It is assumed that one cycle is divided into eight (phases a to h) to adjust the phase.

In FIG. 8, the minimum value-maximum value of the digital video signal during adjustment is "0"-"255" (the bottom value of the output analog video signal is 2V, the maximum level value is 4V), and the slice level is It is "128" (3V converted to the voltage of the output analog video signal), and the sampling clock K represents the state of the phase a. Since the rising edge and the falling edge of the output analog video signal have "blurring", the period of the enable signal E = "1" changes depending on the relationship between the bottom value, the maximum level value, and the slice level of the output analog video signal. Therefore, the count value HD of the horizontal display period counter 8 may change. Also, the period during which the maximum level of the output analog video signal can be sampled may change depending on the phase. In the example of FIG. 8, the count value HD = i
Becomes Then, the period during which the maximum level can be displayed (phase a
Value converted to the number of sampling clocks during which the maximum level of the output analog video signal can be sampled with
i. In this case, the count value HD and the period during which the maximum level can be displayed match the horizontal resolution i, and there is no problem.
In FIG. 9, the minimum value-maximum value of the digital video signal during adjustment is "0"-"255" (the bottom value of the output analog video signal is 2V, the maximum level value is 4V), and the slice level is "128". (3V converted to the voltage of the output analog video signal), and the sampling clock K has a phase d
Represents the state of. In this example, the count value HD = i
Becomes On the other hand, the period in which the maximum level can be displayed is i-1. In this case, the period during which the maximum level can be displayed does not match the horizontal resolution i, which causes a problem such as "flickering" in the display. However, since the count value HD matches the horizontal resolution i, the CPU 5 cannot detect that a defect occurs in the phase d. That is, when the slice level is near the middle of the bottom value and the maximum level value of the output analog video signal, even if the phase is adjusted based on the count value HD, a problem such as "flickering" may occur in the display. .

In FIG. 10, the minimum value-maximum value of the digital video signal during adjustment is "0"-"140 to 153" (the bottom value of the output analog video signal is 2V, the maximum level value is 3.1 to 3. 2V) and the slice level is "12".
8 "(3V converted to the output analog video signal voltage)
And the sampling clock K represents the state of phase a. In this example, the count value HD = i. Also, the period during which the maximum level can be displayed is i. In this case, the count value HD and the period during which the maximum level can be displayed match the horizontal resolution i, and there is no problem. FIG. 11 shows the minimum value-maximum value of the digital video signal at the time of adjustment as "0"-"1".
40-153 "(bottom value of output analog video signal is 2V, maximum level value is 3.1-3.2V), slice level is" 128 "(3V converted to output analog video signal voltage) And the sampling clock K represents the state of the phase d. In this example, the count value H
D = i-1. Further, the period during which the maximum level can be displayed is i-1. In this case, the period during which the maximum level can be displayed does not match the horizontal resolution i, which causes a problem such as "flickering" in the display. However, the count value HD
Also does not match the horizontal resolution i, the CPU 5 can detect that this phase d is inappropriate. That is, if the slice level value or the contrast value is adjusted so that the slice level becomes slightly smaller than the maximum level value of the output analog video signal, and then the phase is adjusted based on the count value HD, the display "flickers". It is possible to avoid problems such as occurrence of. This is steps S51 and S5 in FIG.
2 is the significance.

In FIG. 12, the minimum value-maximum value of the digital video signal during adjustment is "0"-"255" (the bottom value of the output analog video signal is 2V, the maximum level value is 4V), and the slice level is The value is adjusted to "32" (converted into the voltage of the output analog video signal to 2.25V), and the sampling clock K represents the state of the phase a. In this example, the count value HD = i. Also, the period during which the maximum level can be displayed is i. In this case, the count value HD and the period during which the maximum level can be displayed match the horizontal resolution i, and there is no problem. In FIG. 13, the minimum value-maximum value of the digital video signal during adjustment is "0"-"255" (bottom value of output analog video signal is 2V, maximum level value is 4V).
That is, the slice level is adjusted to “32” (converted into the voltage of the output analog video signal and 2.25 V), and the sampling clock K represents the state of the phase d. In this example, the count value HD = i + 1. Further, the period during which the maximum level can be displayed is i-1. In this case, the period during which the maximum level can be displayed does not match the horizontal resolution i, which causes a problem such as "flickering" in the display. However, since the count value HD also does not match the horizontal resolution i,
The CPU 5 can detect that this phase d is inappropriate. In other words, if the slice level value is adjusted so that the slice level is slightly higher than the bottom value of the output analog video signal and then the phase is adjusted based on the count value HD, "flicker" may occur in the display. You can avoid problems. This is the significance of steps S51 and S52 in FIG.

In FIG. 14, the minimum value-maximum value of the digital video signal at the time of adjustment is "0"-"44 to 57" (the bottom value of the output analog video signal is 1.5V and the maximum level value is 2.50).
35 to 2.45V) and adjust the slice level to "9.
7 ”(converted to output analog video signal voltage of 2.2
5 V), and the sampling clock K represents the state of the phase a. In this example, the count value HD = i. Also, the period during which the maximum level can be displayed is i. In this case, the count value HD and the period during which the maximum level can be displayed match the horizontal resolution i, and there is no problem. In FIG. 15, the minimum value-the maximum value of the digital video signal at the time of adjustment is "0"-
Adjust to “44 to 57” (bottom value of output analog video signal is 1.5V, maximum level value is 2.35 to 2.45V) and slice level is “97” (converted to the voltage of output analog video signal. 2.25 V), and the sampling clock K represents the state of the phase d. In this example,
The count value HD = i-1. Further, the period during which the maximum level can be displayed is i-1. In this case, the period during which the maximum level can be displayed does not match the horizontal resolution i, which causes a problem such as "flickering" in the display. However, since the count value HD also does not match the horizontal resolution i, the CPU 5 can detect that the phase d is inappropriate. That is, the slice level is smaller than the maximum level value of the output analog video signal, and the difference between the slice level and the maximum level value of the output analog video signal corresponds to two units of phase adjustment with respect to the amplitude of the output analog video signal. The brightness value and the contrast value are adjusted to be less than the voltage (amplitude × 2/8 when the phase is adjusted by dividing the cycle of the sampling clock K into 8), and then the phase is adjusted based on the count value HD. By doing so, it is possible to avoid problems such as "flickering" in the display. This is the significance of steps S51 and S52 in FIG.

According to the LCD device 100 and the video signal conversion device 101 described above, the count value HD of the horizontal display period counter 8 coincides with the horizontal resolution i while the phase of the sampling clock K is sequentially shifted by "1 / M" cycles. Since the changing of the prescaler value p is repeated as described above, the optimum frequency and phase of the sampling clock K can be determined in a short time. Further, at the time of phase adjustment, at least one of the slice level value, the brightness value and the contrast value is set so that the slice level is slightly smaller than the maximum level of the output analog video signal or the digital video signal or slightly larger than the bottom level. Because of the adjustment, the state in which the video signal cannot be properly sampled due to the "blunting" of the rising and falling of the video signal can be detected as a change in the count value of the horizontal display period counter 8.

[0034]

The video signal converter and LC of the present invention.
According to the D device, the optimum sampling frequency and phase of the A / D conversion means for converting the analog video signal into the digital video signal can be determined in a short time. Further, it is possible to detect a state in which the video signal cannot be properly sampled due to the "blurring" of the rising and falling edges of the video signal, as a change in the count value of the horizontal display period counter.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an LCD device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the contents of a horizontal resolution table.

FIG. 3 is a waveform diagram of each part of the LCD device of FIG.

4 is a flowchart showing a sampling frequency and phase adjustment process in the LCD device of FIG.

FIG. 5 is a flowchart showing a continuation of FIG. 4;

FIG. 6 is an explanatory diagram of a determination result indicating whether the count value of the horizontal display period counter is equal to the horizontal resolution.

FIG. 7 is another explanatory diagram of the determination result indicating whether or not the count value of the horizontal display period counter is equal to the horizontal resolution.

FIG. 8 is an explanatory diagram showing a state in which the slice level is between the bottom value and the maximum level value and sampling is performed at the phase a.

FIG. 9 is an explanatory diagram showing a state in which the slice level is between the bottom value and the maximum level value and sampling is performed at the phase d.

FIG. 10 is an explanatory diagram showing a state in which the slice level is slightly smaller than the maximum level value and sampling is performed at the phase a.

FIG. 11 is an explanatory diagram showing a state in which the slice level is slightly smaller than the maximum level value and sampling is performed at the phase d.

FIG. 12 is an explanatory diagram showing a state in which the slice level is slightly higher than the bottom value and sampling is performed at the phase a.

FIG. 13 is an explanatory diagram showing a state where the slice level is slightly higher than the bottom value and sampling is performed at the phase d.

FIG. 14 is an explanatory diagram showing a state in which the slice level is slightly smaller than the maximum level value and sampling is performed at the phase a.

FIG. 15 is an explanatory diagram showing a state in which the slice level is slightly smaller than the maximum level value and sampling is performed at the phase d.

FIG. 16 is a configuration block diagram showing an example of a conventional LCD device.

FIG. 17 is an explanatory diagram showing a horizontal synchronizing signal and a video signal.

[Explanation of symbols]

100 LCD device 101 video signal converter 2 Comparison / synthesis circuit 3 Maximum level detection circuit 4 PLL section 5 CPU 6 Horizontal resolution table 7 1st horizontal cycle counter 8 Horizontal display period counter 9 Horizontal back porch counter 10 Crystal oscillator 11 Second horizontal cycle counter 12 Vertical cycle counter 20 video amplifier 21 A / D converter A LCD panel drive circuit K sampling clock P LCD panel Td horizontal display period Th horizontal cycle Hsync Horizontal sync signal Vsync Vertical sync signal

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 505 G09G 3/20 623 H04N 5/66 102

Claims (2)

(57) [Claims] 1. A video amplification means (20) for amplifying an input analog video signal and outputting an output analog video signal.
An A / D conversion means (21) for converting the output analog video signal into a digital video signal, and a sampling clock generation means (4) for generating a sampling clock (K) to be supplied to the A / D conversion means (21). ) And a horizontal display period counter (8) for counting the number of sampling clocks (HD) in a period in which the output analog video signal or the digital video signal is higher than a slice level.
And the slice so that at the time of phase adjustment, the slice level is slightly lower than the maximum level of the output analog video signal or the digital video signal or slightly higher than the bottom level of the output analog video signal or the digital video signal. Horizontal display period count adjusting means (5) for adjusting a level and at least one of a maximum level and a bottom level of the output analog video signal or the digital video signal, and a plurality of frequency and phase of the sampling clock (K). A sampling clock control means (5) for detecting a count value of the horizontal display period counter for a candidate and determining a frequency and a phase of the sampling clock (K) based on the count value is provided. Video signal converter (101). 2. An LCD device (100) comprising an LCD panel (P), an LCD panel drive circuit (A) and the video signal conversion device (101) according to claim 1.