JP3613725B2 - Sampling frequency / phase adjusting method, sampling frequency / phase adjusting device and LCD device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sampling frequency / phase adjustment method, a sampling frequency / phase adjustment device, and an LCD (Liquid Crystal Display) device, and more particularly, a sampling frequency capable of optimizing the sampling frequency and phase in an LCD device in a short time. The present invention relates to a phase adjustment method, a sampling frequency / phase adjustment device, and an LCD device including the sampling frequency / phase adjustment device.
[0002]
[Prior art]
FIG. 8 is a block diagram showing an example of a sampling frequency / phase adjusting device in a conventional LCD device.
This sampling frequency / phase adjustment apparatus 500 is a PLL (Phase-Locked Loop) that generates a sampling clock K supplied to an A / D converter C that converts an analog video signal VD sent from a personal computer into a digital video signal, for example. ) Section 4, a sampling clock control section 51 for setting the prescaler value p in the prescaler 3 built in the PLL section 4 and setting the phase φ of the sampling clock K, and a horizontal period Th shown in FIG. A “horizontal period and horizontal display period measuring unit” 52 for measuring and measuring the horizontal display period (waveform period effective for image display within the horizontal scanning period) Td shown in FIG. 9B is provided. ing.
The LCD device includes an LCD panel P, an LCD panel driving circuit A, an A / D converter C, and the sampling frequency / phase adjusting device 500.
[0003]
The operation of the sampling frequency / phase adjustment apparatus 500 is as follows (1) to (5).
(1) The sampling clock control unit 51 acquires the horizontal resolution i corresponding to the horizontal synchronization frequency fh and the vertical synchronization frequency fv. For example, when the horizontal synchronization frequency fh is 35.1 kHz and the vertical synchronization frequency fv is 56 Hz, the horizontal resolution i is “800”.
(2) The sampling clock control unit 51 acquires the horizontal period Th and the horizontal display period Td. Then, an initial value of the prescaler value p is calculated by p = i × {Th / Td} and set in the PLL unit 4. For example, when the horizontal resolution i is 800, the horizontal period Th is 28.49 μs, and the horizontal display period Td is 22.792 μs, p = 1000. The PLL unit 4 generates the sampling clock K by the number of times of the prescaler value p within the period of the horizontal cycle Th. However, the A / D converter C performs edge sampling, so that the horizontal display period Td. Is not guaranteed to be equal to the horizontal resolution i.
(3) The sampling clock control unit 51 counts the number of sampling clocks HD within the horizontal display period Td. If the sampling clock number HD is different from the horizontal resolution i, a new prescaler value p is calculated by p = p ′ × {i / HD}, and is set in the PLL unit 4 again. p ′ is a prescaler value before resetting. For example, when p ′ is 1000, the horizontal resolution i is 800, and the number of sampling clocks HD is “801”, p = 998.
(4) Even after resetting to the new prescaler value p, if the sampling clock number HD is different from the horizontal resolution i, the processing of (3) is repeated and the prescaler value p is reset.
(5) If the sampling clock number HD is different from the horizontal resolution i even after the prescaler value p is reset a predetermined number of times, the phase φ is set so that the phase of the sampling clock K is shifted by a minute amount in order. . Then, this operation is repeated, and the prescaler value p and the phase φ when the sampling clock number HD becomes equal to the horizontal resolution i are determined as appropriate values.
[0004]
[Problems to be solved by the invention]
The above-described conventional sampling frequency and phase adjuster 500 adjusts the sampling clock number HD in the horizontal display period Td to be equal to the horizontal resolution i, the sampling clock number HD in the horizontal display period Td and horizontal resolution i The sampling frequency and phase when they are equal are determined as appropriate values.
However, this method has a problem that it may take a long time to determine the optimum sampling frequency and phase as values to be used .
SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling frequency / phase adjustment method, a sampling frequency / phase adjustment device, and an LCD device that can determine an optimum sampling frequency and phase in a short time.
[0005]
[Means for Solving the Problems]
In a first aspect, the present invention is a sampling frequency / phase adjustment method for adjusting the frequency and phase of a sampling clock supplied to an A / D conversion circuit that converts an analog video signal to digital and sends it to an LCD panel driving circuit. A plurality of candidate values for the phase of the sampling clock are prepared, an appropriate value of the frequency of the sampling clock is searched for within a predetermined search range for each candidate value, and if an appropriate value is found, the appropriate value and the candidate value Sampling frequency, determining the candidate value in the middle of the phase range where the acquired candidate values are longest as a phase, and determining an appropriate value corresponding thereto as the frequency of the sampling clock. Provide a phase adjustment method.
[0006]
In a second aspect, the present invention relates to the frequency and phase of a sampling clock supplied to an A / D conversion circuit that converts an analog video signal to digital and sends it to an LCD panel driving circuit from the following (a) to (g The sampling frequency / phase adjustment method is characterized in that it is determined by the procedure of
(A) The sampling clock frequency is set to a certain initial value.
(B) The sampling clock phase is set to a certain candidate value.
(C) Count the number of sampling clocks in the horizontal display period, and determine whether or not the count value matches the target value.
(D) The above (c) is repeated until the first predetermined number of times matches or until the second predetermined number of times does not match. However, if the count value does not match the target value, the frequency of the sampling clock is changed in a direction approaching the target value before performing the next (c).
(E) The frequency and phase of the sampling clock when the first predetermined number of times coincides are stored.
(F) The above (c) to (e) are repeated for all candidate values of the sampling clock phase.
(G) Select and determine the intermediate phase of the phase range in which the matched phases are the longest and the corresponding sampling frequency .
[0007]
In the sampling frequency / phase adjustment method according to the present invention, an appropriate value of the sampling clock frequency is searched for one of a plurality of candidate values of the phase, and if an appropriate value is found within a predetermined search range, to acquire repeated for all candidate values, the intermediate candidate value of the phase range candidate value appropriate value is found is continuous longest is determined as the phase, a proper value corresponding to the frequency of the sampling clock Thus, the optimum sampling frequency and phase can be determined in a short time.
[0008]
In a third aspect, the present invention relates to a sampling clock that generates a sampling clock (K) that converts an analog video signal to digital and supplies it to an A / D conversion circuit (C) that is sent to an LCD panel drive circuit (A). The generating means (4), the horizontal display period counter (8) for counting the number of sampling clocks (HD) within the horizontal display period, and the sampling clock (for each of a plurality of candidate values of the phase φ of the sampling clock (K)) K) searches for an appropriate value of the frequency within a predetermined search range, and if an appropriate value is found, obtains the appropriate value and a candidate value, and selects an intermediate candidate value in the phase range where the acquired candidate values are the longest continuous. and a sampling clock control means (5) for determining the proper value determined as a phase corresponding to the frequency of the sampling clock Providing the sampling frequency and phase adjusting apparatus characterized by a.
The sampling frequency / phase adjustment apparatus according to the third aspect can suitably implement the sampling frequency / phase adjustment method according to the first aspect.
[0009]
In a fourth aspect, the present invention relates to a sampling clock that generates a sampling clock (K) that converts an analog video signal into a digital signal and supplies it to an A / D conversion circuit (C) that is sent to an LCD panel drive circuit (A). The generation means (4), the horizontal display period counter (8) for counting the number of sampling clocks (HD) in the horizontal display period, and the frequency of the sampling clock (K) by the following procedures (a) to (g) And a sampling clock control means (5) for determining the phase and the phase.
(A) The sampling clock frequency is set to a certain initial value.
(B) The sampling clock phase is set to a certain candidate value.
(C) Count the number of sampling clocks in the horizontal display period, and determine whether or not the count value matches the target value.
(D) The above (c) is repeated until the first predetermined number of times coincides or the second predetermined number of times does not coincide. However, if the count value does not match the target value, the frequency of the sampling clock is changed in a direction approaching the target value before performing the next (c).
(E) The frequency and phase of the sampling clock when the first predetermined number of times coincides are stored.
(F) The above (c) to (e) are repeated for all candidate values of the sampling clock phase.
(G) Select and determine the intermediate phase of the phase range in which the matched phases are the longest and the corresponding sampling frequency .
In the sampling frequency / phase adjustment apparatus according to the fourth aspect, the sampling frequency / phase adjustment method according to the second aspect can be suitably implemented.
[0010]
In a fifth aspect, the present invention relates to an LCD panel, an LCD panel driving circuit, an A / D conversion circuit that converts an analog video signal to digital and sends the digital video signal to the LCD panel driving circuit. An LCD device comprising the sampling frequency / phase adjusting device according to 4 is provided.
In the LCD device of the fifth aspect, since the frequency and phase of the sampling clock of the A / D conversion circuit can be quickly optimized, the display accuracy in the horizontal direction on the screen can be increased.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to embodiments shown in the drawings. Note that the present invention is not limited thereby.
FIG. 1 is a block diagram showing a sampling frequency / phase adjustment apparatus 100 in an LCD according to an embodiment of the present invention.
This sampling frequency / phase adjustment apparatus 100 is an A / D converter C that converts an analog video signal VD (R signal, G signal, B signal) sent from a personal computer into digital video signals r, g, b, for example. A PLL unit 4 for generating a sampling clock K to be supplied to the CPU, a CPU 5 for setting a prescaler value p in a prescaler 3 built in the PLL unit 4 and setting a phase φ of the sampling clock K, and the video signals r, g, b, a horizontal resolution table 6 for storing the horizontal resolution i for each of the horizontal synchronization frequency fh and the vertical synchronization frequency fv, as shown in FIG. 2, and a sampling clock in the horizontal period (Th in FIG. 5). The first horizontal period counter 7 that counts the number and the number of sampling clocks within the horizontal display period (Td in FIG. 5) The horizontal display period counter 8 and the number of sampling clocks in the horizontal back porch (Tb in FIG. 5; corresponding to the display start position in the horizontal direction) from the fall of the synchronization pulse of the horizontal synchronization signal Hsync to the start of the horizontal display period A horizontal back porch counter 9 that counts the time, a crystal oscillator 10 that generates a time-measurement pulse S (for example, 20 MHz), a second horizontal period counter 11 that counts the number of time-measurement pulses within the horizontal period, and a time measurement within the vertical period And a vertical cycle counter 12 for counting the number of pulses for use.
As a transmission method for the digital video signals r, g, and b, a serial transmission method that serially transmits data of each color one pixel at a time may be adopted, or a parallel transmission that transmits data of a plurality of pixels in parallel. A transmission method may be adopted.
The LCD device includes an LCD panel P, an LCD panel driving circuit A, an A / D converter C, and the sampling frequency / phase adjusting device 100.
[0012]
3 and 4 are flowcharts showing the sampling frequency and phase adjustment processing by the sampling frequency / phase adjustment apparatus 100. FIG.
FIG. 5A is a waveform diagram of the vertical synchronization signal Vsync. (B) is a waveform diagram of the horizontal synchronization signal Hsync. (C) is an explanatory diagram of digital video signals r, g, and b in which a waveform period effective for image display is shown as a hatched area. (D) is an explanatory diagram of a synthesized signal output from the synthesis circuit 2. (E) is a waveform diagram of the sampling clock K. FIG.
[0013]
In step S1 of FIG. 3, the clock phase number n indicating the phase of the sampling clock K is initialized to “0”.
In step S2, the second horizontal cycle counter 11 counts the timing pulse S and measures the horizontal cycle Th. For example, the horizontal period Th is 28.49 μs. Further, the vertical period counter 12 counts the time-measurement pulse S and measures the vertical period Tv. For example, the vertical period Tv is 17.85 ms.
In step S3, a horizontal synchronization frequency fh (= 1 / Th) and a vertical synchronization frequency fv (= 1 / Tv) are calculated. In the above numerical example, the horizontal synchronization frequency fh is 35.1 kHz. The vertical synchronization frequency fv is 56 Hz.
In step S4, the horizontal resolution i corresponding to the horizontal synchronization frequency fh and the vertical synchronization frequency fv is read from the horizontal resolution table 6 (see FIG. 2). In the above numerical example, “800” is read as the horizontal resolution i.
In step S5, a prescaler value p corresponding to the horizontal resolution i read in step S4 is extracted from a prescaler initial value table (not shown) in which the initial value of the prescaler value p for each horizontal resolution is stored in advance. The PLL unit 4 is set (by this setting, the sampling clock K is output from the PLL unit 4). The initial value of the prescaler value p corresponding to the horizontal resolution i = 800 is, for example, “1000”.
In step S6, the phase φ = 0 is set in the PLL unit 4. Note that the phase φ = 0 means, for example, a clock phase in which the sampling clock K is generated at the same time as the falling edge of the synchronization pulse of the horizontal synchronization signal Hsync.
[0014]
Proceeding to FIG. 4, in step S7, the first horizontal cycle counter 7 counts the number of sampling clocks HC within the horizontal cycle Th. Further, the horizontal display period counter 8 counts the number of sampling clocks HD within the horizontal display period Td.
In step S8, the prescaler value p is set to
p = i × {HC / HD}
And set in the PLL unit 4. For example, when the horizontal resolution i is 800, the sampling clock number HC within the horizontal period Th is “1000”, and the sampling clock number HD within the horizontal display period Td is “799”, p = 1001.
In step S9, an OK continuous number counter nok that counts the number of times that the sampling clock number HD within the horizontal display period Td continuously matches the horizontal resolution is initialized to “0”. Also, an NG counter nng that counts the number of times the sampling clock number HD within the horizontal display period Td does not match the horizontal resolution is initialized to “0”.
[0015]
In step S10, the horizontal display period counter 8 counts the number of sampling clocks HD within the horizontal display period Td.
In step S11, if the sampling clock number HD in the horizontal display period Td is equal to the horizontal resolution i, the process proceeds to step S12, and if not, the process proceeds to step S15.
[0016]
In step S12, if the OK continuous number counter nok is not "4" or more, the process proceeds to step S13, and if it is "4" or more, the process proceeds to step S14.
In step S13, the OK continuous number counter nok is incremented by "1", and the process returns to step S10.
[0017]
In step S14, it is determined that the phase φ being set is “OK”, and the prescaler value p being set and “OK” of the phase φ are stored. Then, the process proceeds to step S19.
[0018]
In step S15, if the NG counter nng is not “8” or more, the process proceeds to step S16, and if it is “8” or more, the process proceeds to step S18.
In step S16, a new prescaler value p is calculated from p = p ′ ± 1 (p ′ is a prescaler value before resetting), and is reset in the PLL unit 4. That is, if the sampling clock number HD <horizontal resolution i, the prescaler value p = p ′ + 1. If the sampling clock number HD> horizontal resolution i, the prescaler value p = p′−1. For example, when p ′ = 1000 and i = 800, if HD = 799, p = 1001 and if HD = 801, p = 999.
In step S17, the OK continuous number counter nok is initialized to “0”, the NG number counter nng is incremented by “1”, and the process returns to step S10.
[0019]
In step S18, the phase φ being set is determined as “NG”, and the prescaler value p being set and “NG” of the phase φ are stored. Then, the process proceeds to step S19.
[0020]
In step S19, it is determined whether or not the clock phase number n ≧ 15. If n <15, the process proceeds to step S20, and if n ≧ 15, the process proceeds to step S22.
In step S20, the clock phase number n is incremented by “1”.
In step S21, the phase φ for shifting (delaying) the sampling clock K by n / 16 with respect to the period is set in the PLL unit 4. Then, the process returns to step S7.
[0021]
In step S22, the optimum prescaler value p and phase φ are determined from the results obtained in steps S14 and S18 and set in the PLL unit 4. That is, the group of the clock phase number n having the maximum number of times that the phase φ is continuously determined as “OK” in step S14 (the clock phase number n = 15 and n = 0 is considered to be continuous). Among them, the prescaler value p and the phase φ corresponding to the intermediate clock phase number n (the smaller one when there are two intermediate ones) are set as the optimum values. For example, when the result shown in FIG. 6 is obtained, the prescaler value “1000” and the phase φ (= 12/16 period delay) corresponding to n = 12 are determined as optimum values. When the result as shown in FIG. 7 is obtained, the prescaler value “1000” corresponding to n = 11 and the phase φ (= 11/16 period delay) are determined as the optimum values.
[0022]
The CPU 5 sends an image display position control signal to the LCD panel drive circuit A based on the count value of the horizontal back porch counter 9, and always displays an image at a fixed position.
[0023]
According to the sampling frequency / phase adjusting apparatus 100 described above, the prescaler value is set such that the sampling clock number HD in the horizontal display period Td matches the horizontal resolution i while the phase φ of the sampling clock K is sequentially shifted by 1/16 period. Since changing p is repeated, the optimum frequency and phase of the sampling clock K can be determined in a short time.
[0024]
【The invention's effect】
According to the sampling frequency / phase adjustment method, sampling frequency / phase adjustment device, and LCD device of the present invention, an appropriate value of the sampling clock frequency is searched for one of a plurality of candidate values for the phase, and is appropriate within a predetermined search range. If the value is found, the appropriate value and the candidate value are acquired for all candidate values, and the candidate value in the middle of the phase range in which the acquired candidate values are the longest continuous is determined as the phase, and corresponding Since the appropriate value to be determined is determined as the frequency of the sampling clock , the sampling frequency and phase to be supplied to the A / D conversion circuit of the LCD device can be determined to the optimum values in a short time.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a sampling frequency / phase adjusting apparatus according to an embodiment of the present invention.
2 is an explanatory diagram showing the contents of a horizontal resolution table in the sampling frequency / phase adjustment apparatus of FIG. 1; FIG.
FIG. 3 is a flowchart showing sampling frequency and phase adjustment processing by the sampling frequency / phase adjustment apparatus of FIG. 1;
FIG. 4 is a flowchart subsequent to FIG. 3;
5 is a waveform diagram of each part of the sampling frequency / phase adjustment apparatus of FIG. 1; FIG.
FIG. 6 is an explanatory diagram of a determination result indicating whether or not the count value of the horizontal display period counter is equal to the horizontal resolution.
FIG. 7 is another explanatory diagram of a determination result indicating whether or not the count value of the horizontal display period counter is equal to the horizontal resolution.
FIG. 8 is a block diagram showing a conventional sampling frequency / phase adjusting device in an LCD.
FIG. 9 is an explanatory diagram showing a horizontal synchronization signal and a video signal.
[Explanation of symbols]
100 Sampling Frequency / Phase Adjustment Device 2 Synthesis Circuit 3 Prescaler 4 PLL Unit 5 CPU
6 horizontal resolution table 7 first horizontal cycle counter 8 horizontal display period counter 9 horizontal back porch counter 10 crystal oscillator 11 second horizontal cycle counter 12 vertical cycle counter C A / D converter A LCD panel drive circuit K sampling clock P LCD panel Tb Horizontal back porch Td Horizontal display period Th Horizontal cycle Tv Vertical cycle Hsync Horizontal sync signal Vsync Vertical sync signal VD Video signal

Claims (5)

A sampling frequency / phase adjustment method for adjusting a frequency and a phase of a sampling clock supplied to an A / D conversion circuit that converts an analog video signal into a digital signal and sends it to an LCD panel driving circuit,
Prepare a plurality of candidate values for the phase of the sampling clock, search for an appropriate value of the frequency of the sampling clock for each candidate value within a predetermined search range, and obtain an appropriate value and a candidate value if an appropriate value is found. The sampling frequency / phase adjustment is characterized in that the candidate value in the middle of the phase range in which the acquired candidate values are the longest is determined as the phase, and the appropriate value corresponding thereto is determined as the frequency of the sampling clock. Method. The frequency and phase of a sampling clock to be supplied to an A / D conversion circuit that converts an analog video signal to digital and sends it to an LCD panel drive circuit are determined by the following procedures (a) to (g): Sampling frequency and phase adjustment method.
(A) The sampling clock frequency is set to a certain initial value.
(B) The sampling clock phase is set to a certain candidate value.
(C) Count the number of sampling clocks in the horizontal display period, and determine whether or not the count value matches the target value.
(D) The above (c) is repeated until the first predetermined number of times matches or until the second predetermined number of times does not match. However, if the count value does not match the target value, the frequency of the sampling clock is changed in a direction approaching the target value before performing the next (c).
(E) The frequency and phase of the sampling clock when the first predetermined number of times coincides are stored.
(F) The above (c) to (e) are repeated for all candidate values of the sampling clock phase.
(G) Select and determine the intermediate phase of the phase range in which the matched phases are the longest and the corresponding sampling frequency . Sampling clock generating means (4) for generating a sampling clock (K) to be supplied to an A / D conversion circuit (C) for converting an analog video signal to digital and sending it to the LCD panel drive circuit (A), and a horizontal display period A predetermined search for an appropriate value of the frequency of the sampling clock (K) for each of a plurality of candidate values of the phase φ of the sampling clock (K) and a horizontal display period counter (8) that counts the number of sampling clocks (HD) If an appropriate value is found by searching within the range, the appropriate value and the candidate value are acquired, and the candidate value obtained in the middle of the phase range where the acquired candidate value is the longest is determined as the phase, and the appropriate value corresponding to it is determined. sump, characterized by comprising a sampling clock control means (5) for determining a frequency of the sampling clock Packaging frequency and phase adjustment device. Sampling clock generating means (4) for generating a sampling clock (K) to be supplied to an A / D conversion circuit (C) for converting an analog video signal to digital and sending it to the LCD panel drive circuit (A), and a horizontal display period A horizontal display period counter (8) for counting the number of sampling clocks (HD) in the display, and sampling clock control means for determining the frequency and phase of the sampling clock (K) by the following procedures (a) to (g) (5). A sampling frequency / phase adjusting apparatus comprising:
(A) The sampling clock frequency is set to a certain initial value.
(B) The sampling clock phase is set to a certain candidate value.
(C) Count the number of sampling clocks in the horizontal display period, and determine whether or not the count value matches the target value.
(D) If the count value does not match the target value, the frequency of the sampling clock is changed in a direction approaching the target value, and the above (c) is repeated. If it does not match even after repeating a predetermined number of times, the process proceeds to (f).
(E) Store the frequency and phase of the sampling clock when they match, and proceed to (f).
(F) The above (c) to (e) are repeated for all candidate values of the sampling clock phase.
(G) Select and determine the intermediate phase of the phase range in which the matched phases are the longest and the corresponding sampling frequency . 5. A sampling frequency / phase adjusting apparatus according to claim 3 or 4, wherein an LCD panel, an LCD panel driving circuit, an A / D conversion circuit for converting an analog video signal to digital and sending it to the LCD panel driving circuit, and An LCD device comprising:

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