JPH11177901A - Device and method for synthesizing osd - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously display characters and an image reproduced from a video signal without generating vertical oscillation in character display by synchronizing an on-screen display(OSD) signal with a horizontal synchronizing signal including a video signal when the number of counted pulse signals reaches a set point. SOLUTION: When clock signals are outputted from a clock 11 at a fixed period, a time counting counter 12 increases its counter value, and when the counter value reaches the set point and overflows, outputs an overflow signal. After the output of the overflow signal from the counter 12, a synchronizing circuit 13 outputs a vertical display start signal at the time of inputting an initial horizontal synchronizing signal (HSYNC). When the vertical display start signal is outputted from the circuit 13, an OSD circuit 14 outputs an OSD signal related to a character synchronizing with the vertical display start signal. A synthesis circuit 15 synthesizes the ODS signal and the HSYNC including a video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OSD (On Screen Discharge) related to a character displayed on a screen.
The present invention relates to an OSD synthesizing apparatus and an OSD synthesizing method for synthesizing a play (play) signal into a horizontal synchronizing signal including a video signal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional OSD synthesizing apparatus. In FIG. 6, reference numeral 1 denotes a vertical synchronizing signal (hereinafter referred to as "V
SYNC "), the counter value is reset to zero, and when a horizontal synchronization signal (hereinafter, referred to as" HSYNC ") is input, the HSYNC counter increments the counter value.
Reference numeral 2 denotes a vertical position register for storing a vertical position on the screen on which a character is displayed. Reference numeral 3 denotes a counter for comparing the counter value of the HSYNC counter 1 with the register value of the vertical position register 2. When the vertical display start signal is output from the comparator 3, the comparator 4 that outputs a start signal selects a character to be displayed on the screen from a plurality of preset character patterns in accordance with a character selection signal. An OSD circuit 5 for outputting an OSD signal related to the character is a synthesizing circuit for synthesizing the OSD signal output from the OSD circuit 4 with HSYNC including a video signal.

Next, the operation will be described. For example, when a video device or the like is connected to the television, a character indicating the operation status of the video is displayed on the screen. In particular, when fast-forwarding is performed simultaneously with video playback, the character shown in FIG. Such a character is displayed on the screen.

The operation of displaying such a character will be described in detail. First, when a fast-forward key is selected during video playback, a circuit (not shown) outputs VSYNC, and the VSYNC is output to an HSYNC counter. Entered into 1,
The counter value of the HSYNC counter 1 is reset to zero.
The HSYNC counter 1 outputs HSYNC from a circuit (not shown).
Is output, the process of incrementing the counter value is performed each time HSYNC is output.

On the other hand, the comparator 3 always compares the register value of the vertical position register 2 in which the vertical position on the screen displaying the character is stored with the counter value of the HSYNC counter 1, and compares the register value with the counter value. , A vertical display start signal is output.

When the vertical display start signal is output from the comparator 3, the OSD circuit 4 synchronizes the vertical display start signal with the OSD signal relating to the character shown in FIG. (Determined according to the output character selection signal). Then, when the OSD signal is output from the OSD circuit 4, the synthesizing circuit 5
The OSD signal is combined with the HSYNC including the video signal,
A series of processing ends.

As a result, a video image and a character for video reproduction are simultaneously displayed on the television screen (see FIG. 8). However, when fast-forwarding is performed simultaneously with video reproduction, HSYNC becomes unstable. In this state (as shown in FIG. 7, for example, the interval between HSYNCs may become narrower or the interval may become wider due to lack of the HSYNC), so that the character vertically vibrates (see FIG. 8).

FIG. 10 shows a conventional example for preventing vertical vibration of a character. When HSYNC is unstable, the selector 7 always generates a pulse signal (HSYNC not including a video signal) at a constant interval. The HSYNC generator 1 selects the desired HSYNC generator 6 and the HSYNC counter 1 inputs the HSYNC output from the HSYNC generator 6 and increments the counter value. Therefore, vertical oscillation of the character can be prevented. Because no HSYNC is input
The video reproduced image is not displayed (see FIG. 11).

[0009]

Since the conventional OSD synthesizing apparatus is configured as described above, it is possible to simultaneously display a video image and a character for video reproduction. However, since the HSYNC becomes unstable, the vertical display start signal output from the comparator 3 is disturbed, so that there is a problem that the character vertically shakes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. Even when fast-forwarding is performed simultaneously with video playback, a character and video playback video are displayed simultaneously without vertical oscillation of the character. It is an object of the present invention to obtain an OSD synthesizing apparatus and an OSD synthesizing method.

[0011]

When an OSD synthesizing apparatus according to the present invention receives a vertical synchronizing signal, it starts a process of counting the number of pulse signals output at a fixed period, and the pulse signal is output. When the count number reaches the set value, a synchronization start signal indicating that fact is output, and O
The SD signal is synchronized with a horizontal synchronization signal including a video signal.

In the OSD synthesizing apparatus according to the present invention, when the vertical synchronization signal is input, the count number of the pulse signal is reset to zero, and when the count number of the pulse signal reaches a set value, the overflow signal is started to be synchronized. The counting means is constituted by using a counter which outputs a signal.

[0013] The OSD synthesizing apparatus according to the present invention is provided with setting means for setting a set value in the counting means.

The OSD synthesizing device according to the present invention executes processing for synchronizing the OSD signal with the horizontal synchronizing signal when the first horizontal synchronizing signal is input after the synchronizing start signal is output from the counting means. It is like that.

In the OSD synthesizing apparatus according to the present invention, the pulse generating means is constituted by using a clock which generates a clock signal as a pulse signal.

In the OSD synthesizing method according to the present invention, when a vertical synchronizing signal is input, a process of counting the number of pulse signals output at a constant cycle is started, and the count number of the pulse signal is set to a set value. , A synchronization start signal indicating that fact is output, and the OSD signal is synchronized with the horizontal synchronization signal including the video signal.

In the OSD synthesizing method according to the present invention, when the first horizontal synchronization signal is input after the synchronization start signal is output, a process of synchronizing the OSD signal with the horizontal synchronization signal is executed. Things.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram of an embodiment 1 of the present invention.
1 is a configuration diagram showing an SD synthesizing apparatus, in which 11 is a clock signal (hereinafter, referred to as “CLK”) at a constant cycle.
(Pulse generation means), and when a vertical synchronizing signal (hereinafter referred to as “VSYNC”) is input, C
The LK count is reset to zero and the clock 11
Starts a process of counting the number of CLKs output from the CPU and, when the number of CLKs reaches a set value, outputs an overflow signal (synchronization start signal) indicating that, a time measurement counter (counting means) , 13 output a vertical display start signal when the first horizontal synchronization signal (hereinafter referred to as “HSYNC”) is input after the overflow signal is output from the time measurement counter 12 when the overflow signal is output. When a vertical display start signal is output from the synchronization circuit 13, the synchronization circuit (synchronization means) 14 selects a character from a plurality of preset character patterns according to a character selection signal. An OSD circuit (synchronizing means) for outputting an OSD signal relating to the character, and 15 is an OSD circuit 1
4 is converted to an HSY signal including a video signal.
This is a synthesis circuit (synthesis means) for synthesizing with NC. Note that FIG.
3 is a flowchart showing an OSD synthesis method according to Embodiment 1 of the present invention.

Next, the operation will be described. For example, when a video device or the like is connected to the television, a character indicating the operation status of the video is displayed on the screen. In particular, when fast-forwarding is performed simultaneously with video playback, the character shown in FIG. Such a character is displayed on the screen.

The operation of displaying such a character will be described in detail. First, when a fast-forward key is selected during video playback, a circuit (not shown) outputs VSYNC, and the VSYNC is measured for time. The counter value is input to the counter 12, and the counter value of the time measurement counter 12 is reset to zero (steps ST1 and ST2). Then, the time measurement counter 12 outputs the clock CLK from the clock 11 at a constant cycle.
Is output, a process of incrementing the counter value each time CLK is output is executed (step ST3,
ST4). When the counter value reaches the set value and overflows, the time measurement counter 12 outputs an overflow signal indicating that (step ST
5, ST6).

When the overflow signal is output from the time measurement counter 12 in this manner, the synchronization circuit 13
In order to synchronize the OSD signal with the HSYNC including the video signal, as shown in FIG. 3, after the overflow signal is output from the time measurement counter 12, when the first HSYNC is input, the vertical display start signal is changed. Output (Step ST
7). When the vertical display start signal is output from the synchronization circuit 13, the OSD circuit 14 synchronizes with the vertical display start signal and outputs an OSD signal related to the character in FIG. 9 (the character is output from a circuit not shown). (Determined according to the character selection signal) (step ST)
8).

The synthesizing circuit 15 is connected to the OSD circuit 14
When the OSD signal is output from the device, the OSD signal is combined with the HSYNC including the video signal (step ST9), and a series of processes is completed. Even if HSYNC becomes unstable, the number of CLKs output at a constant cycle is always counted, thereby measuring the absolute time since VSYNC is output and determining the vertical display position of the character. Thus, as shown in FIG. 4, a noise bar appears on the screen, but the display of the character is displayed simultaneously with the image without vertical swing. However, the position where the noise bar appears can be controlled by a circuit (not shown), but it is necessary to set the set value of the time measurement counter 12 so that the noise bar and the character do not overlap.

As is apparent from the above, the first embodiment
According to the above, when VSYNC is input, the process of counting the number of CLKs output at a constant cycle is always started, and when the count number of the CLK reaches a set value,
Since the overflow signal is output and the OSD signal is synchronized with HSYNC including the video signal,
Even when fast-forwarding is performed at the same time as video playback, the character and the video playback video can be displayed simultaneously without vertical oscillation of the character display.

Embodiment 2 FIG. In the first embodiment, a case where the set value is set in the time measurement counter 12 in advance has been described. However, as shown in FIG. 5, a setting circuit (setting means) 16 for setting the set value of the time measurement counter 12 is provided. May be provided. Thus, there is an effect that the vertical position for displaying the character can be easily set or changed. Therefore, even if the character overlaps the noise bar, the existing time measurement counter 1
It is possible to avoid the overlapping display of the character and the noise bar without replacing 2.

[0025]

As described above, according to the present invention, when a vertical synchronizing signal is input, the process of counting the number of pulse signals output at a fixed period is started, and the counting of the pulse signals is started. When the number reaches the set value, a synchronization start signal indicating that fact is output, and the OSD signal is synchronized with the horizontal synchronization signal including the video signal. Even in such a case, there is an effect that the character and the video playback image can be simultaneously displayed without vertical swing of the display of the character.

According to the present invention, when the vertical synchronizing signal is input, the count number of the pulse signal is reset to zero,
When the count number of the pulse signal reaches a set value, the counter is configured by using a counter that outputs an overflow signal as a synchronization start signal, so that the OSD signal can be horizontally synchronized without using a complicated device. There is an effect that the signal can be synchronized.

According to the present invention, since the setting means for setting the set value in the counting means is provided, there is an effect that the vertical position for displaying the character can be easily set or changed. Therefore, even when the character overlaps the noise bar, there is an effect that the overlap display of the character and the noise bar can be avoided without replacing the device constituting the counting unit.

According to the present invention, when the first horizontal synchronization signal is input after the synchronization start signal is output from the counting means, the processing for synchronizing the OSD signal with the horizontal synchronization signal is executed. Therefore, there is an effect that the OSD signal can be reliably synchronized with the horizontal synchronizing signal even in the case of fast-forwarding simultaneously with the video reproduction.

According to the present invention, the pulse generating means is constituted by using a clock which generates a clock signal as a pulse signal. Therefore, a pulse signal having a constant period can be output without using a complicated device. There is an effect that can be done.

According to the present invention, when the vertical synchronizing signal is input, the process of counting the number of pulse signals output at a constant cycle is started, and when the count of the pulse signal reaches the set value. However, since a synchronization start signal indicating that fact is output and the OSD signal is synchronized with the horizontal synchronization signal including the video signal, the character display can be performed even when fast-forwarding simultaneously with video playback. There is an effect that a character and a video reproduced from a video can be simultaneously displayed without vertical vibration.

According to the present invention, when the first horizontal synchronization signal is input after the synchronization start signal is output, the OSD
Since the processing for synchronizing the signal with the horizontal synchronizing signal is performed, there is an effect that the OSD signal can be surely synchronized with the horizontal synchronizing signal even when fast-forwarding is performed simultaneously with video reproduction.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an OSD synthesis apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing an OSD synthesis method according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram showing waveforms of various signals.

FIG. 4 is a screen diagram showing an example of a video playback screen.

FIG. 5 is a configuration diagram illustrating an OSD synthesis apparatus according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram illustrating a conventional OSD synthesis apparatus.

FIG. 7 is a waveform diagram showing waveforms of various signals.

FIG. 8 is a screen diagram showing an example of a video playback screen.

FIG. 9 is a plan view showing a character.

FIG. 10 is a configuration diagram illustrating a conventional OSD synthesis apparatus.

FIG. 11 is a screen diagram showing an example of a video playback screen.

[Explanation of symbols]

11 clock (pulse generation means), 12 time measurement counter (counting means), 13 synchronization circuit (synchronization means), 14 OSD circuit (synchronization means), 15 synthesis circuit (synthesis means), 16 setting circuit (setting means) ).

Claims (7)

[Claims] 1. A pulse generating means for outputting a pulse signal at a constant period, and when a vertical synchronizing signal is inputted, a process for counting the number of pulse signals outputted from said pulse generating means is started, and When the count number of the pulse signal reaches the set value, the counting means outputs a synchronization start signal indicating that, and when the synchronization start signal is output from the counting means, the OSD signal is synchronized with the horizontal synchronization signal. An OSD synthesizing apparatus, comprising: a synchronizing unit for synchronizing the OSD signal synchronized by the synchronizing unit with a horizontal synchronizing signal including a video signal. 2. When a vertical synchronization signal is input, the count of a pulse signal is reset to zero, and when the count of the pulse signal reaches a set value, a counter that outputs an overflow signal as a synchronization start signal is used. 2. The OSD according to claim 1, wherein the counting means comprises a counting means.
Synthesizer. 3. The OSD synthesizing apparatus according to claim 1, further comprising setting means for setting a set value in said counting means. 4. The synchronizing means executes processing for synchronizing the OSD signal with the horizontal synchronizing signal when the first horizontal synchronizing signal is input after the synchronizing start signal is output from the counting means. The OSD synthesis apparatus according to any one of claims 1 to 3, wherein 5. The OSD synthesizing apparatus according to claim 1, wherein the pulse generating means is constituted by using a clock for generating a clock signal as a pulse signal. 6. When a vertical synchronizing signal is input, a process for counting the number of pulse signals output at a constant cycle is started, and when the count number of the pulse signal reaches a set value, the fact is notified. When the synchronization start signal is output while the synchronization start signal is output, a process of synchronizing the OSD signal with the horizontal synchronization signal is executed, and the synchronized OSD signal is converted into a horizontal synchronization signal including a video signal. An OSD combining method for combining with a signal. 7. The method according to claim 6, wherein when the first horizontal synchronization signal is input after the synchronization start signal is output, a process of synchronizing the OSD signal with the horizontal synchronization signal is executed. OSD synthesis method.