JP3468306B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and, more particularly, to an image signal of an image memory and an output of a CCD or other image pickup device by a television monitor synchronization signal of the image processing apparatus. The present invention relates to an image processing device that monitors both real-time image signals that are generated. 2. Description of the Related Art In a conventional image processing apparatus, even if an attempt is made to monitor a real-time image output from a CCD or other image pickup device using a synchronizing signal generated by a television monitor synchronizing signal generating circuit, the image is shifted and the television is shifted. A horizontal blanking period appears on the monitor screen, and as a result, real-time images cannot be correctly monitored. Hereinafter, this will be described. FIG. 5 is a block diagram of a conventional example of a television monitor synchronization signal generation circuit of an image processing apparatus, and FIG. 6 is a timing chart. H / 2CLK generator 2 is sync
When a start signal is input, an H / 2CLK signal is generated at a rate of one H / 2 at a time H / 2 based on the data of the H register 1 and the television clock TVCLK. Note that H is 6
Indicates 3.5 μs. [0004] H / 2CLK signal and TV clock TV
When CLK is input to the 7-bit counter 3, the decoder 4
, An H / 2CLK signal delayed by 89 cycles and a sync synchronous CLK signal delayed by 17 cycles are output. In addition,
The 89-cycle delay is a delay of 89 cycles of the TV clock from the H / 2CLK signal as shown, and the 17-cycle delay is a delay of 17 cycles of the TV clock from the H / 2CLK signal as shown. That is. [0005] The sync pattern ROM 5 is H / 2CLK.
Sync pattern data is generated in synchronization with the signal. The sync output unit 6 receives the sync synchronization CLK signal and the sync pattern data, and
The sync pattern data is output as a sync signal in synchronization with the synchronization CLK signal. [0007] 89 period delay H / 2CLK signal and syn
c pattern data is input to an AND gate 7, and
The output of the gate 7 is used as an image memory start signal. The image memory 8 receives the image memory start signal and starts outputting the image memory image signal. The CCD 9 generates a real-time image signal. Reference numeral 11 denotes a changeover switch. [0007] In summary, the synchronizing signal generating circuit for a television monitor as described above has a sync output unit 6 which outputs a sync signal.
monitor the image memory image signal according to the sync signal output in synchronization with the c-sync CLK signal, or
9 for monitoring a real-time image signal. [0008] Here, when an image is projected on the television monitor 10, the timing standard of the sync signal and the image signal is shown in FIG. 7. The start of generation of the sync signal CLK is synchronized with the sync signal.
c After receiving the start signal, the TV clock TVC
This is at the 17th cycle of LK, which is fixed. On the other hand, the timing of the CCD drive pattern can be freely changed by a program. And
The timing of the real-time image signal is determined by the timing of the CCD drive pattern. By the way, CCD
The focus of the determination of the timing of the driving pattern is determined from the viewpoint of facilitating image processing. Therefore, in most cases, the timing of the CCD drive pattern is such that the temporal relationship between the sync signal and the image signal deviates from the standard shown in FIG. 7 as shown in FIG. The image projected on the screen of the television monitor 10 is an improper image shifted in the horizontal blanking period as shown in FIG. 8B. The present invention solves the above-mentioned problem by configuring a television monitor synchronization signal generation circuit that makes the timing setting of the television monitor synchronization signal variable. [0010] A television monitor 120 for selectively supplying a real-time image signal output from the image sensor 100 and an image signal output from the image memory 90 is provided, and the timing setting of the synchronization signal is variable. An image processing apparatus having a television monitor synchronizing signal generating circuit is provided. FIG. 2 is a block diagram showing an embodiment of the present invention.
This will be described with reference to the timing chart of FIG.
When the sync start signal is input, the HCLK generator 30 receives the data of the H register 10 and the TV clock TV.
The HCLK signal is generated at a rate of one per 1H by CLK. Note that H indicates 63.5 μs. The H / 2 delay CLK generator 40 has an HCL
When the K signal and the TV clock TVCLK are input,
An HCLK signal delayed from the HCLK signal by a time H / 2 is generated. When the HCLK signal and the TV clock TVCLK are input, the sync delay CLK generator 50 converts the HCLK signal into the (TV clock TVCLK) signal.
Period) × (set value of sync delay register 20) = t
Sync sync CLK delayed by the time of _SDL is set to time H
/ 2. This delay timing is determined by selecting a set value stored in the sync delay register 20. The sync pattern ROM 60 generates sync pattern data in synchronization with the sync sync CLK. The sync output unit 70 outputs the sync sync CLK and s
When the sync pattern data is input, the sync pattern
Sync signal generated based on the
Output to the TV monitor 120 in synchronization with the sync clock CLK . The HCLK signal delayed by the time H / 2 from the HCLK signal and the sync pattern data of 8 bits
A specific bit in the data is input to an AND gate 80, and
Of the AND gate 80 when a specific bit of the
And the image memory start signal output of AND gate 80 open over bets. The CCD 100 generates a real-time image signal. Reference numeral 110 denotes a changeover switch. As described above, in the image processing apparatus having the synchronizing signal generating circuit for a television monitor according to the present invention, the sync delay CLK generator 50 has the HCL.
Sy at the timing delayed by t _SDL time from the K signal
nc synchronous CLK is generated. This delay timing is synchronized with the sync delay register 2
It can be adjusted by selecting the set value stored in 0. Therefore, the image signal of the image memory and C
Regardless of which real-time image signal obtained from the CD 100 is monitored, the timing of the sync sync CLK, which is the TV monitor synchronization signal, is adjusted by t _SDL in accordance with the image signal of the image memory or the timing of the real-time image signal. As a result, FIG.
4B, the horizontal synchronization pulse can be adjusted to the horizontal blanking period of the image signal, and as shown in FIG. 4B, proper monitoring can be performed without displaying the horizontal blanking period on the screen of the television monitor 120. Can be. Further, when inspecting a CCD product manufactured in a factory, the horizontal blanking period of an image signal may be positively projected on a television monitor screen and inspected. Even in such a case, the image processing apparatus of the present invention can be applied. That is, by selectively adjusting the set value stored in the sync delay register 20, the horizontal blanking period can be easily displayed on the television monitor screen.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating an embodiment of the present invention. FIG. 2 is a timing chart when an image memory image is monitored. FIG. 3 is a timing chart when a real-time image is monitored. FIG. 4A is a diagram illustrating a temporal relationship between a sync signal and an image signal, and FIG. 4B is a diagram illustrating a screen of a television monitor. FIG. 5 is a block diagram of a conventional example. FIG. 6 is a timing chart. FIG. 7 is a diagram showing a standard of timing of a sync signal and an image signal. FIG. 8A is a diagram illustrating a temporal relationship between a sync signal and an image signal, and FIG. 8B is a diagram illustrating a screen of a television monitor. DESCRIPTION OF SYMBOLS 10 H register 20 sync delay register 30 HCLK generator 40 H / 2 delay CLK generator 50 sync delay CLK generator 60 sync pattern ROM 70 sync output unit 80 AND gate 90 Image memory 100 CCD 110 Switching switch 120 TV monitor

Claims (1)

(57) [Claim 1] A television monitor to which a real-time image signal output from an image sensor and an image signal output from an image memory are selectively supplied , and a predetermined time when a sync start signal is input. 1 in H
The HCLK generator for generating the HCLK signal at the rate of each of the above , the SYNC delay register for setting the delay data, and the delay time calculated based on the set delay data.
Sync sync CLK delayed from the HCLK signal
Is a SYNC delay generated at a rate of one per time H / 2.
And Lee generator, read the SYNC pattern by the sync synchronization CLK
SYNC pattern ROM, the HCLK signal delayed by the time H / 2 , and the SYNC pattern ROM.
Read start obtained by ANDing with NC pattern
An AND circuit that outputs a signal to the image memory; and a sync signal based on the SYNC pattern.
And a SYNC output unit for outputting to a monitor .