JPH11245446A - Image signal synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize a position detection signal and a modulation signal without requiring any delay element by detecting the phase difference between a rotational position detection signal and a basic clock signal and regulating the delay time of the modulation signal stepwise according to the phase difference. SOLUTION: A phase difference detecting circuit 8 produces a phase difference signal PHD0-n ' corresponding to a specified delay state based on a basic clock signal VCLK, a rotational position detection signal BD and an n times reference clock signal nPCLK from an n times reference clock signal generating circuit 17. On the other hand, a modulation signal VDATA generated from a laser modulation circuit 3 is introduced to a modulation signal delay circuit 4 to produce a plurality of types of delayed modulation signal VDATA0-n . In response to the phase difference signal PHD0-n ' from the circuit 8, a delayed modulation signal selecting circuit 5 outputs a delayed modulation output signal VDATAOUT. Synchronization of a horizontal sync signal and a modulation signal can thereby be realized without requiring any delay element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal synchronizing circuit for outputting an image signal for generating a modulated beam for forming an image while repeatedly scanning based on a horizontal synchronizing signal to an engine while synchronizing with the horizontal synchronizing signal. Involved
In particular, the present invention relates to an image signal synchronization circuit used for a laser printer or the like.

[0002]

2. Description of the Related Art Generally, in a laser beam printer, a laser beam emitted from a semiconductor laser oscillator is scanned in the main scanning direction by rotation of a polygon mirror, so that a signal for modulating a laser beam for optical writing on a photosensitive member is converted into a polygon. It is necessary to synchronize with the rotation of a beam deflector such as a mirror. As a method of synchronizing the output beam and the rotation of the polygon mirror, when the laser beam is incident on a beam detector attached to a predetermined position slightly deviated from the image scanning area by the polygon mirror, the laser beam is output by the laser beam detector. VDAT which is a modulation signal of a laser beam is added to a BD (beam detect) signal
A method of synchronizing A (video data) signals is generally used. Here, since the BD signal is output in synchronization with the rotation of the polygon mirror, it can be regarded as a rotation position detection signal of the polygon mirror, in other words, a horizontal synchronization signal for each scan line.

In such a general synchronization method, conventionally, a clock having a frequency component several times that of a basic clock signal VCLK of VDATA, which is a modulation signal of the laser beam, is used as a reference clock signal PCLK. The synchronization is finely adjusted by synchronizing the signal with the rotational position detection signal BD.

FIG. 7 is a block diagram showing a synchronizing circuit of a laser beam printer which scans a laser beam by rotating the polygon mirror and performs optical writing.
Is a rotation position detector such as a beam detector that detects the incidence of the laser beam and outputs a rotation position detection signal (horizontal synchronization signal) BD, and sends the position detection signal BD to a synchronization frequency dividing circuit. 1 is the basic clock signal V of the VDATA
A reference clock signal generating circuit for generating a reference clock signal PCLK having a frequency component several times that of the reference clock signal CLK;
Is a synchronous frequency dividing circuit for synchronizing the reference clock signal PCLK with the rotational position detection signal BD and generating a basic clock VCLK. 3 is a circuit for applying a laser beam for optical writing onto the photoconductor based on the basic clock VCLK. A laser modulation circuit for generating a modulation signal VDATA for modulation,
Reference numeral 4 denotes a laser light emitting circuit which emits the laser beam based on a modulation signal VDATA from the laser modulation circuit.

In such a circuit configuration, the reference clock signal PCLK from the reference clock signal generating circuit 1 is input to the synchronous frequency dividing circuit 2 together with the rotational position detection signal BD.
By synchronizing the two signals and dividing the frequency of the reference clock signal PCLK and inputting it to the laser modulation circuit 3, a modulation signal VDATA can be obtained.

[0006] The laser beam of a laser beam printer generally changes either the ON or OFF state at a certain cycle. Here, the cycle for maintaining either the ON or OFF state is determined by the laser modulation signal VDATA. Defined as half cycle. At this time, the frequency of the modulation signal VDATA is represented by 1 / 2x, (2x: half cycle time).

Accordingly, in FIG. 8, the position detection signal BD of the polygon mirror falls, and the rising edge of the reference clock signal PCLK and the modulation signal VD which are the closest from the time when the signal again rises.
This indicates that ATA and ATA are synchronized. However, such a conventional technique does not devise to accurately synchronize the phase difference between the rotation detection signal BD and the modulation signal VDATA.

The applicant has proposed a circuit shown in FIG. 5 in a concurrently filed patent application. Such comparison techniques are:
A phase difference between the rotation position detection signal (horizontal synchronization signal) BD and the basic clock signal is detected, and phase difference signals PHD _{1 to} PHD _{1 to} PHD are detected.
HD _n , a phase difference detection circuit 8 for generating the modulation signal V
By delaying the DATA and the modulation signal delay circuit 4 for generating a delayed modulated signal VDATA ₁ ~VDATA _n of a plurality of (n), the phase difference signal PHD ₁ ~PHD _n from said plurality of delayed modulated signal (modulated signal VDATA And a delay modulation signal selection circuit 5 for selecting a modulation signal, and causing the laser emission circuit 6 to emit a laser beam based on the modulation signal VDATA selected by the delay modulation signal selection circuit 5.

Since the configuration of the main circuit of the comparative technique is the same as that of the embodiment described later, the details of its operation will be left to the description of the embodiment described later, but the problem will be mainly described with reference to FIGS. . First, the rotation speed of the polygon mirror, that is, the period of the rotation position detection signal BD and the reference clock signal PCL
Since the rotation position detection signal BD is usually asynchronous with K, the rotation position detection signal BD can be input at any time with respect to the reference clock signal PCLK. Therefore, the maximum value Φmax1 of the phase difference between the rotation position detection signal BD and the modulation signal VDATA at this stage is when the rotation position detection signal BD rises immediately after the rise of the reference clock signal PCLK, One cycle of the reference clock signal PCLK. Next, in order to suppress the phase difference between the rotation detection signal BD and the modulation signal VDATA, the phase difference Φx from the rotation detection signal BD to the rise of the reference clock PCLK is detected by the phase difference detection circuit 8, and the period T of the reference clock PCLK is detected. The modulation signal VDATA is delayed by the modulation signal delay circuit 4 for a time Φy obtained by subtracting the phase difference Φx time from the rotation detection signal BD to the rise of the reference clock PCLK from the time, and the delay modulation signal selection circuit 5
The fine adjustment of the synchronization between the rotational position detection signal BD and the modulation signal VDATA is performed by selecting the corresponding modulation signal VDATA.

In FIG. 6, a reference clock PC is used for fine adjustment of the synchronization between the rotational position detection signal BD and the modulation signal VDATA.
This shows that the modulation signal VDATA is delayed by Φy time obtained by subtracting the phase difference Φx time from the rotation detection signal BD to the rise of the reference clock PCLK from the cycle T time of LK.

[0011]

In the comparative technique, a plurality of delay elements are generally used in series as a phase difference detection circuit for detecting the phase difference Φx and a modulation signal delay circuit for delaying the modulation signal VDATA. (Series), the delay time variation of each delay element affects the synchronization accuracy of the rotational position detection signal BD and the modulation signal VDATA. In particular, since the delay element needs to use a delay time as short as about 10 ns because it is necessary to finely adjust the synchronization of the rotation position detection signal BD and the modulation signal VDATA, a printer having a low polygon mirror rotation speed can be used. In other words, if a rotational position detection signal BD having a long period is used, the number of delay elements connected in series necessarily increases, and the accumulation of the delay time variation of each delay element causes the rotation position detection signal BD and the modulation signal. There is a possibility that the synchronization accuracy of VDATA may be significantly affected. Therefore, the phase difference detection circuit and the modulation signal delay circuit require delay elements with little variation, but the use of such delay elements inevitably leads to an increase in cost.

An object of the present invention is to provide an image signal synchronizing circuit capable of synchronizing a position detection signal BD and a modulation signal VDATA with high accuracy, particularly an image signal synchronizing circuit in a laser printer, similarly to the above-mentioned comparison technique. In particular, the present invention is directed to the position detection signal BD and the modulation signal V.
An object of the present invention is to provide an image signal synchronizing circuit capable of performing high-accuracy synchronization with DATA without using a delay element.

[0013]

According to the present invention, an image signal for generating a modulated beam for forming an image while repeatedly scanning based on a horizontal synchronizing signal is synchronized with the horizontal synchronizing signal. An n-times reference clock signal generating means for generating an n-times frequency of the reference clock signal PCLK in an image signal synchronizing circuit for outputting to the engine side; and a horizontal synchronization signal and a basic clock signal based on the n-times reference clock signal. A plurality of delayed image signals by sequentially delaying an image signal modulated based on the basic clock signal based on the n-th reference clock signal by detecting a phase difference between the image signal and the phase difference detection means for generating a phase difference signal. Image signal delay means for generating, and a delayed image signal for selecting one image signal from the plurality of delayed image signals corresponding to the phase difference signal. Characterized by comprising a-option to delay the image signal selecting means.

In this case, the phase difference detecting means may include a shift register for sequentially delaying the horizontal synchronizing signal based on the n-times reference clock signal to generate a plurality of delayed synchronizing signals. A first latch circuit that generates a basic synchronization signal based on a horizontal synchronization signal and a basic clock signal, and generates a number of sampling signals corresponding to the plurality of delay signals based on the basic synchronization signal and the delay synchronization signal; It is preferable that the latch circuit includes a group of latch circuits and an adder that outputs a phase difference signal according to a delay state of the basic clock based on the sampling signal. In particular, in the present invention, a selector can be used instead of the adder. However, since noise is easily generated due to irregular reflection or the like at the time of beam scanning of the polygon mirror, the selector can also pick up these noises with high accuracy. Synchronous control cannot be performed. The present invention can eliminate such a point.

When this invention is applied to a synchronizing circuit used in a laser beam printer that scans a laser beam by rotating a polygon mirror to perform optical writing, as described in an embodiment described below, the incidence of the laser beam is controlled. A horizontal synchronization signal detector (rotation position detector) that detects and outputs a rotation position detection signal BD (horizontal synchronization signal)
A synchronization circuit for synchronizing a predetermined reference clock signal PCLK with the rotational position detection signal BD to generate a basic clock VCLK, and an n-times reference clock signal generation circuit for generating a frequency n times the reference clock signal PCLK When,
A laser modulation circuit for generating a modulation signal VDATA (image signal, video data) for modulating a laser beam for optical writing on the photoreceptor, and a plurality of signals by delaying the modulation signal by an n-fold reference clock signal generating a modulation signal delay circuit for generating a delayed modulated signal VDATA ₁ ~VDATA _n, the n-fold the reference clock signal by detecting the phase difference between the and the rotational position detection signal reference clock signal phase difference signal PHD ₁ ~PHD _n a phase difference detection circuit, a delay modulation signal selection circuit for selecting the phase difference signal PHD ₁ ~PHD _n from said plurality of delayed modulated signal (including modulation signal VDATA), composed of a laser emitting circuit for emitting the laser beam Preferably.

According to this configuration, the phase difference between the rotational position detection signal BD and the basic clock signal VCLK is detected by the n-times reference clock signal, and the delay time of the modulation signal VDATA is increased by the n-times reference clock based on the phase difference. a plurality of delay modulated signal based on a signal VDATA ₁ ~VDA
Stepwise can be adjusted in response to the TA _n.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention unless otherwise specified, and are merely illustrative examples. Only. FIG. 1 is a block diagram showing an image signal synchronizing circuit of a laser beam printer according to an embodiment of the present invention. Numeral 7 denotes a beam detector for detecting the incidence of the laser beam and outputting a rotational position detection signal (horizontal synchronization signal) BD. And sends the position detection signal BD to the synchronous frequency dividing circuit 2. 1 is a reference clock signal generation circuit for generating a reference clock signal PCLK having a frequency component several times that of the VDATA basic clock signal VCLK;
Reference numeral 2 denotes a synchronization frequency dividing circuit for synchronizing the reference clock signal PCLK with the rotational position detection signal BD and generating a basic clock VCLK. Reference numeral 3 denotes an optical writing circuit on a photosensitive member (not shown) based on the basic clock VCLK. This is a laser modulation circuit that generates a modulation signal VDATA for modulating a laser beam. These components are the same as those of the above-described conventional technology.

In this embodiment, similarly to the comparison technique, the rotational position detection signal (horizontal synchronization signal) BD
And the phase difference between the basic clock signal and the phase difference signal P
A plurality (n) of phase difference detection circuits 8 for generating HD _{1 to} PHD _n and a delay of the modulation signal VDATA
Delayed modulated signal VDATA ₁ and the modulation signal delay circuit 4 for generating a ~PHD _n, the phase difference signal PHD ₁ ~PHD _n from said plurality of delayed modulated signal (including modulation signal VDATA)
And a laser light emitting circuit 6 for emitting a laser beam based on the modulation signal VDATA selected by the delay modulation signal selection circuit 5, and further includes the reference signal An n-times reference clock signal generation circuit 17 for generating a frequency n times the frequency of the clock signal PCLK is provided.

Next, a main circuit of the present embodiment will be described with reference to FIG. First, the phase difference detection circuit 8 sequentially outputs the quadrupled reference clock signal nPCLK based on the n-times reference clock signal nPCLK output from the n-times reference clock signal generation circuit 17 and the rotational position detection signals BD and BD _{1 to} BD ₃ on the preceding stage.
Delay signals BD _{1 to} BD ₄ delayed by one cycle of CLK (１ ／ T (T: cycle of VCLK)) are output.
Latch circuits (flip-flops) F / F _{2 to} F / F ₅
And a basic synchronization signal PH based on the rotational position detection signal BD and the basic clock signal VCLK.
A latch circuit F / F ₁ for generating the basic synchronization signal PH
Sampling signal P based on the delay signals BD _{1 to} BD ₄
Latch circuits for generating the _{H 1 ~PH 4 F / F 6} ~F / F 9, and an adder for outputting a phase difference signal PHD ₀ ~PHD ₂ corresponding to the delay state based on the sampling signal PH ₁ ~PH ₄ consisting of ADD _1.

Next, the configuration of the phase difference detection circuit 8 will be described in detail. As described above, the rotational position detection signal B
The maximum value of the phase difference between D and the modulation signal VDATA is the case where the rotation position detection signal BD rises immediately after the rise of the basic clock VCLK, and is almost one cycle of the basic clock VCLK. The rotation detection signal BD and the modulation signal VDAT
When it is desired to suppress the phase difference of A to 1 / n (n is a natural number) of the modulation signal VDATA, for example, 1/4, the quadruple reference output from the quadruple reference clock signal generation circuit 17 as shown in FIG. sequentially by the clock signal nPCLK and front side rotation position detection signal BD and BD ₁ ~BD _3, 4 times the reference clock signal one period of nPCLK (1 / 4T (T: VCLK
)), And delay signals BD _{1 to} BD ₄ delayed by minutes are output.

And F / F₆~ F / F₉In the signal BD
Set (falling), signal PH and delay signal BD₁~ B
D_FourAnd the sampling signal PH₁~ PH_FourIs raw
Is done. And adder ADD₁F / F₆~ F / F₉Yo
Sampling signal PH₁~ PH_FourIs entered and the
Sampling signal PH₁~ PH_FourPhase difference corresponding to the number of additions
Signal PHD₀~ PHD_TwoSelect the adder ADD₁Coming out
Power. In the present embodiment, the adder ADD₁Instead of
Can be substituted by using a selector, but the polygon mirror
-Noise occurs due to diffuse reflection etc. during beam scanning
The selector also picks up these noises to make
Synchronous control cannot be performed frequently. For example, selector
Choose and PH_FourShould be selected, but the noise pal before that
PH in response to₁May be chosen. Meanwhile
Arithmetic ADD₁In the case of, P
H₁To F / F_FiveIs the adder ADD₁Even if output to the side
The sampling signal PH₁~ PH_FourRank corresponding to the number of additions
Phase difference signal PHD₀~ PHD_TwoTo select and output
Tte PH When selecting 2, the adjacent PH_ThreeSelect
PH even more than that_FourThere is no choice.

FIG. 9 shows the operation of the adder ADD.₁Addition form of
Show, PHD₀Is the first bit, PHD 1 is the second bit, P
HD_ThreeIs the third bit, and PHD₀~ PHD_ThreeFormed by
PH by binary number₁~ PH_FourThat you have selected one of
Is set so that For example, PHD₁When set
The "PHD_Three, PHD_Two, PHD₁"Is" 001 "
Where "001" in binary represents "1" in decimal
To PH₁It turns out that was selected.

On the other hand, as shown in FIG.
The latch circuit F / F of the phase difference detection circuit 8_Two~ F / F_Five
Four latch circuits connected in series according to the group
F / F_Ten~ F / F₁₃From a shift register composed of
The four latch circuits F / F 1₀~ F / F₁₃The laser
Modulation signal VDATA generated by modulation circuit 3 and n-times base
The n-times reference clock output from the quasi-clock signal generation circuit 17
Shift (delay) by one cycle of the lock signal nPCLK
F / F_Ten~ F / F₁₃4 types of delayed modulation signals
No. VDATA₁~_FourIs generated.

The delay modulation signal selection circuit 5 includes a selector SEL
₁Where the phase difference signal PHD₀~ PHD_Two
Selector SEL₁Using the delay modulation signal VDAT
A₁~ Select 4 and output the delay modulation output signal synchronized with the BD signal
Get VDATAOUT.

Next, the overall operation of the embodiment will be described with reference to FIG. 1 and time charts shown in FIGS. FIGS. 2 and 3 show a case where the frequency of the reference clock signal PCLK matches the frequency of the basic clock signal VCLK for the sake of simplicity. In FIG. 1, first, a rotational position detection signal BD output from the rotational position detector 7 is shown.
The reference clock signal PCLK output from the reference clock signal generation circuit 1 generates a basic clock signal VCLK in the synchronous frequency divider 2.

The basic clock signal VCLK and the rotation position detection signal BD are introduced into a phase difference detection circuit 8, and the rotation position detection signal BD is converted by a latch circuit F / F ₁ in the detection circuit 8 as shown in FIG. The latch is performed at the first rising edge of the basic clock signal VCLK from the rising edge of the signal BD to generate the synchronization signal PH. The rotational position detection signal BD is delayed by one cycle of the n-times reference clock signal nPCLK output from the n-times reference clock signal generation circuit 17 using a shift register constituted by latch circuits F / F _{2 to} F / F _5. a plurality of generating a delay rotational position detection signal BD ₁ ~BD ₄ was introduced into the latch circuit F / F ₆ ~F / F ₉ corresponds to the delay rotational position detection signal BD ₁ ~BD ₄ to delay the rotational position detection in the signal BD ₁ ~BD _4, the sampling signal by sampling the synchronization signal PH PH ₁ ~PH ₄ adders ADD ₁
Output to As a result, the addition operation shown in FIG. 9 is performed based on sampling signals PH _{1 to} PH ₄ , and adder ADD
Obtaining a phase difference signal PHD ₀ ~PHD _{2 throughout.}

On the other hand, the modulation generated by the laser modulation circuit 3
The signal VDATA is introduced into the modulation signal delay circuit 4 and
As described above, the F / F of the delay circuit 4_Ten~ F / F₁₃By
Several types of delayed modulation signal VDATA₁~ VDATA_FourGenerate a
I do. (See FIG. 4) Here, the phase difference signal PHD₀~ PHD_TwoDelay delay
Tuning signal selection circuit SEL 1 using the delay modulation output signal VD
Get ATAOUT.

The flow of such a signal is described with reference to the timing charts of FIGS. 2 and 3. FIG. 2 shows a case where the phase difference between the rotational position detection signal BD and the basic clock VCLK is a half cycle of the basic clock VLCK. Is shown. And in this chart, for the basic clock VCLK is risen between the sampling signal PH ₂ and PH _3, a phase difference signal PHD ₀ ~PHD ₂ based on the delay rotation position detection signal BD ₃ and BD ₄ " 110 "output to the PH ₃ is output that has been selected to position modulation signal selection circuit side, selects the delay modulated signal VDATA _1, delayed modulated output signal VD
It is shown that ATAOUT is obtained. This will be described with reference to FIG. 2. Each F / F _{1 to} F / F ₅ , F / F ₁₀
When the delay amount of the to F / F ₁₃ is a 10 ns, when the basic clock VCLK rises in PH _3, it determines that .phi.x = 30 ns delay occurs in the base clock VCLK.
On the other hand, when the period T of VCLK is 40 ns, VDA
Selecting a delayed modulated signal VDATA ₁ of the TA 40-30 = 10ns (T-φx = φy).

The timing chart of FIG. 3 shows a case where the phase difference between the rotation position detection signal BD and the basic clock VCLK is minimum and maximum, and the maximum value of the phase difference between the rotation position detection signal BD and the modulation output signal VDATAOUT is n times. Latch circuit F / F output by reference clock signal nPCLK
Indicates that an latch circuit component of the delay time of _{2 ~F} / F _5. That is, the rotation position detection signal BD and the modulation signal VDA
Indicating that TA synchronization accuracy is 1 latch circuits worth of delay time of the latch circuit _{F / F 2 ~F / F 5} .

[0030]

As described above, according to the present invention, the position detection signal BD and the modulation signal VDATA can be synchronized with the n-times reference clock signal without fine adjustment of the phase of the basic clock used in the laser modulation circuit. Since a delay time corresponding to one latch circuit output based on nPCLK is realized, a highly accurate synchronous circuit can be obtained at low cost. In addition, the present invention provides a method of controlling the position detection signal BD and the modulation signal VD without using a delay element.
Since synchronization with ATA is realized, high-precision synchronization can be obtained without considering the variation of delay elements.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an image signal synchronization circuit of a laser beam printer according to an embodiment of the present invention.

FIG. 2 is a time chart showing the overall operation of the embodiment of FIG. 1;

FIG. 3 shows a rotational position detection signal BD and a basic clock VCL.
FIG. 7 is a time chart showing a case where the phase difference of K is minimum and maximum.

FIG. 4 shows a specific circuit configuration of a phase difference detection circuit, a modulation signal delay circuit, and a delay modulation signal selection circuit, which are main components of the present invention.

FIG. 5 is a block diagram illustrating an image signal synchronization circuit of a laser beam printer according to a comparative technique.

FIG. 6 is a time chart illustrating the overall operation of the comparative technique.

FIG. 7 is a block diagram showing an image signal synchronization circuit of a conventional laser beam printer.

FIG. 8 is a time chart showing the entire operation of the conventional technique.

9 is a示表view the addition form of the adder ADD ₁ shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference clock signal generation circuit 2 Synchronous frequency dividing circuit 3 Laser modulation circuit 4 Modulation signal delay circuit 5 Delay modulation signal selection circuit 6 Laser light emitting circuit 7 Rotational position detector 8 Phase difference detection circuit 17 n times reference clock signal generation circuit

Claims (2)

[Claims] An image signal synchronizing circuit for outputting an image signal for generating a modulated beam for forming an image while repeatedly scanning based on a horizontal synchronizing signal to an engine while synchronizing with the horizontal synchronizing signal, wherein the reference clock signal N-times reference clock signal generation means for generating an n-times frequency of PCLK; phase difference detection for detecting a phase difference between a horizontal synchronization signal and a basic clock signal based on the n-times reference clock signal to generate a phase difference signal Means and image signal delay means for sequentially delaying an image signal modulated based on the basic clock signal based on the n-times reference clock signal to generate a plurality of delayed image signals, and corresponding to the phase difference signal Delay image signal selecting means for selecting a delayed image signal for selecting one image signal from the plurality of delayed image signals. And an image signal synchronizing circuit. 2. A shift register comprising: a group of latch circuits for generating a plurality of delay synchronization signals by sequentially delaying the horizontal synchronization signal based on the n-times reference clock signal; A first latch circuit that generates a basic synchronization signal based on a signal and a basic clock signal, and a latch circuit that generates a number of sampling signals corresponding to the plurality of delay signals based on the basic synchronization signal and the delay synchronization signal 2. The image signal synchronization circuit according to claim 1, further comprising a group, and an adder that outputs a phase difference signal according to a delay state of the basic clock based on the sampling signal.