JPH0669086A - Semiconductor device - Google Patents

Abstract

PURPOSE:To determine the position of a chip inside a wafer by detecting the state of a fuse element which can be cut being matched to the position of the chip and outputting it externally. CONSTITUTION:By cutting a fuse element 1 according to the position of a chip inside a wafer, the output of a 2-input NAND gate 7 changes according to the state of the fuse element 1 when a TEST signal is set to a high level and the output signal is output externally, thus determining the position inside the wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, obtaining many non-defective products from one wafer leads to cost reduction. Therefore, efforts are being made to design the size of the chip as small as possible. However, even if it is made small, the minimum necessary circuit must be included. In addition, there is a limit in the case where the capacity is quadrupled in three years like Dynamic Ram. Therefore, by increasing the size of the wafer, the number of chips that can be produced per wafer is also increased. However, it is technically difficult to increase the size of the wafer, and 8-inch wafers are currently being used for mass production.

Further, simply increasing the size of the wafer does not increase the number of non-defective products. The larger the wafer, the more difficult it is to create a uniform surface. In addition, due to temperature changes during manufacturing, the surface of the wafer becomes non-uniform due to warping of the wafer. Therefore, variations occur in transistor characteristics and the like within the wafer surface. As shown in FIG. 4, there are a large number of semiconductor chip regions 101 in the wafer 100, but the semiconductor chip is provided with an identification mark (not shown) so that the position within the wafer can be known to some extent.
It can be used for production control such as defect distribution.

[0004]

In this conventional semiconductor device, the identification mark is provided on the semiconductor chip.
After assembly, it was inconvenient because the position in the wafer could not be known unless the chip was exposed again.

[0005]

The semiconductor device of the present invention comprises:
A semiconductor chip is provided with an identification signal generating means including a fuse element having one end connected to a fixed potential supply terminal and a fuse test circuit that receives a test signal and generates a detection signal according to the potential level of the other end of the fuse element. It is said that it is being done.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, in a first embodiment of the present invention, a fuse element 1 and a fuse test circuit 2 are provided for each semiconductor chip.

The fuse element is one in which electrodes such as an aluminum film are provided on both ends of a fuse body such as a polysilicon film and may be the same as that used for a redundant circuit or the like. If necessary, the polysilicon film is irradiated with laser light or the like to be cut. One end of the fuse element is connected to the power supply terminal Vcc, and the other end is connected to the fuse test circuit 2. The input end (the other end of the fuse element) of the fuse test circuit 2 is connected to the ground end via the enhancement-type MOST 3. The potential at the input end is supplied to the gate of the MOST 3 via the inverter 4 and is also supplied to the 2-input NAND gate 7 via the inverters 5 and 6. Two
The test signal TEST is supplied to the input NAND gate 7.

For example, if the fuse element 1 of the semiconductor chip in the first region is not blown but is blown in the second region in order to divide the region in the wafer into two regions, In the chip in the first region, the potential of the contact A is always fixed at high level. When it is desired to know the state of the fuse element, if the test signal TEST is changed from low level to high level as shown in FIG.
Since the output of the inverter 4 is always at the low level, the output signal WADD changes from the low level to the high level by the 2-input NAND gate 7. In the case of the chip in the second region, the potential of the contact A is fixed to the low level, so that when the test signal changes from the low level to the high level, the output of the inverter 4 is always at the high level.
The output WADD of the input NAND gate 7 is at a low level. By outputting this WADD signal from the output pin (external terminal), it is possible to know which region of the wafer the semiconductor chip was on.

In general, if n circuits of FIG. 1 are provided on a semiconductor chip and are output to n output pins, 2 ⁿ kinds of identification signals can be obtained by a combination of cutting and non-cutting fuse elements. Therefore, it is possible to subdivide and know the region in the wafer where the semiconductor chip was present.

The test signal may be supplied from the input pin to the fuse test circuit via the bonding pad of the semiconductor chip, or may be supplied from the test circuit in a semiconductor device having a built-in test circuit. You may

Referring to FIG. 3, the second embodiment of the present invention has two fuse elements 1a and 1b and two fuse test circuits 2a and 2b. In the fuse test circuit 2a, the test signal TEST outputs the counter circuit 8
It is applied to the 2-input NAND gate 7a via a. The output signal of the counter circuit 8a becomes the test signal of the fuse test circuit 2b and is applied to the 2-input NAND gate 7b via the counter circuit 8b. 2 input NA
The output terminals of the ND gates 7a and 7b supply the commonly connected signal WADD.

When the wafer region is divided into four regions for identification, for example, both the fuse elements 1a and 1b are not blown in the first region, and the fuse element 1a is cut in the second region, but the fuse 1b is not cut. It is assumed that 1a is not cut in the third region, but 1b is cut in the third region, and both 1a and 1b are cut in the fourth region. In the semiconductor chip in the second region, the contact B is fixed at high level and the contact C is fixed at low level. If the test signal TEST is changed from low level to high level in order to know the state of the fuse element, the output of the inverter 6 is low level if the output contact D of the counter circuit 8a is set to high level. The output signal of the 2-input NAND gate 7a changes from low level to high level. Further, when the contact D changes to the high level, the counter circuit 8b operates, the output contact E becomes the high level, and the output of the inverter 6b becomes the high level. Therefore, the output signal of the 2-input NAND gate 7b becomes Change to low level. If the delay times are made different by means such as making the bit numbers of the counter circuits 8a and 8b different,
From one output pin (WADD) to the fuse elements 1a, 1
There is an advantage that the state of b can be known. The counter 8a is not always necessary, and the test signal TEST may be directly applied to the 2-input NAND gate 7a.

[0013]

As described above, according to the present invention, the semiconductor chip is provided with the fuse element which can be cut by the laser beam or the like and the means for electrically detecting the presence or absence of the cut and generating the identification signal. By cutting according to the position within the wafer, it is possible to detect whether or not the fuse element is cut by inputting a test signal, and to know the position of the semiconductor chip within the wafer even after assembly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart of the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a plan view of a conventional wafer.

[Explanation of symbols]

 1, 1a, 1b Fuse element 2, 2a, 2b Fuse test circuit 3, 3a, 3b MOST 4, 4a, 4b Inverter 5, 5a, 5b Inverter 6, 6a, 6b Inverter 7, 7a, 7b Inverter 8a, 8b Counter

Claims (1)

[Claims] 1. An identification signal generating means comprising a fuse element having one end connected to a fixed potential supply terminal and a fuse test circuit for receiving a test signal and generating a detection signal according to the potential level of the other end of the fuse element. Is provided on a semiconductor chip.