JPH06349926A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be restrained from increasing in chip area due to a provided test pad, to lessen in cost, set free from laminations imposed due to a chip area, simplify in test control procedure, and enhance the design efficiency of a test program or the like. CONSTITUTION:In a gate array integrated circuit and a digital/analog hybrid integrated circuit, test pads TP1 and TP2 used for test control are provided outside a corresponding chip CHP2 forming region or inside a scribing zone SZ used for splitting chips. A metal wiring layer, which is provided between the test pads TP1 and TP2 and an inner integrated circuit LC provided inside the corresponding chip CHP2, is kept in a cutoff state by a fuse after test control, and a guard ring GR kept in a cutoff state when the metal wiring layer is arranged in connected again in mass production.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a technique which is particularly effective when used for a gate array integrated circuit and a digital / analog mixed integrated circuit which require a test pad for test adjustment. It is a thing.

[0002]

2. Description of the Related Art There is a gate array integrated circuit in which various kinds of logic integrated circuit devices can be optionally constructed by adding different metal wiring layers to each kind of logic elements such as transistors arranged in rows. There is also a digital / analog mixed integrated circuit such as a hard disk driver in which a digital circuit including a combination of logic elements and an analog circuit such as an amplifier circuit and an oscillation circuit are formed on the same chip (semiconductor substrate). In these semiconductor devices, test adjustment for function confirmation and characteristic setting is performed at the product development and mass production stages, and a test pad for that purpose is provided.

The gate array integrated circuit is described, for example, on pages 166 to 192 of Nikkei Electronics, published by Nikkei McGraw-Hill, Inc., September 9, 1985.

[0004]

In recent years, high integration and large scale of gate array integrated circuits and mixed digital / analog integrated circuits have been remarkable, and the number of pads including test pads required has been increasing accordingly. It is in. However, in the conventional gate array integrated circuit, mixed digital / analog integrated circuit, and the like, a test pad that is meaningless after the test adjustment is formed in the chip formation region.
Therefore, the chip area of the gate array integrated circuit and the digital / analog mixed integrated circuit is increased, which hinders the cost reduction. Conversely, if the number of pads is reduced, the test adjustment process becomes complicated and the test program There is a problem in that the design efficiency of such items as described above decreases.

An object of the present invention is to suppress an increase in chip area due to the provision of test pads and to reduce the cost of a semiconductor device. Another object of the present invention is to solve the constraint on the number of pads that depends on the chip area, simplify the test adjustment processing of the semiconductor device, and improve the design efficiency of the test program and the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a gate array integrated circuit, a digital / analog mixed integrated circuit, etc., a test pad for test adjustment is formed outside a corresponding chip forming region, that is, in a scribe region for cutting a chip, or a predetermined pad of an adjacent chip. Or combine multiple chips into a Taegu chip to form
The metal ring layer provided between the test pad and the internal integrated circuit of the corresponding chip is cut after the test adjustment is completed, and the guard ring that was in the cut state for arranging this metal wiring layer is put into mass production. Is connected.

[0008]

According to the above means, the increase of the chip area due to the provision of the test pad can be suppressed without lowering the reliability of the gate array integrated circuit and the digital / analog mixed integrated circuit, and the cost can be reduced. In addition to being able to achieve the above, it is possible to solve the constraint on the number of pads that depends on the chip area, simplify the test adjustment processing, and improve the design efficiency of the test program and the like.

[0009]

1 is a plan layout view of an embodiment of a wafer WAF in which a gate array integrated circuit to which the present invention is applied is formed, and FIG. 2 shows the wafer WAF on the surface of the wafer WAF in FIG. An enlarged layout diagram of an embodiment before a test of a chip of a gate array integrated circuit to be formed (here, a test represents a test adjustment process including a test and an adjustment, that is, trimming and the like) is shown. 3 and 4 are block diagrams of one embodiment of the chip of the gate array integrated circuit of FIG. 2 before and after the test, respectively, and FIG.
In the figure, an enlarged layout drawing of one embodiment in the mass production state is shown. Based on these drawings, the outline of the arrangement of the gate array integrated circuit of this embodiment and the test adjustment process and its features will be described. In this example,
The wafer WAF is made of, but not limited to, single crystal silicon, and the gate array integrated circuit has P-channel and N-channel MOSFETs (metal oxide semiconductor type field effect transistors. In this specification, MOSFETs are used as insulated gate type electric fields. It is basically configured by a CMOS (complementary MOS) circuit in which effect transistors are collectively called. Further, in the following description regarding the layout, the upper and lower sides and left and right sides of the wafer and the chip surface are represented by the positional relationship of each layout drawing.

In FIG. 1, the gate array integrated circuit of this embodiment is formed in a grid pattern on one wafer WAF surface with a predetermined number, and the gate array integrated circuit is cut into chips on each side. Scribe area is provided.

[0011] Here, three chips CH that are shaded
Focusing on P1 to CHP3, each gate array integrated circuit has an internal integrated circuit LC arranged in the central portion of the chip occupying most of its area as a basic constituent element, as illustrated in FIG. A plurality of internal pads P for bonding with corresponding external terminals are provided around the internal integrated circuit LC.
AD is provided, and on the outside, along the outer periphery of the chip,
A guard ring GR including a predetermined diffusion layer and a metal wiring layer formed thereabove is provided. Guard ring GR
Is supplied to the ground potential of the circuit. Guard ring GR
Surrounds a substantial formation area of each chip,
A scribe region SZ having a predetermined width for cutting the chip is provided on the outer side thereof.

In this embodiment, two test pads TP1 and TP2 are provided on the upper scribe region SZ of each chip, that is, outside the formation region thereof. Also,
The guard ring GR of each chip is cut at a position close to these test pads, and a metal wiring layer for connecting the test pads TP1 and TP2 to the corresponding internal integrated circuit LC of the chip is cut at this cut portion. Laid out.

By the way, as shown in FIG. 3, the internal pads PAD of each chip are provided with a power supply voltage supply pad VCC and a ground potential supply pad VSS for supplying operating power to the gate array integrated circuit, and m pads. Data input pads DI1 to DIm and n data output pads DO
1 to DOn are included. The internal integrated circuit LC operates using the power supply voltage VCC and the ground potential VSS supplied via the power supply voltage supply pad VCC and the ground potential supply pad VSS as operation power supplies, and the data input pads DI1 to DIm.
A predetermined logical operation process is performed on the input data DI1 to DIm supplied via the. Then, as a result, the output data DO1 to DOn are selectively formed and output to the outside via the data output pads DO1 to DOn.

Further, in the internal integrated circuit LC, predetermined probe characteristics are selectively set in accordance with a test signal supplied through the test pads TP1 and TP2 during the probe test in the wafer state of the gate array integrated circuit. Selectively perform a predetermined test operation. In this embodiment, the test pads TP1 and TP2 of each chip are formed outside the corresponding chip formation region, that is, in the scribe region SZ, as described above. Therefore, the provision of the test pads TP1 and TP2 does not increase the substantial chip area of the gate array integrated circuit, which can promote cost reduction of the gate array integrated circuit. In addition, since test pads can be added without increasing the chip area of the gate array integrated circuit, it is possible to adopt an efficient test adjustment method without being restricted by the number of chips. Can be simplified and the design efficiency of the test program etc. can be improved.

The probers used for the test adjustment of the gate array integrated circuit are arranged in two rows in the front and back, so to speak, as the needles for contacting the pads. Therefore, it is possible to simultaneously contact the corresponding needles with the internal pad PAD provided in the formation area of each chip and the test pads TP1 and TP2 provided outside the formation area, that is, in the scribe area SZ. Further, in the scribe region SZ, as is well known, a target for alignment required in an element forming process and a metal wiring layer forming process and a tag for process evaluation are formed, but the test pads TP1 and TP2 are not formed. There is no particular problem because the formation may be performed after all the element forming steps are completed.

On the other hand, in the gate array integrated circuit of this embodiment, as shown in FIG. 3, two fuses F1 and F2 are provided between the test pads TP1 and TP2 and the corresponding internal integrated circuit LC of the chip. Is provided. These fuses are cut by, for example, irradiating a predetermined laser beam after the test adjustment of the gate array integrated circuit is completed. As a result, after the chip is cut, the test pads TP1 and TP2 and the internal integrated circuit LC of the corresponding chip can be completely separated as illustrated in FIG. The breakdown can be prevented and the reliability of the gate array integrated circuit can be improved.

Further, in the gate array integrated circuit of this embodiment, the cutting portion of the guard ring GR provided for arranging the metal wiring layer between the test pads TP1 and TP2 and the internal integrated circuit LC of the corresponding chip. However, in the mass production state, as illustrated in FIG. 5, the connection state is returned by changing a part of the photomask for the metal wiring layer. At this time, the test pads TP1 and TP2
It goes without saying that all or part of the metal wiring layer between the internal integrated circuit LC of the chip and the internal integrated circuit LC of the corresponding chip is not formed. As a result, in the gate array integrated circuit that is shipped as a mass-produced product, the guard ring GR is formed without being cut, which further improves the reliability of the gate array integrated circuit.

FIG. 6 is an enlarged layout view of the second embodiment before the test of the chip of the gate array integrated circuit formed on the surface of the wafer WAF of FIG. FIG. 2 shows a second gate array integrated circuit to which the present invention is applied.
The outline of the embodiment and its features will be described. Since this embodiment basically follows the embodiment of FIGS. 2 to 5, a description will be added to the parts different from this. Further, since the following description will be focused on the chip CHP2, the chip CHP1 is an adjacent chip above it, and the chip CHP3 is an adjacent chip below it.

In FIG. 6, in the gate array integrated circuit of this embodiment, the predetermined pads PADp and PADq provided outside the formation region of the corresponding chip CHP2, that is, inside the formation region of the adjacent chip CHP1 are used as test pads TP1.
And TP2. Here, the pads PADp and PADq may be connected to external terminals as meaningful internal pads when viewed from the adjacent chip CHP1, or may be test pads for other test adjustment processing. Good. In either case, for example, when the test adjustment for the chip CHP2 is performed, the adjacent chip CHP1 is not connected to the test apparatus and cannot be supplied with the operating power, so that these pads are also used except for a special case. Does not cause problems.

The pads PADp and PADq, that is, the test pads TP1 and TP2 are coupled to the internal integrated circuit LC of the chip CHP1 and the internal integrated circuit LC of the corresponding chip CHP2 via a predetermined metal wiring layer. . The same pads PADp and PADq provided on the chip CHP2 are also used as the test pads TP1 and TP2 of the adjacent chip CHP3. Therefore, part of the guard ring GR of each chip is cut on the upper side and the lower side, and the test pads TP1 and TP2 are coupled to the internal integrated circuit LC of the corresponding chip via the cut portion. The metal wiring layer is laid out.

As described above, in the gate array integrated circuit of this embodiment, the test pads TP1 and TP2 can be realized by also using the internal pads of the adjacent chips, in other words, without forming the pads in the scribe region SZ. Therefore, while obtaining the same effect as that of the first embodiment,
Further cost reduction of the gate array integrated circuit can be promoted.

FIG. 7 shows a plan layout view of another embodiment of the wafer WAF in which the gate array integrated circuit to which the present invention is applied is formed, and FIG. 8 shows the wafer W of FIG.
An enlarged layout view of one embodiment of the chips CHP1 to CHP4 and the teg chip TEG1 formed in the AF is shown. Based on these drawings, the outline and features of the third embodiment of the gate array integrated circuit to which the present invention is applied will be described. It should be noted that this embodiment is similar to that shown in FIGS.
Since the embodiment is basically followed, description will be added only to the parts different from this.

In FIG. 7, the gate array integrated circuit of this embodiment is formed in a grid pattern on one wafer WAF surface with a predetermined number, and in the middle thereof, for example, a layout area for two gate array integrated circuits is formed. Thus, the six teg chips TEG1 to TEG6 shared by a predetermined number of gate array integrated circuits are formed. A scribe region having a predetermined width for cutting the gate array integrated circuit as a chip is provided on the four sides of the gate array integrated circuit and the chip.

Here, each of the TEG chips TEG1 to TEG6 is provided with a large number of pads arranged in two rows along its four sides, as represented by the TEG chips TEG1 in FIG. These pads are not particularly limited, but after being divided into groups of four, they are respectively coupled to adjacent chips CHP1 to CHP4 via the corresponding four metal wiring layers to supply the power supply voltage supply pad VCC and the ground potential. It functions as the pad VSS and the test pads TP1 and TP2. When the predetermined test adjustment process is performed, the TEG chips TEG1 to TEG6 are sequentially coupled to the test apparatus via the prober, and the test adjustment processes of the corresponding predetermined number of gate array integrated circuits are collectively performed at the same time via these TEG chips. Is done.

As described above, in this embodiment, the test pads TP1 and TP2, including the power supply voltage supply pad VCC and the ground potential supply pad VSS, are integrated outside the corresponding chip formation region, that is, the teg chips TEG1 to TEG6. Since it is formed, the test adjustment processing of the corresponding predetermined number of gate array integrated circuits can be realized in parallel without moving the prober. As a result, it is possible to further reduce the cost of the gate array integrated circuit, further simplify the test adjustment process, and further improve the design efficiency of the test program and the like.

By applying the present invention to a semiconductor device such as a gate array as shown in the above embodiment, the following operational effects can be obtained. (1) In a semiconductor device such as a gate array integrated circuit,
A test pad for test adjustment is formed outside the corresponding chip forming area, that is, in a scribe area for cutting a chip, or also serves as a predetermined pad of an adjacent chip, or a plurality of chips thereof are integrated into a tegu chip. At the same time, the metal wiring layer for connecting between the test pad and the internal integrated circuit of the corresponding chip is cut off after the test adjustment is completed, and the guard ring that is in the cut state for arranging this metal wiring layer is placed. By returning to the connected state in the mass production state, it is possible to suppress the increase in the chip area due to the provision of the test pad without lowering the reliability of the gate array integrated circuit or the like. (2) According to the above item (1), the cost of the gate array integrated circuit and the like can be reduced. (3) According to the above item (1), it is possible to solve the constraint of the number of pads that depends on the chip area, simplify the test adjustment processing of the gate array integrated circuit, etc., and improve the design efficiency of the test program etc. To be

The invention made by the present inventor has been specifically described above based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1 and FIG. 7, the shape of the wafer WAF is arbitrary, and the number of chips and TEGA chips formed on the surface of the wafer WAF can be set arbitrarily. In FIG. 2, the number and shape of the internal pads PAD provided in each chip are not restricted by this embodiment. Also, the test pad T
P1 and TP2 can be provided in the scribe region SZ on the lower side, left side, or right side of each chip, and four or more test pads can be provided in any scribe region SZ. 3 and 4, the internal pad PAD provided on each chip may include pads for various other purposes. The fuses F1 and F2 are, for example, MOSFs that can be selectively turned off after the test adjustment is completed.
It can be replaced with a switch means such as ET. Figure 8
In, the power supply voltage supply pad VCC and the ground potential supply pad VS provided in the TEG chips TEG1 to TEG6
S can be shared by a plurality of chips, and various embodiments can be adopted, such as the number of pads provided for these TEGA chips and their applications.

In the above description, the case where the invention made by the present inventor is mainly applied to the gate array integrated circuit which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to, for example, a digital / analog mixed integrated circuit such as a hard disk driver and various memory integrated circuits. The present invention can be widely applied to semiconductor devices that require at least a test pad.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a gate array integrated circuit, a digital / analog mixed integrated circuit, etc., a test pad for test adjustment is formed outside a corresponding chip forming region, that is, in a scribe region for cutting a chip, or a predetermined pad of an adjacent chip. Or a plurality of chips are integrated into a TEGG chip and the metal wiring layer provided between the test pad and the internal integrated circuit of the corresponding chip is cut after the test adjustment is completed. By returning the guard ring, which was in the disconnected state to arrange the wiring layer, to the connected state in the mass production state, the reliability of the gate array integrated circuit and the digital / analog mixed integrated circuit, etc. is not deteriorated, and the test pad The increase in the chip area due to the provision of the It is, solves the limitations of the number of pads coming from the chip area, the test adjustment process by simplifying, it is possible to improve the design efficiency of such a test program.

[Brief description of drawings]

FIG. 1 is a plan layout view showing an embodiment of a wafer on which a gate array integrated circuit to which the present invention is applied is formed.

2 is an enlarged layout view showing a first embodiment before testing a chip of a gate array integrated circuit formed on the wafer of FIG. 1. FIG.

FIG. 3 is a block diagram showing an embodiment before a test of the chip of the gate array integrated circuit of FIG.

FIG. 4 is a block diagram showing an embodiment after a test of the chip of the gate array integrated circuit of FIG.

5 is an enlarged layout view showing an embodiment in a mass production state of chips of the gate array integrated circuit of FIG.

6 is an enlarged layout view showing a second embodiment before testing a chip of a gate array integrated circuit formed on the wafer of FIG. 1. FIG.

FIG. 7 is a plan layout view showing another embodiment of a wafer on which a gate array integrated circuit to which the present invention is applied is formed.

8 is an enlarged layout view showing an embodiment of a chip and a tip chip of a gate array integrated circuit formed on the wafer of FIG.

[Explanation of symbols]

WAF ... wafer, CHP1 to CHP4 ... chip. LC: Internal integrated circuit, PAD, PADp, PA
Dq ... internal pad, TP1-TP2 ... test pad, GR ... guard ring, SZ ... scribe area. F1 to F2 ... Fuse, VCC ... Power supply voltage supply pad, VSS ... Ground potential supply pad, DI
1-DIm ... Data input pad, DO1-DOn
..Data output pads TEG1 to TEG6 ... Tegu chips.

Claims (6)

[Claims] 1. A semiconductor device, wherein a test pad for test adjustment is formed outside a formation region of a corresponding chip. 2. The semiconductor device according to claim 1, wherein the test pad is formed in a scribe region for cutting a chip. 3. The semiconductor device according to claim 1, wherein the test pad also serves as a predetermined pad of an adjacent chip. 4. The semiconductor device according to claim 1, wherein the test pad is formed by integrating a plurality of chips into a teg chip. 5. The test pad is coupled to an internal integrated circuit of a corresponding chip via a predetermined metal wiring layer, and the metal wiring layer is provided after the test adjustment of the corresponding chip is completed. The semiconductor device according to claim 1, wherein the semiconductor device is in a substantially cut state. 6. Each of the chips includes a guard ring formed along the outer periphery thereof, and the metal wiring layer is formed by cutting a part of the guard ring to form a corresponding chip forming region. To be extended out,
6. The semiconductor device according to claim 5, wherein the cut part of the guard ring is returned to the connected state in mass production of the chips.