KR100331262B1 - Connection state test circuit of BGA package - Google Patents

Abstract

The present invention provides a circuit for testing the connection state between the solder ball and the board of the uBGA package between the input pad and the buffer so that the connection state of the BGA package can be easily distinguished from defects due to poor connection and defects due to operation performance. A test circuit includes a plurality of transistors having a long channel length operated by a chip select signal (/ CS) by a drain connected between a plurality of input pads 10 and a plurality of input buffer input terminals and a source connected to ground. LTR, the output terminal 40 which receives the drain stage state values SPAD of the plurality of transistors LTR and the channel selection signal / CS and outputs a connection state between the solder balls and the board. By easily determining the connection status of the test, not only can the test time be shortened, but there is an advantage that it is easy to determine whether the connection is defective or not.

Description

BA package connection status test circuit

The present invention relates to a connection state test circuit of a BGA package, and more particularly, a circuit capable of testing a connection state between a solder ball and a board of a uBGA package is formed between an input pad and a buffer, so that defects and operations due to a poor connection can be obtained. The present invention relates to a connection test circuit of a BGA package that can easily identify a defect due to performance.

Since semiconductor devices have a big impact on reliability by each process element in the manufacturing stage, they are adjusted to form desired shapes, doping states, etc. through various experiments and inspections at each stage of the manufacturing process, but very minute errors in the manufacturing process Since each one can greatly affect the operation of the semiconductor device, the manufactured semiconductor device is inspected whether it is manufactured as designed through an inspection step using equipment for testing (probe station, tester, etc.).

After performing the wafer state test as described above, the package is actually used.

Electronic packaging technology is an organic connection between a semiconductor chip and a chip or between a chip and other peripheral components. An electronic packaging structure made using this technology provides power to the semiconductor chip from the outside. In addition, it transfers signals between components, wraps and protects semiconductor chips sensitive to external environmental changes, and also emits heat generated from the chips. As semiconductor technology advances and chips become denser and faster, existing packaging structures cannot satisfy performance. Accordingly, the development of a new packaging structure with improved characteristics and economics is required. As semiconductor technology develops today, electronic packaging technology, which appears to be a secondary technology of semiconductors, plays an important role in determining the performance and price of advanced electronic products.

Next-generation packaging technologies include flip chip technology, ball grid array (BGA) technology, and multi-chip module (MCM) technology. Of these, flip chip technology is the first step in connecting semiconductors to the outside. Is used.

BGA package uses solder ball as lead of chip to connect chip package and printed circuit board without using lead frame or pin. It is possible to micronize and multiply pitch, good electrical characteristics and very low defect rate of surface mount. There is an advantage.

As mentioned above, when the BGA package is connected to the sole ball and the board, the micro pitch and the pin can be reduced, so that the size of the sole ball becomes smaller, so that the contact reliability can be obtained while the soft contact is obtained during the test. Test the connection.

1 is a circuit diagram showing a connection state test circuit of a conventional BGA package.

As shown here, an input buffer 30 is formed at an input terminal to which the input pad 10 is connected, and an antistatic circuit 20 is provided to prevent static electricity flowing into the input terminal.

Therefore, in order to check the connection state between the solder ball and the board, when a negative current is applied to the input pad 10, the NMOS transistor in the antistatic circuit 20 is turned on, and a negative voltage, which is an NP junction voltage, is measured on the pad.

When the negative current is applied to the input pad 10 when normally connected as described above, it is determined to be normal when the negative voltage is measured at the input pad 10.

In this way, all the input pads 10 are tested to test the connection state or the measurement through the TDBI device, but there is a problem in that it is not possible to determine whether it is a bad due to a bad connection or a bad function.

The present invention was created to solve the above problems, and an object of the present invention is to connect a transistor with a long channel between the input buffer and the input pad and ground to test the connection state between the solder ball and the board of the uBGA package. In addition, the present invention provides a connection state test circuit of a BGA package, which is operated by a chip select signal to determine a connection state based on an input value of a buffer so that a failure due to a connection failure and a failure due to an operation performance can be easily distinguished.

1 is a circuit diagram showing a connection state test circuit of a conventional BGA package.

2 is a circuit diagram in which a connection state test circuit of a BGA package according to the present invention is installed on one input pad of a plurality of input pads.

3 is a circuit diagram showing an output unit of the BGA package connection state test circuit according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: input pad 20: electrostatic discharge circuit

30: input buffer 40: output

According to the present invention, a plurality of transistors having a long channel length operated by a chip select signal having a drain connected between a plurality of input pads and a plurality of input buffer input terminals and a source connected to ground, and a channel, An output unit receives the drain stage state values of the plurality of long transistors and the chip select signal and outputs a connection state.

The above output part is output by multiplying the inverted chip select signal by the drain terminal state values of a plurality of transistors having a long channel length. That is, the output becomes high when all signals are high potential, and the output becomes low potential when any signal has a low potential value.

Referring to the present invention made as described above is as follows.

Normally, when the BGA package is connected to the solder ball of the BGA package and the multiple input pads of the board, when the high potential and the chip select signal are activated on the multiple input pads, the drain terminal state values of the transistors having a long channel length have a high potential. As a large number of long transistors are turned on, the high potential is discharged to a low potential.

At this time, the drain stage state values applied to the output unit are operated by outputting a high potential value through an unused pad, which is logically multiplied with an inverted value of the active chip select signal.

However, if any of the defects in the connection state occurs, the drain stage state value becomes low potential, and the output value of the output section is operated to be output at low potential.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2 to 3 are circuit diagrams showing a connection state test circuit of a BGA package according to the present invention.

2 is a connection state test circuit installed in one input pad of a plurality of input pads 10.

As shown here, the chip select signal inverting the transistor LTR having a long channel length having a drain connected between the input pad 10 and the input buffer 30 and having a source connected to the ground by the first inverter INV1. The high potential is applied to the output terminal connected to the node A when the chip select signal / CS is activated, that is, the low potential is input and the high potential is input to the input pad 10. Thereafter, as the transistor LTR is gradually turned on over time, the high potential applied to the input pad 10 is converted to a low potential.

The test circuit shown in FIG. 2 is installed in each of the input pads, and the value of each node A and the chip select signal / CS output the connection state of the solder ball through the output unit 40 as shown in FIG. 3.

As shown here, the value of inverting the chip select signal / CS operates the first PMOS transistor P1 and the first NMOS transistor N1 and is operated by the value of node A according to the connection state of the solder balls. The second to nth NMOS transistors N2 to Nn are connected to the ground in series with the first NMOS transistor N1, so that the node B depends on the operation state of the chip select signal / CS and the second to nth NMOS transistors Nn. The value of is changed and this value is inverted and output through the second inverter INV2.

That is, in the standby state, the chip select signal / CS has a high potential and is inverted by the first inverter INV1 to turn on the first PMOS transistor P1 so that the node B becomes a high potential and this value is the second inverter. Output via (INV2). In this case, no matter what value the node A value SPAD has, that is, the node B value cannot be changed regardless of the on / off state of the second to nNMOS transistors N2 to Nn.

When the chip select signal / CS has a low potential in the precharged state as described above, this value is inverted by the first inverter INV1 so that the first PMOS transistor P1 is turned off and the first NMOS transistor N1 is turned off. Is turned on. When the second to nNMOS transistors N2 to Nn, which operate according to the value SPAD of the plurality of nodes A, which vary according to the connection state of the plurality of solder balls and the board, are turned on, the node B is discharged and stored. Since the potential becomes a potential, the value of the output unit output through the second inverter INV2 has a high potential value. Therefore, the connection state between the solder ball and the board will be informed that normal.

However, if any connection between the solder ball and the board is bad, the node A value SPAD does not have a high potential, so that any one of the second to nNMOS transistors N2 to Nn is turned off, so that the node B Does not discharge and remains in a high potential state, and is reversed through the second inverter INV2. Therefore, the output value of the output unit 40 becomes low potential, thereby informing that a defect has occurred in the connected state.

The output unit 40 according to the present invention outputs a low potential when any one of the inverted chip select signal (/ CS) value and the value of the node A has a low potential, and a high voltage when all signal values have a high potential. By performing the AND function that outputs the above, any circuit can be employed.

As described above, the present invention connects a transistor having a long channel between the input buffer and the input pad to ground and operates the chip selection signal to test the connection state between the solder ball and the board of the BGA package. By determining the connection state, it is possible to easily distinguish the defects caused by the poor connection and the defects caused by the operation performance, thereby reducing the test time and improving the productivity by reducing the test time.

Claims (2)

A plurality of transistors having a long channel length operated by a chip select signal by connecting a drain between a plurality of input pads and a plurality of input buffer input terminals and a source connected to ground; An output unit for receiving the drain terminal state values and the chip select signal of the plurality of transistors having a long channel length and outputs a connection state Connection state test circuit of the BGA package, characterized in that consisting of. The method of claim 1, wherein the output unit A connection state test circuit of a BGA package, characterized by outputting the result of inverting the chip selection signal and the drain terminal state values of a plurality of transistors having a long channel length.