JPH0668531B2 - Pulse width error detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A pulse width error detection circuit for detecting an abnormal pulse width of an interface signal, etc., which reliably detects an error even with an input pulse signal of a short pulse width that cannot be detected due to logic characteristics. With the aim of being able to do so, an input pulse signal having an indistinguishable pulse width is expanded by a pulse width expansion circuit to a pulse width that is less than the reference pulse width for error discrimination and identifiable, and this pulse width expansion signal is used in a gate circuit. Then, it is added to the input pulse signal and output to the pulse width error determination circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width error detection circuit for detecting an abnormal pulse width of an interface signal or the like.

For various interface signals in the computer system, if a correct signal is not transmitted, it may cause a hardware error. Therefore, an error detection circuit to detect whether the interface signal is normal is provided, and error detection output is provided. The cause of the hard error occurrence can be easily identified by the logging process of.

[Prior Art] FIG. 5 shows an example of a conventional error detection circuit.

In FIG. 5, option ports 22a, 22b, ...
.., 22n are the same printed circuit boards and can be added depending on the number of channels. On the other hand, the error discriminating circuit 14 is provided as a common port 24 for the option ports 22a to 22n on different printed circuit boards, and discriminates whether or not the interface signal is normal by dot-ORing the signals transmitted from the option ports 22a to 22n.

Two types of interface signals INT-1 and INT-2 are provided to the driver 26 and the option port 22a to 22n, respectively.
Input by 30. Option ports 22a-22
The output signal of n is an open collector signal and is suppressed by the gate signals to the AND gates 28 and 32, and the AND gates 28 and 32 of only a specific option port connected to the channel, for example, the option port 22a.
32 becomes a permissible state by the gate signal and the driver 2
The interface signals INT-1 and INT-2 from 6 and 30 are output to the error determination circuit 14 of the common port 24.

The error determination circuit 14 of the common port 24 can detect various errors, and one of them is to detect a pulse width error.

That is, the error discriminating circuit 14 uses the reference pulse width Tref (for example, Tref = 100n) as the discriminating reference of the pulse width error.
s) is preset, and the option ports 22a to
The pulse width Tn of the interface signal output from any one of 22n is compared with the reference pulse width, and when the pulse width is less than the reference pulse width Tref, a pulse width error detection output is generated.

[Problems to be Solved by the Invention] However, in such a conventional pulse width error detection circuit, if an interface signal of, for example, about 5 ns is given to an option port connected to a channel, it takes about 5 ns. In the case of a short pulse width, due to the characteristic of the logic of the option port, this interface signal of about 5 ns cannot be detected and output to the error determination circuit, and there is a problem that a pulse width error cannot be detected.

The present invention has been made in view of such a conventional problem, and is a pulse that is capable of surely detecting a pulse width error even with an input pulse signal of a short pulse width that cannot be detected due to logic characteristics. It is an object to provide a width error detection circuit.

[Means for Solving Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1, an input pulse signal a having a pulse width which cannot be discriminated, for example, a pulse width of about 5 ns is extended to a constant pulse width T2 which is equal to or less than a reference pulse width Tref (for example, Tref = 100 ns) for error discrimination and which can be discriminated. A pulse width expansion circuit 10, a gate circuit 12 for adding an output signal d of the pulse width expansion circuit 10 and an input pulse signal a, and a gate circuit 1.
The pulse width discriminating circuit 14 which discriminates that the output signal e of 2 is less than the reference pulse width Tref and produces an error detection output.
And are provided.

[Operation] Even if the interface signal has a short pulse width of about 5 ns, which is indistinguishable in terms of logic characteristics, it can be identified in terms of logic characteristics by the pulse width expansion circuit, for example, 2 to 3
It has a machine cycle pulse width and is expanded to a pulse width that is less than or equal to the reference pulse width for error determination, and is finally added to the input pulse signal and output to the error determination circuit. Moreover, even if the pulse width cannot be detected, the pulse width error can be detected with certainty.

[Embodiment] FIG. 2 is a configuration diagram of an embodiment showing one embodiment of the present invention.

In FIG. 2, 22a to 22n are option ports mounted on the same printed board according to the number of additional channels, 24 is a common port formed on another printed board, and the common port 24 has a pulse width determination circuit. 14 is provided.

The interface signal is input to each of the option ports 22a to 22n by the driver 26, and the output of the driver 26 is given to the pulse width expansion circuit 10.
The pulse width expansion circuit 10 is used for the error determination set in the pulse width determination circuit 14 when the interface signal from the driver 26 has a pulse width that cannot be identified due to the logic characteristics, for example, a pulse width of about 5 ns. It is expanded to a pulse width T2 which is equal to or less than the reference pulse width Tref and which can be identified by the logic characteristics, and is output.

The pulse width expansion circuit 10 is composed of a first differentiation circuit 16, a pulse width guarantee circuit 18, and a second differentiation circuit 20. The first differentiating circuit 16 outputs a differentiating signal synchronized with the rising edge of the interface signal from the driver 26. The pulse width assurance circuit 18 is triggered by the differential output from the first differentiating circuit 16 and generates a pulse signal having a constant pulse width T1 that exceeds the reference pulse width Tref set in the pulse width determining circuit 14. The second differentiating circuit 20 converts the guarantee signal from the pulse width guaranteeing circuit 18 into a pulse signal having a constant pulse width T2 which is equal to or less than the reference pulse width Tref set in the pulse width discriminating circuit 14 and which can be identified by the logic characteristics. .

The output of the pulse width expansion circuit 10 and the interface signal from the driver 26 are added by the OR gate 12 and are given to the pulse width determination circuit 14 of the common port 24 through the NAND gate 28 which is in an allowable state by the gate signal during the channel connection. There is.

FIG. 3 shows the option port 22 in the embodiment of FIG.
It is an Example block diagram which showed the specific Example of the pulse width expansion circuit 10 provided in a-22n.

In FIG. 3, the first differentiating circuit 16 to which the interface signal a from the driver 26 is input is
The inverter 36 and the NAND gate 38 form a digital differentiating circuit. That is, the delay circuit 34 delays the input pulse signal by a predetermined time and then inverts it by the inverter 36 and inputs it to one of the NAND gates 38 and NAN.
By directly inputting the input pulse signal to the other side of the D gate 38, a differential pulse signal b synchronized with the rising edge of the input pulse signal having a pulse width determined by the delay time of the delay circuit 34 is generated.

The differential signal b from the first differentiating circuit 16 is input to the pulse width guaranteeing circuit 18, and the pulse width guaranteeing circuit 18 uses the JK-FF.
40, 42 and 44 are vertically connected. 1st JK
-The first differentiating circuit 16 is connected to the preset terminal PS of the FF40.
Differential signal b is input, the J terminal is fixed to logic "0", and the K output of the third stage JK-FF44 is feedback-connected to the K terminal. The machine clock MC is applied to the clock terminals C of the JK-FFs 40, 42 and 44. Further, the Q output of the first-stage JK-FF40 is connected to the J terminal of the second-stage JK-FF42, and the output is connected to the K terminal, and the second-stage and third-stage JK-FF42 are connected. Similarly, 44 is connected.

With the configuration of the pulse width guarantee circuit 18 as described above, the first-stage JK-FF 40 set by the input of the preset terminal PS of the differential signal b is reset after the third-stage JK-FF 44 is set. Therefore, pulse width guarantee circuit 1
The Q output of the first stage JK-FF 40, which is the output of 8, outputs the pulse width guarantee signal c having the pulse width T1 corresponding to 2 to 3 of the machine clock MC.

The second differentiating circuit 20 to which the guarantee signal c of the pulse width guaranteeing circuit 18 is input is provided with a delay circuit 46, an inverter 48 and an AN.
It is composed of a D gate 50. That is, the pulse width guarantee signal c
Is delayed by the delay circuit 46 for T2, inverted by the inverter 48 and input to one of the AND gates 50, and the pulse width guarantee signal c is directly input to the other of the AND gates 50.
As a result, the AND gate 50 outputs the differential signal d having the pulse width of the delay time T2 of the delay circuit 46 in synchronization with the rise of the pulse width guarantee signal c. Here, the pulse width T2 of the differential signal d is equal to or smaller than the reference pulse width Tref that is distinguishable in terms of logic characteristics and used for error determination.

The output d of the second differentiating circuit 20 which is the final output of the pulse width expanding circuit 10 is added to the interface signal a output from the driver 26 via the first differentiating circuit 16 in the OR gate 12, and the channel is being connected. The signal is output to the error determination circuit 14 of the common port 24 through the NAND gate 28 which is placed in the allowable state by the gate signal.

Next, the operation of the embodiment of FIG. 3 will be described with reference to the signal waveform diagram of FIG.

Now, assuming that the interface signal a having a normal pulse width is input at the timing of time t1, the first differentiating circuit 16 generates the differentiating signal b in synchronization with the rise of the interface signal a, and the pulse width guaranteeing circuit. The 18th JK-FF 40 is preset, and the output of the pulse width guarantee signal c as its Q output is started. When the next machine clock MC is received, the first stage JK-FF40 in the preset state is set, the second stage machine clock MC sets the second stage JK-FF42, and the third stage machine clock is used. The third-stage JK-FF44 is set, and after the third-stage JK-FF44 is set, the first-stage JK-FF40 is reset, whereby the output of the pulse width guarantee signal c is stopped, and the second-stage JK-FF44 is reset. A pulse width guarantee signal c having a pulse width T1 corresponding to two to three machine clocks MC is output to the differentiating circuit 20.

The second differentiating circuit 20 which has received the pulse width guarantee signal c from the pulse width guarantee circuit 18 synchronizes with the rising edge of the pulse width guarantee signal c and has a fixed time T determined by the delay time of the delay circuit 46.
Generate a differential signal d with a pulse width of 2 and finally OR
The gate signal 12 is added to the interface signal a, and as a result, the port output signal e having the same pulse width as the normal interface signal a is output to the error determination circuit 14 via the NAND gate 28.

At this time, since the pulse width of the port output signal e is larger than the reference pulse width Tref for error determination, no error detection output is output.

On the other hand, the pulse width is abnormally short 5 at the timing of time t2.
If an interface signal a of about ns is input, the pulse width guarantee circuit 18 outputs a pulse width guarantee signal c having a pulse width T1 based on the differentiated signal d of the first differentiator circuit 16, and this pulse width guarantee Based on the signal c, the second differentiating circuit 20 outputs the differentiating signal d having the pulse width T2. The differential signal d from the second differentiating circuit 20 is added by the OR gate 12 with the interface signal a having a short pulse width of about 5 ns, and is output to the error discriminating circuit 14 via the NAND gate 28. Since the port output signal e at this time is smaller than the reference pulse width Tref for error determination, a pulse width error detection output is generated.

As described above, even an interface signal having a short pulse width that cannot be detected in terms of logic characteristics can be detected in terms of logic characteristics by pulse width expansion processing and a pulse width shorter than the reference pulse width Tref for error determination. It is possible to detect a pulse width error by converting the signal into a signal having and outputting it to the error discrimination circuit.

It should be noted that although the above embodiment has been described by taking the detection of the pulse width error of the interface signal input to the option port as an example, the present invention is not limited to this, and the pulse width error detection of an appropriate input pulse signal is performed. Therefore, it can be applied as it is.

[Effects of the Invention] As described above, according to the present invention, even a fine pulse that cannot be detected due to logic characteristics can be reliably detected as a pulse width error.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. 3 is a configuration diagram of a specific embodiment of the present invention; FIG. 5 is a configuration diagram of a conventional circuit. In the figure, 10: pulse width expansion circuit 12: gate circuit (OR gate) 14: pulse width determination circuit 16: first differentiating circuit 18: pulse width guarantee circuit 20: second differentiating circuit 22a to 22n: option port 24 : Common port 26: driver 28, 38: NAND gate 34, 46: delay circuit 36, 48: inverter 40, 42, 44: JK-FF 50: AND gate

Claims (2)

[Claims] 1. A pulse width expansion circuit (10) for expanding an input pulse signal (a) having an indistinguishable pulse width to a constant pulse width (T2) which is equal to or less than a reference pulse width (Tref) for error discrimination and which can be discriminated. A gate circuit (12) for adding an output signal (d) of the pulse width expansion circuit (10) and an input pulse signal (a); and an output signal (e) of the gate circuit (12) being the reference pulse. A pulse width error detection circuit comprising: a pulse width determination circuit (14) which determines that the width is less than or equal to the width (Tref) and produces an error detection output. 2. The pulse width expansion circuit (10) comprises a differential signal (b) synchronized with the rising edge of the input pulse signal (a).
Of the reference pulse width (T) triggered by the output of the first differentiating circuit (16)
Guaranteed signal (c) with constant pulse width (T1) exceeding ref)
And a guarantee signal (c) of the pulse width guarantee circuit (18) for generating a pulse width guarantee circuit (18) that is less than or equal to the reference pulse width (Tref) and is identifiable constant pulse width (T2).
The second differentiating circuit (2
0) and the pulse width error detection circuit according to claim 1.