JPH0667207A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH0667207A JPH0667207A JP22166792A JP22166792A JPH0667207A JP H0667207 A JPH0667207 A JP H0667207A JP 22166792 A JP22166792 A JP 22166792A JP 22166792 A JP22166792 A JP 22166792A JP H0667207 A JPH0667207 A JP H0667207A
- Authority
- JP
- Japan
- Prior art keywords
- additional capacitance
- pixel
- pixel additional
- tft
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ビデオカメラ用のビュ
ーファインダーやビデオプロジェクターなどに用いられ
るアクティブマトリクス方式液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device used for a viewfinder or a video projector for a video camera.
【０００２】[0002]
【従来の技術】代表的なフラットパネル型ディスプレイ
である液晶表示装置は、共通電極が形成された一方側の
透明基板と、多数の画素領域を備えるマトリクスアレイ
が形成された他方側の透明基板との間に液晶が封入され
ており、共通電極と各画素領域の画素電極との間に印加
される電位を制御して、画素領域毎の液晶の配向状態を
変えるようになっている。その代表的なものが薄膜トラ
ンジスタ（以下、ＴＦＴと略す。）を利用して、所定の
信号電位を各画素電極に印加する方式であり、そのマト
リクスアレイの等価回路は、たとえば、図６に示すよう
に表される。2. Description of the Related Art A typical flat panel type liquid crystal display device includes a transparent substrate on one side on which a common electrode is formed and a transparent substrate on the other side on which a matrix array having a large number of pixel regions is formed. A liquid crystal is sealed between the two, and the electric potential applied between the common electrode and the pixel electrode of each pixel region is controlled to change the alignment state of the liquid crystal for each pixel region. A typical example thereof is a method of applying a predetermined signal potential to each pixel electrode using a thin film transistor (hereinafter, abbreviated as TFT), and an equivalent circuit of the matrix array is, for example, as shown in FIG. Represented by.
【０００３】このような構成の液晶表示装置に対して
は、表示の高精細化の要求があり、この要求に対応する
ために、各画素領域を微細化する傾向にある。そのため
に、画素領域における液晶容量１３が減少し、オフ抵抗
の高いＴＦＴ１０を構成してリーク電流を小さくして
も、表示電圧が低下し、表示の保持特性が低くなりやす
い傾向がある。そこで、画素付加容量１を液晶容量１３
と並列に接続することにより、表示電圧の保持特性を向
上することが行われる。画素付加容量１は、たとえば、
図４（図５のＩ−Ｉ断面）および図５に示すように、Ｔ
ＦＴ１０のドレイン９に導通接続される下電極２と、誘
電体膜１５と、前段のゲート線６ａに導通接続される上
電極３と、により構成される。ゲート線６ｂが非選択期
間時には、前段のゲート線６ａも、ほとんどの時間が非
選択期間であり、基準電位が印加されている。このこと
を利用して、画素付加容量１に電荷を蓄積し、画素領域
の液晶印加電圧の保持特性を向上させている。For the liquid crystal display device having such a structure, there is a demand for higher definition of display, and in order to meet this demand, each pixel region tends to be miniaturized. Therefore, the liquid crystal capacitance 13 in the pixel region decreases, and even if the TFT 10 having high off resistance is configured to reduce the leak current, the display voltage tends to decrease, and the display retention characteristics tend to deteriorate. Therefore, the pixel additional capacitance 1 is replaced with the liquid crystal capacitance 13
The display voltage holding characteristic is improved by connecting in parallel with. The pixel additional capacitance 1 is, for example,
As shown in FIG. 4 (I-I cross section of FIG. 5) and FIG.
It is composed of a lower electrode 2 that is conductively connected to the drain 9 of the FT 10, a dielectric film 15, and an upper electrode 3 that is conductively connected to the gate line 6a in the preceding stage. When the gate line 6b is in the non-selection period, most of the gate line 6a in the preceding stage is also in the non-selection period, and the reference potential is applied. By utilizing this fact, charges are accumulated in the pixel additional capacitance 1 to improve the holding characteristic of the liquid crystal applied voltage in the pixel region.
【０００４】微細化が進むのにつれて液晶容量１３は更
に減少するので、十分な保持特性を得るために必要とさ
れる画素付加容量１は増加する。電荷蓄積容量は、誘電
体膜の膜厚と誘電率および電極の重なり面積で決定され
る。画素付加容量１の誘電体膜１５は、通常、ＴＦＴ１
０のゲート絶縁膜１１と同時に形成されるので、膜厚や
誘電率を自由に設定することはできない。そのため、画
素付加容量１を増加させるためには面積を拡大する必要
があるが、画素付加容量を形成した領域は透明でないた
めに開口率（表示可能な画素領域）の低下につながる。
開口率は最低限２５％必要とされるため、画素付加容量
の面積を犠牲にすることになり、十分な保持特性を得ら
れない。そのため、画面のムラやちらつきが発生して表
示品質が低い。As the miniaturization progresses, the liquid crystal capacitance 13 further decreases, so that the pixel additional capacitance 1 required to obtain sufficient holding characteristics increases. The charge storage capacity is determined by the film thickness and dielectric constant of the dielectric film and the overlapping area of the electrodes. The dielectric film 15 of the pixel additional capacitance 1 is usually the TFT 1
Since it is formed at the same time as the gate insulating film 11 of 0, the film thickness and dielectric constant cannot be freely set. Therefore, although it is necessary to increase the area in order to increase the pixel additional capacitance 1, the area where the pixel additional capacitance is formed is not transparent, which leads to a reduction in the aperture ratio (displayable pixel region).
Since the aperture ratio is required to be at least 25%, the area of the pixel additional capacitance is sacrificed and a sufficient holding characteristic cannot be obtained. Therefore, display unevenness and flicker occur and display quality is low.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術では、画
素領域の微細化にともなって、表示品質が低下するとい
う課題がある。The above-mentioned conventional technique has a problem that the display quality is deteriorated as the pixel area is miniaturized.
【０００６】[0006]
【課題を解決するための手段】そこで、本発明の液晶表
示装置は、上記課題を解決するものであって、アクティ
ブマトリクス方式液晶表示装置において、画素付加容量
が基板の垂直方向に形成された溝内に形成されているこ
とを特徴とする。Therefore, a liquid crystal display device of the present invention is to solve the above-mentioned problems. In the active matrix liquid crystal display device, a pixel additional capacitance is formed in a groove formed in the vertical direction of the substrate. It is characterized in that it is formed inside.
【０００７】[0007]
【実施例】次に本発明の一実施例について添付図面を参
照して説明する。本発明の実施例の液晶表示装置におけ
るＴＦＴ１０と画素付加容量１の断面図を図１（図２の
Ｉ−Ｉ断面）に、平面図を図２に示す。長方形の溝内に
画素付加容量１が形成されている場合を示しているが、
溝の形状や数には制限がなく、円形や三角形の穴が多数
個並んだところに画素付加容量を形成しても良い。ま
た、図２においては、画素付加容量１がＴＦＴ１０のド
レインに導通接続される下電極２と、誘電体膜１５と、
前段のゲート線６ａに導通接続される上電極３から構成
される場合を示しているが、図３に示すように、上電極
３がゲート線６ｂと平行に作り込まれた容量線１４に導
通接続する場合も挙げられる。An embodiment of the present invention will now be described with reference to the accompanying drawings. A cross-sectional view of the TFT 10 and the pixel additional capacitance 1 in the liquid crystal display device of the embodiment of the present invention is shown in FIG. 1 (I-I cross section in FIG. 2), and a plan view is shown in FIG. The case where the pixel additional capacitance 1 is formed in the rectangular groove is shown.
The shape and number of the grooves are not limited, and the pixel additional capacitance may be formed where a large number of circular or triangular holes are arranged. Further, in FIG. 2, the pixel additional capacitance 1 is conductively connected to the drain of the TFT 10, the lower electrode 2, the dielectric film 15, and
Although a case is shown in which the upper electrode 3 is conductively connected to the gate line 6a at the previous stage, the upper electrode 3 is electrically connected to the capacitance line 14 formed in parallel with the gate line 6b as shown in FIG. An example is when connecting.
【０００８】溝の形成方法には、以下の方法が挙げられ
る。透明基板を直接エッチングして、目的とする溝を
形成する。酸化シリコン膜をＣＶＤ法により堆積し
て、目的とする溝にパターニングする。透明基板上に
堆積された多結晶シリコン膜または非晶質シリコン膜
を、目的とする溝の形状に合わせてパターニングした
後、膜をすべて酸化して酸化シリコンとする。多結晶シ
リコン膜を酸化する場合、形成される酸化シリコンは約
２．２倍の厚さとなるため、予め酸化後の溝の深さを予
測して多結晶シリコン膜を成膜しておく必要がある。通
常、酸化方法には、ドライ酸化とウエット酸化の二通り
があるが、ここでは酸化速度が大きなウエット酸化を用
いるほうがよい。窒化シリコン膜をＣＶＤ法により堆
積して、目的とする溝にパターニングする。酸化シリコ
ンを形成するよりも簡便である。The method of forming the groove includes the following methods. The transparent substrate is directly etched to form the target groove. A silicon oxide film is deposited by the CVD method and patterned into a target groove. The polycrystalline silicon film or the amorphous silicon film deposited on the transparent substrate is patterned according to the shape of the target groove, and then the entire film is oxidized to form silicon oxide. When oxidizing the polycrystalline silicon film, the thickness of the silicon oxide formed is about 2.2 times, so it is necessary to predict the depth of the groove after the oxidation to form the polycrystalline silicon film in advance. is there. Generally, there are two kinds of oxidation methods, dry oxidation and wet oxidation. Here, it is preferable to use wet oxidation, which has a high oxidation rate. A silicon nitride film is deposited by the CVD method and patterned into a target groove. It is easier than forming silicon oxide.
【０００９】これ以降の工程は、通常の多結晶シリコン
ＴＦＴを用いた液晶表示装置の作製方法と同様である。
減圧ＣＶＤ法により、ＴＦＴのチャネル領域およびソー
ス７、ドレイン９を形成する膜厚５００〜２０００Åの
多結晶シリコン膜が成膜される。多結晶シリコンをパタ
ーニング後、その上に酸化シリコンまたは窒化シリコン
からなるゲート絶縁膜１１および画素付加容量の誘電体
膜１５が５００〜２０００Å形成される。ゲート絶縁膜
１１としては、高温熱酸化による酸化シリコンが最も信
頼性の高い膜である。通常は、工程の簡便化のためにゲ
ート絶縁膜１１と誘電体膜１５は同時に成膜されるが、
画素付加容量を特に大きくする必要があるときには誘電
体膜１５のみを選択的に薄膜化する。ＴＦＴ１０のドレ
イン９の端部により形成される下電極２には、ｎ型の不
純物としてイオン注入により選択的にリンが導入されて
いる。不純物がドープされた多結晶シリコンを堆積し
て、画素付加容量１の上電極２およびＴＦＴ１０のゲー
ト８を１５００〜５０００Å形成する。多結晶シリコン
の代わりに、ＭｏＳｉx やＷＳｉx 等の低抵抗材料を用
いるとゲート信号の遅延にともなう表示異常の低減に効
果がある。ＴＦＴ１０には、真性の多結晶シリコンであ
るチャネル領域を除いて、ｎ型の不純物としてリン（ｐ
型を形成する場合はボロン）が導入されている。ここで
リンの導入は、ゲート８をマスクとするイオン注入を利
用することにより、ソース７およびドレイン９が自己整
合的に形成されている。この画素付加容量１とＴＦＴ１
０の上方には、層間絶縁膜として３０００〜１５０００
Åの酸化シリコン膜があり、この膜の焼き締めとリンな
どの不純物の活性化のために８００〜１０００℃という
高温でのアニールが行われている。ＴＦＴ１０のソース
７とドレイン９には、それぞれ、アルミニウムなどの金
属膜からなるソース線５ａとＩＴＯなどの透明電導膜か
らなる画素電極４が導通接続されている。この上に、耐
湿保護膜（図示せず）を成膜してＴＦＴの基板工程が終
了する。Subsequent steps are the same as in the method of manufacturing a liquid crystal display device using a normal polycrystalline silicon TFT.
By the low pressure CVD method, a polycrystalline silicon film having a film thickness of 500 to 2000 Å which forms the channel region of the TFT, the source 7 and the drain 9 is formed. After patterning the polycrystalline silicon, the gate insulating film 11 made of silicon oxide or silicon nitride and the dielectric film 15 of the pixel additional capacitance are formed thereon in a thickness of 500 to 2000Å. As the gate insulating film 11, silicon oxide by high temperature thermal oxidation is the most reliable film. Normally, the gate insulating film 11 and the dielectric film 15 are formed at the same time to simplify the process.
When it is necessary to particularly increase the pixel additional capacitance, only the dielectric film 15 is selectively thinned. To the lower electrode 2 formed by the end of the drain 9 of the TFT 10, phosphorus is selectively introduced as an n-type impurity by ion implantation. Polycrystalline silicon doped with impurities is deposited to form the upper electrode 2 of the pixel additional capacitor 1 and the gate 8 of the TFT 10 in the range of 1500 to 5000Å. If a low resistance material such as MoSi x or WSi x is used instead of polycrystalline silicon, it is effective in reducing display anomalies due to the delay of the gate signal. Except for the channel region which is intrinsic polycrystalline silicon, the TFT 10 has phosphorus (p) as an n-type impurity.
Boron is introduced when forming a mold. Here, phosphorus is introduced by utilizing ion implantation using the gate 8 as a mask, so that the source 7 and the drain 9 are formed in a self-aligned manner. This pixel additional capacitance 1 and TFT1
Above 0, as an interlayer insulating film, 3000 to 15000
There is a silicon oxide film of Å, and annealing is performed at a high temperature of 800 to 1000 ° C. for baking the film and activating impurities such as phosphorus. A source line 5a made of a metal film such as aluminum and a pixel electrode 4 made of a transparent conductive film such as ITO are electrically connected to the source 7 and the drain 9 of the TFT 10, respectively. A moisture resistant protective film (not shown) is formed on this, and the substrate process of the TFT is completed.
【００１０】以上のようにして、画素付加容量を溝内に
形成することにより、同じ占有面積で、より大きな容量
を得ることができる。たとえば、従来のような平坦な基
板上に長方形の画素付加容量が形成されている場合、縦
３０μｍ、横２０μｍであるとすると、その占有面積は
６００μｍ2 である。そこに、縦２０μｍ、横５μｍ、
深さ２μｍの長方形の溝を２つ形成すると、溝の側壁の
面積２００μｍ2 だけ表面積が増加する。つまり、従来
と同じ占有面積で容量を１／３増加させることができ
る。表示電圧の保持特性が低い場合には、画面のムラや
ちらつきが発生するという問題があるが、本発明によれ
ば、画素付加容量の占有面積を一定に保ちながら、保持
特性を向上することができる。また、逆に、保持特性が
十分に大きな場合には、保持特性を一定に保ちながら占
有面積を低下させて開口率を高くし、画面の明るさを増
すこともできる。By forming the pixel additional capacitance in the groove as described above, a larger capacitance can be obtained with the same occupied area. For example, in the case where a rectangular pixel additional capacitor is formed on a flat substrate as in the conventional case, if the vertical length is 30 μm and the horizontal length is 20 μm, the occupied area is 600 μm 2 . There, vertical 20μm, horizontal 5μm,
When two rectangular grooves having a depth of 2 μm are formed, the surface area is increased by 200 μm 2 of the side wall area of the groove. That is, it is possible to increase the capacity by 1/3 with the same occupied area as the conventional one. When the holding characteristic of the display voltage is low, there is a problem that screen unevenness and flicker occur. However, according to the present invention, it is possible to improve the holding characteristic while keeping the area occupied by the pixel additional capacitance constant. it can. On the contrary, when the holding property is sufficiently large, the occupied area can be reduced to increase the aperture ratio and the screen brightness can be increased while keeping the holding property constant.
【００１１】[0011]
【発明の効果】以上のとおり、本発明の液晶表示装置に
おいては、下記のような効果がある。 画素付加容量の占有面積を一定に保ちながら、表示電
圧の保持特性を向上させることができる。As described above, the liquid crystal display device of the present invention has the following effects. It is possible to improve the holding characteristic of the display voltage while keeping the area occupied by the pixel additional capacitance constant.
【００１２】表示電圧の保持特性を一定に保ちなが
ら、画素付加容量の占有面積を低下させることにより、
開口率を向上させることができる。By keeping the display voltage holding characteristic constant and reducing the area occupied by the pixel additional capacitance,
The aperture ratio can be improved.
【００１３】これらの効果により、画面の表示品質の向
上が得られる。Due to these effects, the display quality of the screen can be improved.
【図１】本発明の実施例による液晶表示装置のＴＦＴと
画素付加容量の断面図。（図２のＩ−Ｉ断面）FIG. 1 is a cross-sectional view of a TFT and a pixel additional capacitance of a liquid crystal display device according to an embodiment of the present invention. (I-I cross section of FIG. 2)
【図２】本発明の実施例による画素領域の平面図。FIG. 2 is a plan view of a pixel area according to an embodiment of the present invention.
【図３】本発明の実施例による画素領域の平面図。FIG. 3 is a plan view of a pixel area according to an exemplary embodiment of the present invention.
【図４】従来の液晶表示装置のＴＦＴと画素付加容量の
断面図。（図５のＩ−Ｉ断面）FIG. 4 is a cross-sectional view of a TFT and a pixel additional capacitance of a conventional liquid crystal display device. (I-I cross section of FIG. 5)
【図５】従来の画素領域の平面図。FIG. 5 is a plan view of a conventional pixel area.
【図６】液晶表示装置のマトリクスアレイの等価回路
図。FIG. 6 is an equivalent circuit diagram of a matrix array of a liquid crystal display device.
１・・・画素付加容量 ２・・・下電極 ３・・・上電極 ４・・・画素電極 ５ａ、５ｂ・・・ソース線 ６ａ、６ｂ・・・ゲート線 ７・・・ソース ８・・・ゲート ９・・・ドレイン １０・・・ＴＦＴ １１・・・ゲート絶縁膜 １２・・・層間絶縁膜 １３・・・液晶容量 １４・・・容量線 １５・・・誘電体膜 1 ... Pixel additional capacitance 2 ... Lower electrode 3 ... Upper electrode 4 ... Pixel electrode 5a, 5b ... Source line 6a, 6b ... Gate line 7 ... Source 8 ... Gate 9 ... Drain 10 ... TFT 11 ... Gate insulating film 12 ... Interlayer insulating film 13 ... Liquid crystal capacitance 14 ... Capacitance line 15 ... Dielectric film
Claims (1)
において、画素電極を駆動する薄膜トランジスタのドレ
イン電極に接続された画素付加容量が基板に対して垂直
方向に形成された溝内に形成されていることを特徴とす
る液晶表示装置。1. In an active matrix type liquid crystal display device, a pixel additional capacitance connected to a drain electrode of a thin film transistor driving a pixel electrode is formed in a groove formed in a direction vertical to a substrate. Liquid crystal display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22166792A JPH0667207A (en) | 1992-08-20 | 1992-08-20 | Liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22166792A JPH0667207A (en) | 1992-08-20 | 1992-08-20 | Liquid crystal display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0667207A true JPH0667207A (en) | 1994-03-11 |
Family
ID=16770383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22166792A Pending JPH0667207A (en) | 1992-08-20 | 1992-08-20 | Liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0667207A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999028784A1 (en) * | 1997-11-28 | 1999-06-10 | Matsushita Electric Industrial Co., Ltd. | Reflection-type display device and image device using reflection-type display device |
| US5971782A (en) * | 1996-08-26 | 1999-10-26 | Yazaki Corporation | Connector with a steering angle sensor and column structure using the same |
| JP2000081636A (en) * | 1998-09-03 | 2000-03-21 | Seiko Epson Corp | Electrooptical device and its manufacture and electronic instrument |
| KR20010048437A (en) * | 1999-11-26 | 2001-06-15 | 박종섭 | Silicon Light Valve |
| NL1012470C2 (en) * | 1998-07-24 | 2005-02-07 | Nec Lcd Technologies | Liquid crystal display device of the active matrix type. |
| KR100487392B1 (en) * | 1999-07-02 | 2005-05-03 | 샤프 가부시키가이샤 | Liquid crystal display device and method for fabricating the same |
| JP2007311741A (en) * | 2006-05-15 | 2007-11-29 | Lg Philips Lcd Co Ltd | Thin film transistor and its manufacturing method as well as display substrate |
| JP2011061212A (en) * | 2006-05-15 | 2011-03-24 | Lg Display Co Ltd | Thin film transistor, method of manufacturing the same, and display substrate |
| CN105529334A (en) * | 2014-10-16 | 2016-04-27 | 三星显示有限公司 | Thin film transistor array substrate, method of manufacturing the same, and organic light-emitting diode (oled) display including the same |
| JP2021067766A (en) * | 2019-10-21 | 2021-04-30 | セイコーエプソン株式会社 | Electro-optic device and electronic apparatus |
-
1992
- 1992-08-20 JP JP22166792A patent/JPH0667207A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5971782A (en) * | 1996-08-26 | 1999-10-26 | Yazaki Corporation | Connector with a steering angle sensor and column structure using the same |
| WO1999028784A1 (en) * | 1997-11-28 | 1999-06-10 | Matsushita Electric Industrial Co., Ltd. | Reflection-type display device and image device using reflection-type display device |
| NL1012470C2 (en) * | 1998-07-24 | 2005-02-07 | Nec Lcd Technologies | Liquid crystal display device of the active matrix type. |
| JP2000081636A (en) * | 1998-09-03 | 2000-03-21 | Seiko Epson Corp | Electrooptical device and its manufacture and electronic instrument |
| KR100487392B1 (en) * | 1999-07-02 | 2005-05-03 | 샤프 가부시키가이샤 | Liquid crystal display device and method for fabricating the same |
| KR20010048437A (en) * | 1999-11-26 | 2001-06-15 | 박종섭 | Silicon Light Valve |
| JP2007311741A (en) * | 2006-05-15 | 2007-11-29 | Lg Philips Lcd Co Ltd | Thin film transistor and its manufacturing method as well as display substrate |
| JP2011061212A (en) * | 2006-05-15 | 2011-03-24 | Lg Display Co Ltd | Thin film transistor, method of manufacturing the same, and display substrate |
| JP4713433B2 (en) * | 2006-05-15 | 2011-06-29 | エルジー ディスプレイ カンパニー リミテッド | Thin film transistor |
| US8927995B2 (en) | 2006-05-15 | 2015-01-06 | Lg Display Co., Ltd. | Thin film transistor with anti-diffusion area that prevents metal atoms and/or ions from source/drain electrodes from shortening the channel length and display substrate having the thin film transistor |
| CN105529334A (en) * | 2014-10-16 | 2016-04-27 | 三星显示有限公司 | Thin film transistor array substrate, method of manufacturing the same, and organic light-emitting diode (oled) display including the same |
| CN105529334B (en) * | 2014-10-16 | 2021-03-16 | 三星显示有限公司 | Thin film transistor array substrate, method of manufacturing the same, and organic light emitting display device |
| JP2021067766A (en) * | 2019-10-21 | 2021-04-30 | セイコーエプソン株式会社 | Electro-optic device and electronic apparatus |
| US11598997B2 (en) | 2019-10-21 | 2023-03-07 | Seiko Epson Corporation | Electro-optical device and electronic apparatus |
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