JPH0666802B2 - Repeater Chietuka for multiplex transmission - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a repeater checker for multiplex transmission.

[Background technology]

In a general multiplex transmission control system, as shown in FIG. 1, one receiver RC and, for example, eight relays (each assigned an address of 1 to 8) TC ₁ to.
And TC ₈ contact with the transmission line L, and relay _TC 1 to Tc ₈
A load (not shown) is connected to each.

The receiver RC controls the terminal device via the relays TC _{1 to} TC ₈ and monitors the control state of the terminal device. Specifically repeater terminal unit receiver RC can be controlled is connected to, for example, sends a control data of the address data 1 and the terminal device TC ₁ to the transmission line L. Each of the repeaters TC _{1 to} TC ₈ is adapted to take in the address data and the control data sent out to the transmission line L, compare the taken-in address data with its own address data, and when they match ( The terminal device is controlled based on the control data taken in when its own address is designated). In this case, since the address data is 1, the repeater TC ₁ switches the control state of the terminal device based on the control data, and the other repeater T 1
C _{1 to} TC ₈ do not switch control states.

Also, at this time, the repeater TC with its own address specified
₁ sends the monitoring data to the transmission line L at the same timing as the control data is taken in, and the receiver RC is
This control data is taken in at the same timing as the control data is sent, and the control status of the terminal is monitored. This monitoring data is for the control data sent immediately before.

Usually, the multiplex transmission control system, the two-cycle operation of the previous control cycle and after the monitoring cycle, the control cycle sends each control data to the relay TC ₁ to Tc ₈ addresses 1-8, monitoring Address 1 to 1 in cycle
The monitoring data of the _eight relays TC _{1 to} TC ₈ is taken in, the monitoring data is not taken in the control cycle, and the control data is not sent in the monitoring cycle.

A repeater used in such a multiplex transmission control system is configured as shown in FIG. This repeater is of the three-control, three-monitor type, and is connected to the receiver RC by six transmission lines L _{1 to} L ₆ . The six internal divisions are the power supply line L ₁ and GND that supply the power supply voltage + 12V.
(Ground) line _{L 2,} the transmission signal (address data + control data) transmission signal line _{L 3} to send the DP, the reply signal (monitor data) return signal line _{L 4} Send RD, sub synchronization signal to send a sub-synchronous signal CP ₁ A line L ₅ and a main synchronization signal line L ₆ for transmitting the main synchronization signal CP ₂ . The sub sync signal CP ₁ , the main sync signal CP ₂ , the transmission signal DP and the reply signal RD are transmitted at the timings shown in FIG.
The main synchronization signal CP _2, the period 1 KHz, are fed from the constant reception unit RC high level (power supply voltage) time 0.3 msec. The sub synchronization signal CP ₁ is transmitted with the same pulse as the main synchronization signal CP ₂ with a phase advance of 180 degrees, and thus the main synchronization signal CP ₂ is transmitted.
Are transmitted corresponding to the first to twelfth pulses, respectively, and the four pulses of the cycle corresponding to the thirteenth to sixteenth pulses of FIG. The units TC _{1 to} TC ₈ are adapted to detect start information for signal transmission / reception.
The transmission signal DP includes address data from the first bit to the eighth bit and control data from the ninth bit to the twelfth bit, and these data are the main synchronization signal CP ₂
Are sequentially sent at the same timing as the first to twelfth pulses. Reply signal RD is sent at the same timing as the pulse from the ninth main synchronization signal CP ₂ to the 12th.

This repeater is configured to supply power to each circuit section by the power supply circuit E ₁ . Then, the main synchronization signal CP ₂ (FIG. 4 (B)) and the sub synchronization signal CP ₁ sent from the receiver RC.
Based on (FIG. 4 (A)), the timing generation circuit TA ₁
Generates various timing pulses.

The timing generation circuit TA ₁ generates a read signal A ₃ (FIG. 4 (D)) composed of 12 pulses at the same timing as the first to twelfth pulses of the main synchronization signal CP ₂ . This read signal A ₃ is applied to the clock input terminal CK of the shift register SR ₁ . As a result, the shift register SR ₁ reads the transmission signal DP (address data + control data: FIG. 4 (C)) sent from the receiver RC while sequentially shifting.

While the shift register SR ₁ is reading the transmission signal DP by the read signal A ₃ (FIG. 5 (A)),
Specifically, read signal as _{A 3} outputs eight pulses, the transmission signal 8-bit address data of the DP is read into the shift register SR _1, the shift register SR ₁ of the output terminal _Q 1 to Q ₈ From the address data output in parallel, that is, the main synchronization signal C
At the same timing as the pulse of the sub-synchronization signal CP ₁ between the 8th and 9th pulses of P ₂ , the timing generation circuit TA ₁ outputs the address coincidence timing determination signal A ₄ (fifth).
(B) is generated and sent to the address coincidence detection circuit AD ₁ .

The address match detection circuit AD ₁ receives the address match timing determination signal A _{4 and} outputs the address data output from the output terminals Q _{1 to} Q ₈ of the shift register SR ₁ and the self address set by the eight address setting switch groups SW ₁ . An address match signal is generated at the output terminal Q when both addresses match, and this is applied to the output circuit DR.

Even after the address match signal is generated, the shift register SR ₁ continues to read the transmission signal DP, and the main synchronization signal C
The timing generation circuit TA ₁ outputs the output timing pulses A ₆ , A ₇ , and A ₈ at the same timing as the ninth to twelfth pulses of P ₂ (FIGS. 5 (F), (G), and (H)).
Are generated respectively and are added to the output circuit DR.

The output circuit DR outputs the output terminals Q _{1 to} Q ₃ of the shift register SR ₁ when the output timing pulses A ₆ , A ₇ , and A ₈ are applied in the state where the address match signal is input.
Is output from the output from the output _Q 1 to Q ₃ the control data input to the data input terminal _D 1 to D _3, the delay circuit DL
It controls the relay _RY 1 to Ry ₃ through ₁ through DL _3.

In addition, the timing generation circuit TA ₁ uses the main synchronization signal CP ₂
Sub-sync signal C between the 12th and 13th pulses of
A reset signal A ₅ (FIG. 5 (E)) is generated at the same timing as the pulse of P ₁ , and the reset signal A ₅ (FIG. 5 (E)) is generated.
Add to D ₁ . Accordingly, the address match detection circuit AD
₁ stops the output of the address match signal.

In addition, the timing generation circuit TA ₁ uses the main synchronization signal CP ₂
Sub-sync signal CP ₁ between the 8th and 9th pulses of
Read signal A ₂ which rises at the same timing as the pulse of
(FIG. 5 (D)) is generated and added to the shift register SR ₂ . The shift register SR ₂ reads the 3-bit monitoring data applied to the input terminals P _{1 to} P ₄ . This monitoring data is input via the photocouplers PC _{1 to} PC ₃ .

After this, the timing generation circuit TA ₁ outputs the main synchronization signal CP.
_The sending timing signal A ₁ (FIG. 5 (C)) is generated at the same timing as the 9th to 12th pulses of No. ₂ and the monitoring data is sequentially shifted and sent as the reply signal RD from the output terminal Q.

The reply signal RD is transmitted only when an address is designated and is not shown in the circuit diagram. However, for example, the monitor data may be generated only when the address match signal is output. Alternatively, it can be realized by generating the sending-out timing signal A ₁ only when the address coincidence signal is generated.

The address coincidence detection circuit AD ₁ is specifically realized by a circuit as shown in FIG. In FIG. 6, the exclusive OR circuits EX _{1 to} EX ₈ and the AND circuit AN ₁ have address data (D _{1 to} D ₈ ) and self addresses (D ₁ ′ to
D ₈ ′) are individually compared, and when all match, the output of the AND circuit AN ₁ becomes high level, and the output of the AND circuit AN ₁ is output to the D flip-flop FF ₁ by the address match determination timing signal A ₄ In response to the reset signal A _{5 and the} D flip-flop FF ₁
Will be reset.

The output circuit DR is specifically realized by a circuit as shown in FIG. In FIG. 7, AND circuits AN _{2 to} AN.
₄ is opened when an address coincidence signal is output to pass control data (D _{1 to} D ₃ ) and AND circuits AN _{5 to} AN.
₇ is opened when the output timing pulses A ₆ , A ₇ , and A ₈ are output to allow the control data (D _{1 to} D ₃ ) to pass therethrough.

Such a multiplex transmission control system is constructed on-site, but during the construction, wiring of trunk lines such as signal lines and power lines and wiring to sensors, dampers, etc. connected to repeaters are performed correctly. There is a possibility that there will be two cases, that is, a trouble with the repeater may occur and a trouble due to a defect in the repeater itself may occur.

For such troubles, there has been a demand for a checker capable of individually checking the repeaters in order to quickly determine the cause and deal with the troubles.

[Object of the Invention]

An object of the present invention is to provide a repeater checker for multiplex transmission, which can check the repeaters individually.

[Disclosure of Invention]

A repeater checker for multiplex transmission according to the present invention includes a power supply voltage,
The main synchronization signal composed of periodic pulses and a phase advance of 180 degrees from the main synchronization signal generate a pulse for a period corresponding to the number of bits of the address data and control data, and stop the pulse generation for a fixed number of subsequent periods. A sub-synchronization signal and a transmission signal composed of the address data and control data are sent from the receiver, and when the address data and the self-address match, the terminal device is controlled according to the control data, and the terminal device A repeater checker for multiplex transmission for checking a repeater that repeats a cycle operation of sending a reply signal consisting of monitoring data of the control state of the control data to the receiver at the same timing as the control data. The start address data and stop address data in a plurality of consecutive address groups each indicating the repeater The start address data setting switch and the stop address data setting switch to be set respectively, and the address data generated in response to the data transmission completion detection pulse signal with the start address data set by the start address data setting switch as the initial value An address generator to be updated, a control data setting switch for setting the control data, the start switch, a power supply circuit for generating a power supply voltage for the repeater, the main synchronization signal and the sub synchronization signal, and control In the cycle, the main synchronization signal corresponding to the first bit of the address data output from the address generator based on the signal by the operation of the transmission start switch and the sub synchronization signal and the control data set by the control data setting switch. Half of the pulse A read timing signal that rises at the same timing as the previous pulse of the sub-synchronization signal is generated, and the sub-synchronization signal half cycle before the pulse of the main synchronization signal corresponding to each bit of the address data and control data. A shift signal is generated at the timing of each pulse, a read signal is generated at the same timing as each pulse of the main synchronization signal corresponding to the control data, and the main signal corresponding to the last bit of the address data and control data is generated. A timing generation circuit that causes the read timing signal to fall after a pulse of a synchronization signal is generated, the address data and control data are read in response to the read timing signal, and the address data and control data are read in response to the shift signal. The signals are sequentially shifted and serially output as the transmission signal. A first shift register; a second shift register that sequentially reads and outputs in parallel the monitoring data of the reply signal sent from the repeater in response to the read signal; and the second shift register A display for displaying the output of the device, a fall detection circuit for detecting the fall of the read timing signal to generate the data transmission completion detection pulse signal, and the data transmission completion detection pulse signal for the timing generation circuit. A logical sum circuit that regenerates a read timing signal from the timing generation circuit in the next cycle by supplying it in a logical sum combined state with a signal by operating a transmission start switch; and the timing generation circuit of the data transmission completion detection pulse signal. Variable delay circuit for delaying the transmission of the A match detection circuit for detecting a match between the input address data and the stop address data set by the stop address data setting switch, and the data transmission completion detection pulse signal in response to the match detection output of the match detection circuit. A cutoff gate for cutting off the supply to the timing generation circuit, the delay time of the variable delay circuit is set short in a control cycle for sending control data to the repeater, and is monitored from the repeater after the control cycle. It is characterized in that it is set long in the monitoring cycle for receiving data.

Embodiments of the present invention will be described below in detail with reference to the drawings.

An eighth embodiment of the repeater checker for multiplex transmission according to the present invention
A description will be given with reference to FIGS. This multiplex transmission repeater checker, as shown in FIG.
The main synchronization signal CP ₂ consisting of periodic pulses and a phase advance of 180 degrees from the main synchronization signal CP ₂ generate a pulse for a period corresponding to the number of bits of address data and control data, and then for a fixed number of periods thereafter. A sub-synchronization signal CP ₁ for stopping the generation and a transmission signal composed of address data and control data are sent from the receiver, and when the address data and the self address match, the terminal device is controlled according to the control data, Sends a reply signal consisting of monitoring data of the control status of the terminal to the receiver at the same timing as the control data. It is for checking the repeater that repeats the cycle operation, and indicates each of the multiple repeaters to be checked. Start address that sets start address data and stop address data in multiple consecutive address groups Response data setting switch SW _3A and stop address data setting switch SW _3B, and the start address data set by the start address data setting switch SW _{3A is} used as an initial value, and the address data generated in response to the data transmission completion detection pulse signal is sequentially output. Up-down counter UDC that is an address generator to be updated, and control data setting switch SW that sets control data
₄ , a transmission start switch SW ₂ , a battery power supply BT that is a power supply circuit that generates a power supply voltage for the repeater, a main synchronization signal CP ₂ and a sub-synchronization signal CP _1, and the transmission start switch SW ₂ in the control cycle. The main synchronization signal corresponding to the address data output from the up / down counter UDC, which is an address generator, and the control data setting switch SW ₄ based on the sub-synchronization signal CP ₁ and the leading bit of the control data set by the control data setting switch SW _4. Read timing signal B which rises at the same timing as the pulse of the sub-synchronization signal CP _{1 which} is a half cycle before the pulse of CP _2.
7 is generated, and a shift signal B ₃ is generated at the timing of each pulse of the sub-synchronization signal CP _{1 which} is a half cycle before the pulse of the main synchronization signal CP ₂ corresponding to each bit of the address data and the control data. generating a read signal B ₅ at the same timing as each of the main synchronization signal CP ₂ of pulses corresponding to the address data and control data is read after the occurrence of the last bit in the main synchronization signal CP ₂ corresponding pulse timing signal B ₇ And a timing generation circuit TA ₂ for falling the address signal, read address data and control data in response to a read timing signal B ₇ , and sequentially shift address data and control data in response to a shift signal B ₃ to serially transmit as a transmission signal DP. first shift register _SR 3 to be output to, and SR _4, reply signal sent from the repeater Display a second shift register SR ₅ for outputting in parallel read while sequentially shifting in response to the signal B ₅ reads monitoring data RD, a display for displaying the output of the second shift register SR ₅ Elements LED _{1 to} LED ₄ , a fall detection circuit DF that detects the rising of the read timing signal B ₇ and generates a data transmission completion detection pulse signal, and a timing generation circuit T that generates the data transmission completion detection pulse signal.
The timing generation circuit T is supplied to A _{2 in a} logical sum combined state with a signal by operating the transmission start switch SW _2.
OR gate O which is a logical sum circuit for regenerating read timing signal B ₇ from A _{2 in the} next cycle
R ₁ and the timing generation circuit T for the data transmission completion detection pulse signal
A variable delay circuit DL that delays the transmission of A ₂ , and a match detection that detects a match between the address data output from the up / down counter UDC that is an address generator and the stop address data set by the stop address data setting switch SW _3B. a circuit AD _2, the timing generating circuit TA ₂ of the data transmission completion detection pulse signal in response to the coincidence detection output of the coincidence detection circuit AD ₂
AND gate AN, which is a shut-off gate that shuts off the supply to
And a _9, a delay time of the variable delay circuit DL, characterized in that as well as shorter control cycle to send the control data to the repeater, and set longer monitoring cycle to receive monitoring data from the repeater after control cycle And

More specifically, this repeater checker for multiplex transmission has a receiver RC at the time of a test as shown in FIG.
Instead of the relay TC ₁ via _six transmission lines L _{1 to} L _6.
It is intended to be connected to the to Tc _8. The six internal divisions are as described above.

The multiplex transmission relay checker repeater with battery power supply BT, which is charged by the AC power supply AC of AC100V supplies power supply voltage to each circuit unit _TC 1 to Tc ₈
Supply a voltage of + 12V.

Then, the timing generation circuit TA ₂ always keeps the main synchronization signal CP ₂ (FIG. 9 (E)) and the sub synchronization signal CP ₁ (9th time).
As shown in FIG. 9A, when the transmission start switch SW ₂ is operated, the switch input circuit SI outputs the transmission start pulse B ₆ (FIG. 9B). Is generated, and the timing generation circuit T is generated via the variable delay circuit DL.
In addition to A ₂ , add directly to the up / down counter UDC. The timing generation circuit TA ₂ uses the transmission start pulse B ₆
And the sub-sync signal CP ₁ based on the main sync signal CP ₂
1st reading timing signal B ₇ that rises at the same timing as the half cycle before the pulse sub sync signal CP ₁ pulse _(FIG. 9 (I)) to generate the first-th main synchronization signal CP ₂ Sub-synchronization signal CP _one half cycle before the pulse of the pulse
_The shift signal B ₃ (FIG. 9 (F)) and the gate signal B ₄ (FIG. 9 (G)) are generated at the timing of the trailing edge of each pulse up to the _first pulse. On the other hand, the up-down counter UDC, when the transmission start pulse B ₆ is input, the set start address by the start address setting switch group SW _3A, to preset the example 1 address.

The shift register SR ₃ reads the address data indicating the first address output from the up / down counter UDC at the timing of the read timing signal B ₇ , and the shift register SR ₄ controls at the same timing by the control data setting switch group SW _4. The data is read, the shift registers SR ₃ and SR ₄ sequentially shift the read address data and control data by the shift signal B ₃ , and the AND circuit AN ₈ controlled by the gate control signal B ₄
A transmission signal DP (FIG. 9 (H)) having the pulse width of the gate control signal B ₄ is output through the.

In addition, the timing generation circuit TA ₂ uses the main synchronization signal CP ₂
The read signal B ₅ (FIG. 10 (A)) is generated at the same timing as each of the 9th to 12th pulses of the shift register SR ₅ based on the read signal B ₅ and the reply signal RD ( FIG. 10 (B)) is sequentially read and monitoring data is output to the output terminals Q _{0 to} Q ₃ , whereby the display elements LED _{1 to} LED ₄ are driven and the monitoring data is displayed on the display elements LED _{1 to} LED ₄ . Will be done. The reply signal RD in FIG. 10 (B) indicates that the control of 2 is completed when the pulse indicated by the broken line is not output.

When the read timing signal B ₇ falls, it generates the falling is detected by the fall detecting circuit DF and falling edge pulses (data transmission completion pulse). This falling edge pulse passes through the AND gate AN ₉ to form the waveform of FIG. 9 (J), further passes through the OR gate OR ₁ and the variable delay circuit DL, and the timing generation circuit TA.
₂ is input, and the same operation as when the transmission start pulse is input is performed. However, in this case, since the output of the AND gate AN ₉ is input to the clock input terminal CK of the up / down counter UDC, the count value of the up / down counter UDC changes from the previous 1 to 2, and this time. The address data indicating the second address is transmitted together with the same control data as the previous time, and the monitoring data is fetched and displayed as in the previous time. After that, the same operation as described above is repeated, and the address data and the control data indicating different addresses are sequentially transmitted, and the monitoring data is captured and displayed.

The address data output from the up / down counter UDC is the stop address setting switch group SW _3B.
The output of the coincidence detection circuit AD ₂ changes from the high level to the low level when it coincides with the address data (for example, address 8) set by the address gate AN ₉
Is closed, the pulse input to the timing generation circuit TA ₂ is cut off, and all operations are stopped.

Next, an operation procedure of the multiplex transmission repeater checker will be described.

The start address setting switch group SW _3A and the stop address setting switch group SW _3B are set to the start address and the stop address of the repeater to be checked.

The control data setting switch group SW ₄ is set to the control state to be checked.

Press the transmission start switch SW ₂ (control cycle).

For example, if the repeater address is 1 and the control is 2, the transmission signal DP is as shown in FIG. 11 (A), and the reply signal RD returned from the repeater TC _{1 having the} address 1 is shown in FIG. 11 (C). ), The reply signal RD at this time corresponds to the previous control state and does not become monitoring data.

Press the transmission start switch SW ₂ (monitoring cycle).

The transmission signal DP at this time is as shown in FIG. 11 (B), and the reply signal RD returned from the relay TC _{1 having} the address 1 is as shown in FIG. 11 (D), and the reply signal RD at this time is shown. The monitoring data of the transmission signal DP transmitted in
It shows the result corresponding to the control data of, and the operation of the control 2 of the repeater TC ₁ of the address 1 can be checked by comparing the control data of and the start data of. It can be checked Similarly, the repeater _TC 2 to Tc ₈ addresses 2-8.

This check is sequentially performed for each control.

As a result of such a configuration, it is possible to check the circuits of the repeaters TC _{1 to} TC ₈ , check the crossovers of the repeaters, and check the wiring of the terminal. In addition, the battery power source BT
It is easy to carry because it is operated by and is small and lightweight, and the cause of the repeater trouble can be quickly identified.

Here, in FIG. 8, regarding the variable delay circuit DL between the OR gate OR ₁ and the timing circuit TA ₂ ,
A description will be given based on FIGS. 12 and 13.

The variable delay circuit DL is capable of adjusting the delay time, and the output pulse of the differentiating circuit DF is the timing generating circuit T.
The timing to be added to A ₂ can be adjusted.

With this configuration, the transmission start switch SW _{2 is set} to 1
The same control data can be sent to all the repeaters TC _{1 to} TC ₈ by only pressing the button twice, which makes the operation extremely easy. Further, by shortening the delay time of the variable delay circuit DL in the control cycle, it is possible to shorten the transmission interval T of the address and control data to each of the repeaters TC ₁ to TC ₈ and perform the control quickly. Can be done (total control time can be shortened). On the other hand, in the monitoring cycle, by increasing the delay time of the variable delay circuit DL, each of the relays TC ₁ -TC _1- .
The transmission interval T of the address and control data to the TC ₈ can be lengthened and therefore each of the relays TC _{1 to} TC ₈ can be extended.
It is possible to increase the reception interval of the monitoring data from the display elements LED _{1 to} LE for displaying the monitoring data.
The lighting time of D ₄ can be lengthened, and as a result, the control data of each of the relays TC _{1 to} TC ₈ can be matched with the monitoring data with a margin, and the operation can be reliably checked.

Further, the maximum current consumption can be suppressed to a low level by preventing the time during which the external device (terminal device) is being controlled from overlapping.

〔The invention's effect〕

According to the repeater checker for multiplex transmission of the present invention, all the repeaters can be individually checked only by performing an extremely simple operation, and the trouble of each repeater can be quickly clarified. Further, according to the present invention, in the control cycle, by setting the delay time of the variable delay circuit to be short, the transmission interval of the address and control data to the repeater can be shortened, and control can be performed quickly, The total control time can be shortened. Also, in the monitoring cycle, by setting the delay time of the variable delay circuit long,
The reception interval of the monitoring data from the repeater can be lengthened, the lighting time of the display element that displays the monitoring data can be lengthened, and the control data of the repeater and the monitoring data can be matched with sufficient margin. Therefore, the operation can be surely checked.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a conventional multiplex transmission control system, FIG. 2 is a circuit diagram of a repeater thereof, FIGS. 3, 4, and 5 are timing charts of respective parts, FIG. 6, and FIG. 8 is a circuit diagram of a main part of a repeater, FIG. 8 is a circuit diagram of a repeater checker for multiplex transmission according to an embodiment of the present invention, and FIGS. 9, 10, and 11 are timing diagrams of respective parts thereof. FIG. 12 is a circuit diagram showing a specific configuration of the variable delay circuit, and FIG. 13 is its timing chart. BT: battery power supply (power supply circuit), SW _3A ... start address data setting switch, SW _3B ... stop address data setting switch, UDC ... up-down counter (address generator), SW ₄ ... control data setting switch , SW ₂ ... transmission start switch, TA ₂ ...
… Timing generator, SI …… Switch input circuit, S
R ₃ , SR ₄ ... First shift register, SR ₅ ... Second shift register, LED _{1 to} LED ₄ ... Display element (display device), DF ... Fall detection circuit, OR ₁ ... OR Circuit (OR circuit), DL ... Variable delay circuit, AD ₂
... Match detection circuit, AN ₉ ... AND gate (shut-off gate)

Claims (1)

[Claims] 1. A power supply voltage, a main synchronization signal composed of periodic pulses, and a phase advance of 180 degrees from the main synchronization signal, generating pulses during a period corresponding to the number of bits of address data and control data, and a constant number thereafter. The sub-synchronization signal for stopping the pulse generation during the period of, and the transmission signal composed of the address data and the control data are sent from the receiver, and when the address data and the self address match, the sub-synchronization signal is generated according to the control data. A repeater checker for multiplex transmission for checking a repeater that controls a terminal and sends a reply signal consisting of monitoring data of the control state of the terminal to the receiver at the same timing as the control data. Therefore, the start address data and the strike address in a plurality of consecutive address groups respectively indicating the plurality of repeaters to be checked are Start address data setting switch and stop address data setting switch for setting the respective set address data, and the start address data set by the start address data setting switch as an initial value, which is generated in response to the data transmission completion detection pulse signal. An address generator for sequentially updating address data, a control data setting switch for setting the control data, a transmission start switch, a power supply circuit for generating a power supply voltage for the repeater, the main synchronizing signal and the sub synchronizing signal. The address data corresponding to the first bit of the control data generated by the operation of the transmission start switch in the control cycle and output from the address generator based on the sub-synchronization signal and the control data set by the control data setting switch. Previous A read timing signal that rises at the same timing as the pulse of the sub-synchronization signal half cycle before the pulse of the main synchronization signal is generated, and a half of the pulse of the main synchronization signal corresponding to each bit of the address data and control data is generated. A shift signal is generated at the timing of each pulse of the sub-sync signal before a cycle, a read signal is generated at the same timing as each pulse of the main sync signal corresponding to the control data, and the read signal is generated. A timing generation circuit that causes the read timing signal to fall after the pulse of the main synchronization signal corresponding to the final bit is generated, and the address data and control data are read in response to the read timing signal, and in response to the shift signal. The address data and the control data are sequentially shifted and the data is sent. A first shift register for outputting in series as a signal, and a second shift register for sequentially reading and outputting in parallel the monitoring data of the reply signal sent from the repeater in response to the read signal. A display for displaying the output of the second shift register; a fall detection circuit for detecting the fall of the read timing signal to generate the data transmission completion detection pulse signal; and a data transmission completion detection pulse signal for the fall detection circuit. A logical sum circuit that regenerates a read timing signal from the timing generation circuit in the next cycle by supplying the timing generation circuit in a logical sum combined state with a signal by operating the transmission start switch, and the data transmission completion detection pulse signal A variable delay circuit for delaying the transmission of the timing generating circuit, A match detection circuit that detects a match between the address data output from the address generator and the stop address data set by the stop address data setting switch, and the data transmission completion in response to the match detection output of the match detection circuit. And a cutoff gate for cutting off the supply of the detection pulse signal to the timing generation circuit, the delay time of the variable delay circuit is set short in the control cycle for sending control data to the repeater, and after the control cycle A repeater checker for multiplex transmission, wherein the repeater checker is set to be long in a monitor cycle for receiving monitor data from the repeater.