JPS60199256A - Repeater checker for multiplex transmission - Google Patents

Abstract

PURPOSE:To check individually repeaters by controlling a terminal device in response to a control data by a repeater checker when a power supply voltage and a transmission signal comprising a main synchronizing signal, sub-synchronizing signal, address data and a control data are transmitted from a receiver when the address data and the own address are coincident. CONSTITUTION:A shift register SR3 reads an address data outputted from an up-down counter UDC in the timing of a read timing signal B7, shift registers SR3, SR4 shift sequentially the read address data and the control data by using a shift signal B3 and output a transmission signal DP having a pulse width the same that of a gate control signal B4. When the address data outputted from the UDC is coincident with the address data set by a stop address setting switch group SW3B, the output of a coincidence detection circuit AD2 changes from a high level to low level, an AND gate AN9 is closed and the pulse input to a timing generating cirlcuit TA2 is disconnected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a repeater checker for multiplex transmission.

[Background technology]

As shown in Figure 1, a general multiplex transmission control system consists of one receiver RC and, for example, eight repeaters (each assigned an address from 1 to 8) TC+ to T.
C8 is connected through a transmission line, and a load (not shown) is connected to each repeater TC, to TC8, respectively.

The receiving v&RC controls the terminals via repeaters TC and -TC8, and also monitors the control status of the terminals. Specifically, the receiver RC sends address data 1 of a repeater connected to a terminal to be controlled, such as TC, and control data of the terminal to the transmission line.

Each repeater 101 to 10 takes in the address data and control data sent out to the transmission line, compares the read address data with its own address data, and when they match (self The terminal device is controlled based on the control data captured when the address is specified.

In this case, since the address data is 1, the repeater TC
I switches the control state of the terminal device based on the control data,
The other repeaters Tc1 to Tc8 do not switch their control states.

Also, at this time, the repeater T whose own address is specified
C1 sends monitoring data to the transmission line at the same timing as the control data is taken in, and the receiver RC takes in this monitoring data at the same timing as the control data, and monitors the control state of the terminal.

This monitoring data is for the previously sent control data.

Normally, this multiplex transmission control system operates in two cycles: a previous control cycle and a subsequent monitoring cycle. In the control cycle, control data is sent to the repeaters Tc1-"rc8 of Address Address 8, and in the monitoring cycle, address 8
The monitoring data of the repeaters Tc1 to TC8 are taken in, but no monitoring data is taken in during the control cycle, and no control data is sent during the monitoring cycle.

A repeater used in such a multiplex transmission control system is configured as shown in FIG. This repeater is of a three-control, three-monitoring type, and is connected to the receiver RC through six transmission lines L1 to L6. The six lines are divided into power supply line L1 that supplies power supply voltage +12V and GND.
(ground) line L2, transmission signal line L3 that sends the transmission signal (address data + control data) DP, reply signal line L4 that sends the reply signal (monitoring data) RD, sub-synchronization signal line L5 that sends the sub-synchronization signal CP, This is the main synchronization signal line L6 that sends the main synchronization signal CP2. Sub synchronization signal cpl, main synchronization signal cp2. The transmission signal DP and reply signal RD are transmitted at the timing shown in FIG. The main synchronization signal CP2 is constantly sent out from the receiver RC with a period of IKHz and a high level (power supply voltage) time of 0.3 m5ec.

The sub synchronization signal CP is the same pulse as the main synchronization signal CP2, but is transmitted with a phase lead of 180 degrees, and is transmitted corresponding to the 1st to 12th pulses of the main synchronization signal CP2, and the 13th pulse is the same as the main synchronization signal CP2. The four pulses of the period corresponding to the 16th pulse are empty pulses, and each repeater 'rc, -'rce detects the start information of signal transmission/reception by these four empty pulses. The transmission signal DP consists of address data from the 1st bit to the 8th pinpoint and control data from the 9th bit to the 12th bit. It is sent sequentially with pulse and pacing timing. The reply signal RD is sent at the same timing as the 9th to 12th pulses of the main synchronization signal cp2.

This repeater is configured to supply power to each circuit section through a power supply circuit E1. Then, the main synchronization signal cp2 < Fig. 4 (B)) and the sub-synchronization signal CP sent from the receiver RC.
, (FIG. 4(A)), the timing generation circuit TA
, generates various timing pulses.

This timing generation circuit TAI generates a read signal A3 (fourth
(D)) and applies this read signal A3 to the clock input terminal CK of the shift register SR. As a result, the shift register SR, transmits the transmission signal DP (address data + control data: Fig. 4) sent from the receiver RC.
C)) will be read while being shifted sequentially.

While this shift register SR is reading the transmission signal DP by the read signal A3 (FIG. 5(A)),
Specifically, eight pulses are output as the read signal A3, 8-bit address data of the transmission signal DP is read into the shift register SR1, and the address data is output from the output terminals Q1 to Q8 of the shift register SR. In a state where the main synchronization signal C is output in parallel, that is, the main synchronization signal C
At the same timing as the pulse of the sub synchronization signal CP1 between the 8th and 9th pulses of P2, the timing generation circuit TA generates the address matching timing determination signal A, (5th
(B)) and sends it to the address match detection circuit AD.

The address match detection circuit AD detects address data outputted from the output terminals Q1 to Q8 of the shift register SR and eight address setting switch groups SW in response to the address match timing determination signal A4.

When the two addresses match, an address match signal is generated at the output terminal Q, and this signal is applied to the output circuit DR.

Furthermore, even after the address match signal is generated, the shift register SR continues to read the transmission signal DP, and the main synchronization signal c
At the same timing as the 9th to 12th pulses of p2, the timing generation circuit TA1 outputs timing pulses A, , A7 . A8 (Figure 5 (F), (G), (H))
are generated and applied to the output circuit DR.

In the state where the address match signal is input, the output circuit DR outputs the output timing pulse A6. When A7A8 is added, shift register SR.

are output from the output terminals Q1 to Q3 of the data input terminals D1 to D1.
The control data input to D3 is output to the output terminal Q.

It is output from ~Q3 and controls relays RY and ~RY3 via delay circuits DL and ~DL3.

Further, the timing generation circuit TA generates a main synchronization signal cp2.
The sub-sync signal C between the 12th and 13th pulse of
Reset signal A5 (
FIG. 5(E)) is generated and applied to the address match detection circuit ADI. As a result, address match detection circuit A
DI stops outputting the address match signal.

Further, the timing generation circuit TA+ outputs the main synchronization signal CP2.
The sub-sync signal CPl between the 8th and 9th pulses of
Read signal A2 that rises at the same timing as the pulse of
(FIG. 5(D)) is generated and added to the shift register SR2. Shift register SR2 reads 3-bit monitoring data applied to input terminals P1 to P4. This monitoring data is input via photocouplers PCI to PC3.

After this, the timing generation circuit TA generates the main synchronization signal CP.
A sending timing signal A1 (FIG. 5(C)) is generated at the same timing as the 9th to 12th pulses of No. 2, and the monitoring data is sequentially shifted and sent out from the output terminal Q as a reply signal RD.

Note that the reply signal RD is sent only when an address is specified, and although it is not shown in the circuit diagram, it may be configured such that, for example, monitoring data is generated only when an address matching signal is output. Alternatively, this can be realized by generating the sending timing signal A1 only when an address match signal is generated.

Address match detection circuit AD is specifically realized by a circuit as shown in FIG. In FIG. 6, the exclusive OR circuits EX, ~EX8 and the AND circuit AN output address data (D, ~Do) and a self address (Dl'
~D8'), and when they all match, the output of the AND circuit AN becomes high level, and the output of the AND circuit AN is transferred to the D flip-flop FFI.
is held in response to the address match determination timing signal 4, and D flip-flop FF,
or reset.

The output circuit DR is specifically realized by a circuit as shown in FIG. In FIG. 7, AND circuits AN2 to AN
4 opens when the address match signal is output and passes control data (DI-D:l) to AND circuits AN6 to A.
Ny is the output timing pulse A6. When AV and As are output, it is opened to allow control data (DI-D3) to pass through.

Such a multiplex transmission control system is constructed on site, and during construction, sensors are connected to trunk wiring such as signal lines and power lines, and to repeaters.

There are two possibilities: trouble may occur with the repeater due to incorrect wiring to the damper or the like, and trouble may occur due to a defect in the repeater itself.

There has been a demand for a checker that can check each repeater individually in order to quickly determine the cause of such troubles and deal with the troubles.

(Object of the Invention) An object of the present invention is to provide a repeater checker for multiplex transmission that can check repeaters individually.

[Disclosure of the invention]

In the multiplex transmission repeater checker of the present invention, when a transmission signal consisting of a power supply voltage, a main synchronization signal, a sub-synchronization signal, address data, and control data is sent from a receiver, and the address data matches its own address, A multiplex transmission repeater for checking a repeater that controls a terminal device according to the control data and sends a return signal consisting of monitoring data of the control state of the terminal device to the receiver at the same timing as the control data. A checker that generates address data and control data of a repeater to be checked,
address and control data generating means for sequentially changing either address data or control data starting from the first one each time a data transmission completion detection pulse is input; and a synchronizer for generating the main synchronization signal and the sub synchronization signal. A signal generation circuit, a power supply circuit that generates a power supply voltage for the repeater, a transmission start switch, and output from the address and control data generation means in response to the operation of the transmission start switch and a data transmission completion detection pulse. a first shift register that reads address data and control data and sends it out in series as the transmission signal; a second shift register that reads monitoring data of the reply signal sent from the repeater while sequentially shifting it and outputs it in parallel; , a display that displays the output of the second shift register, and a data transmission completion detection pulse applied to the address and control data generating means and the first shift register when transmission of the set of address data and control data is completed. transmission completion detection means, and when one of the address data and control data generated from the address and control data generation means becomes the final number, the transmission completion detection pulse is sent to the address and control data generation means. The present invention is characterized in that it is configured to include a cutoff means for cutting off the supply.

Embodiments of the present invention will be described in detail below with reference to the drawings.

The eighth embodiment of a multiplex transmission repeater checker according to an embodiment of the present invention
This will be explained based on FIGS. 11 to 11.

As shown in FIG. 8, this multiplex transmission intermediate checker is connected to the repeaters Tc, -'rC8 through six transmission lines t, -'rC8 instead of the reception fiRc during testing. It is something that The division into six pieces is as described above.

In this multiplex transmission repeater checker, the bacterial power supply BT charged by the AC power supply AC of AClooV supplies power supply voltage to each circuit section, and the repeaters TC1 to TC8
A voltage of +12V is supplied to the

The timing generation circuit TA2 constantly generates the main synchronization signal cp2 (Fig. 9(E)) and the sub-synchronization signal cp, (Fig. 9(D)), as shown in Fig. 9(A). When the transmission start switch sw2 is operated, the switch input circuit s1 generates a transmission start pulse Bs (FIG. 9(B)) and applies it to the timing generation circuit TA2 and the amplifier down counter UDC. The timing generation circuit TA2 generates a read signal that rises at the same timing as the pulse of the sub-synchronizing signal CPl, which is half a cycle before the first pulse of the main synchronizing signal CP2, based on the transmission start pulse B6 and the sub-synchronizing signal cP1. Timing signal B? (FIG. 9(I)), and the pulse of the sub-sync signal CP1 is generated from the pulse of the sub-sync signal CP1 half a cycle before the first pulse of the main sync signal CP2 to the pulse of the sub-sync signal CP1 half a cycle before the 12th pulse. At the timing of the trailing edge of each pulse up to, shift signal B3 (Fig. 9 (F))
and generates gate signal B4 (FIG. 9(G)).

On the other hand, when the transmission start pulse B6 is input, the up/down counter UDC receives the start address set by the start address setting switch group 5W3A, for example 1.
Bricent the street address.

The shift register SR3 reads the address data indicating the 1st address output from the up/down counter UDC at the timing of the read timing signal B7, and the shift register SR4 reads the control data set by the control data setting switch group SW4 at the same timing. Shift registers SR3 and SR4 sequentially shift read address data and control data in response to a shift signal B3, and an AND circuit AN8 controlled by a gate control signal B4.
A transmission signal DP (FIG. 9(H)) having a pulse width of the gate control signal B4 is outputted through the gate control signal B4.

The timing generation circuit TA2 also generates a main synchronization signal CP2.
A read signal B6 (Fig. 10 (A)) is generated at the same timing as each of the 9th to 12th pulses of , and the shift register SR5 generates a reply signal RD (Fig. (B)) are sequentially read and the monitoring data is output to the output terminals QO-Q3, thereby driving the display elements LED, .about.LED, and the monitoring data is displayed on the display elements LED, .about.LED4. Note that the reply signal RD in FIG. 10(B) indicates that the second control is completed when the pulse indicated by the broken line is not output.

Then, when the read timing signal B7 falls, the falling edge detection circuit DF detects this falling edge and generates a falling edge pulse (data transmission completion pulse). This falling edge pulse passes through the ant gate (A N s) and becomes the waveform shown in FIG.
It is input to the timing generation circuit TA2 through R, and the same operation as when the transmission start pulse is input is performed. However, in this case, the output of the AND gate AN9 is the clock input terminal C of the up/down counter UDC.
Since the count value of the up/down counter UDC changes from 1 to 2, this time the address data indicating address 2 is sent together with the same control data as last time, and the same control data as before is sent. Capture and display monitoring data.

Thereafter, the same operation as described above is repeated, and address data indicating specific addresses and control data are sequentially transmitted, and monitoring data is captured and displayed.

Then, the address data output by the up/down counter UDC is the stop address setting switch group 5w3B.
When the address data (for example, indicating address 8) matches the address data set by , the output of the match detection circuit AD2 changes from a high level to a low level, the AND gate AN9 closes, and a pulse is input to the timing generation circuit TA2. is shut off and all operations stop.

Next, the operating procedure of this multiplex transmission repeater checker will be explained.

(2) Set the start address setting switch group 5W3A and the stop address setting switch group 5W3B to the start address and stop address of the repeater to be checked.

■ Set the control data setting switch group SW4 to the control state to be checked.

■Press the transmission start switch sw2 (control cycle).

For example, if the repeater address is 1 and the control is 2, the transmission signal DP will be as shown in FIG.
The response signal RD at this time corresponds to the previous control state and does not serve as monitoring data.

■Press the transmission start switch SW2 (monitoring cycle).

The transmission signal DP at this time is as shown in FIG. 11(B), and the reply signal R returned from the repeater TC1 of address 1
D becomes as shown in FIG. 11 (D), and the monitoring data of the reply signal RD at this time shows the result corresponding to the control data of the transmission signal DP transmitted in ■, and the control data in ■ and the control data in ■ Comparing with monitoring data,
The operation of control 2 of repeater TC1 at address l can be checked. The repeaters TC2 to TC at addresses 2 to 8 can also be checked in the same way.

Note that this checker is performed sequentially for each control.

As a result of this configuration, the circuits of each repeater TC to TC8 can be checked, and the repeater crossover wires can be checked.

You can check the terminal wiring. In addition, since it is operated by the Hasoteri electric SBT and is small and lightweight, it is easy to carry, and the cause of repeater trouble can be quickly determined.

Another embodiment of the invention will be described based on FIGS. 12 and 13. This multiplex transmission repeater checker is the first
As shown in Figure 2, a delay circuit DL that can adjust the delay time is provided between the OR gate OR1 and the timing generation circuit TA2.
is inserted so that the timing at which the output pulse of the differentiating circuit DF is applied to the timing generating circuit TA2 can be adjusted.

With this configuration, the transmission start switch SW2 is set to 1.
With just one press, the same control data can be sent to all repeaters TC to TC8, making operation extremely easy. In addition, in the control cycle, by shortening the delay time of the delay circuit DL, the transmission interval T of addresses and control data to each relay WTC, ~TC8 can be shortened, and control can be performed quickly. (The total control time can be shortened). On the other hand, in the monitoring cycle, the delay circuit D
Each repeater TC by increasing the delay time of L.

~The transmission interval T of address and control data to TC8 can be lengthened, so that each repeater T Cla~
A display element LED that can lengthen the reception interval of the monitoring data from the TC8 and therefore displays the monitoring data;
- The lighting time of the LED 4 can be increased, and as a result, the control data and monitoring data of each repeater TC1 to TC8 can be compared with sufficient time, and the operation can be checked reliably.

Furthermore, by making it possible to prevent the times during which external equipment (terminals) are being controlled from overlapping, the maximum current consumption can be kept low.

In the above embodiment, the address data is from address 1 to address 8.
The address of each repeater TC, -Tce is changed automatically.
Although the same control can be performed by one operation of the transmission start switch SW2, the control data may be changed automatically. In this case, monitoring data corresponding to the previous control data will be obtained this time, and monitoring data corresponding to the current control data will be obtained next time. In other words, if the control data is changed sequentially (the address data is the same) every cycle, the monitoring data indicating the operating state for this control data will be obtained with a one cycle delay, and the control data of a certain cycle and the monitoring data will be obtained with a delay of one cycle. The check can be made by comparing the monitoring data of the next cycle.

Further, both the address data and the control data may be sequentially changed (for example, so that the combination of the address data and the control data becomes a round robin).

The operating procedure in this case is a combination of the procedure for changing address data and the procedure for changing control data.

〔Effect of the invention〕

According to the $15 checker for multiplex transmission of the present invention, all repeaters can be checked individually by performing extremely simple operations, and troubles in each repeater can be quickly resolved. In addition, the second invention can further shorten the total control time and ensure operation check.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a conventional multiplex transmission control system, Figure 2 is a circuit diagram of its repeater, Figure 3 (1!J), Figures 4 and 5 are timing diagrams of each part, Figures 6 and FIG. 7 is a specific circuit diagram of the main parts of a repeater, FIG. 8 is a circuit diagram of a repeater checker for multiplex transmission according to an embodiment of the present invention, and FIGS. 9 and 10.
11 and 11 are timing diagrams of each part thereof, FIG. 12 is a circuit diagram of a main part of a multiplex transmission repeater checker according to another embodiment of the present invention, and FIG. 13 is a timing diagram thereof. BT... Buffer power supply, SW2... Transmission start switch, TA2... Timing generation circuit, SR3, SR4
゜SR5...Shift register, SW, 3...Address data setting switch, SW4...Control data setting switch, LEDI-LED4...Display element, DL...
・Delay circuit, DF...Falling detection circuit Figure 1

Claims (1)

[Claims] fil A transmission signal consisting of a power supply voltage, a main synchronization signal, a sub-synchronization signal, address data, and control data is sent from the receiver, and when the address data and the self address match, the control data is control the terminal according to the
A multiplex transmission repeater check for checking a repeater that sends a return signal consisting of monitoring data of the control state of the terminal device to the receiver at the same timing as the control data, the repeater to be checked. address and control data generation means for generating address data and control data, and sequentially changing one of the address data and control data from the first one each time a data transmission completion detection pulse is input; a synchronization signal generation circuit that generates a synchronization signal and a sub-synchronization signal; a power supply circuit that generates a power supply voltage for the repeater; a transmission start switch; a first shift register that reads address data and control data output from the address and control data generating means and sends them out in series as the transmission signal; and a first shift register that sequentially shifts and reads monitoring data of a reply signal sent from the repeater. a second shift register that outputs in parallel, a display that displays the output of the second shift register, and a data transmission completion detection pulse that generates a data transmission completion detection pulse when transmission of a set of address data and control data is completed. and a transmission completion detection means for applying the transmission completion detection pulse to the first shift register, and the transmission completion detection pulse when either one of the address data and control data generated from the address and control data generation means becomes the final number. and a cutoff means for cutting off supply to the address and control data generation means. (2) A transmission signal consisting of a power supply voltage, a main synchronization signal, a sub-synchronization signal, address data, and control data is sent from the receiver, and when the address data and its own address match, the terminal device control,
A multiplex transmission repeater check 7 for checking a repeater that sends a return signal consisting of monitoring data of the control data of the terminal device to the receiver at the same timing as the control data.
generating the address data and control data of the repeater to be checked, and sequentially changing either the address data or the control data from the first one each time the data transmission completion detection pulse is input. address and control data generation means, a synchronization signal generation circuit that generates the main synchronization signal and the sub synchronization signal, a power supply circuit that generates a power supply voltage for the repeater, a transmission start switch, and a transmission start switch for operating the transmission start switch. a first shift register that reads address data and control data output from the address and control data generating means in response to a base start pulse and a data transmission completion detection pulse, and serially sends out the address data and control data as the transmission signal; A second shift register that sequentially shifts and reads the monitoring data of the sent reply signal and outputs it in parallel, a display that displays the output of this second shift register, and a set of address data and control data transmission. transmission completion detection means for supplying a data transmission completion detection pulse to the address and control data generation means and the first shift register upon completion; and one of the address data and control data generated from the address and control data generation means. a cutoff means for cutting off the supply of the transmission completion detection pulse to the address and control data native means when the transmission completion detection pulse reaches the final number, and delaying the data transmission completion detection pulse outputted from the transmission completion detection means. and a variable delay circuit for supplying the first shift register to the first shift register.