JPS60178745A - Repeater checker for multiplex transmission - Google Patents

Abstract

PURPOSE:To dissolve quickly the trouble of each repeater by displaying the output of the 2nd shift register which reads with sequential shift the monitor data on the reply signals sent from a repeater then outputs those monitor data in parallel to each other. CONSTITUTION:Shift registers SR3 and SR4 shift successively both the address data and control data read by a shift signal B3 and delivers a transmission signal DP having the pulse width of a gate control signal B4 through an AND circuit AN8 which is controlled by the signal B4. A timing producing circuit TA2 produces the read signal B5 with the same timing as each of the 9th-12th pulses of a main synchronizing signal CP2. Then a shift register SR5 reads successively replay signals RD according to the signal B5 and outputs monitor data through output terminals Q0-Q3. Thus display elements LED1-LED4 are driven to display the monitor data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a repeater checker for multiplex transmission.

r1! Background Technology] A general multiplex transmission control system, as shown in Figure 1, has one receiver RC and, for example, eight repeaters (each address is assigned 1 to 8) T.
c1 to Tc8 are connected through transmission lines, and each repeater Tc1 to
A load (not shown) is connected to each terminal.

The receiver RC controls the terminals via the repeaters Tc1 to 'rce, and monitors the control status of the terminals. Specifically, the receiver RC sends address data 1 of a repeater, such as a TC, to which a terminal to be controlled is connected, and control data of the terminal to a transmission line. Each repeater Tc1 to TC8 is adapted to take in the address data and control data sent out to the transmission line, and compares the read address data with its own address, and when they match (own address The terminal device is controlled based on the control data imported when the terminal is specified.

In this case, since the address data is 1, the repeater TC
1 switches the control state of the terminal device based on the control data, and the other repeaters TC1 to TC8 do not switch the control state.

Also, at this time, the repeater T whose own address is specified
C1 sends monitoring data to the transmission line at the same timing as the control data is taken in, and the receiver RC takes in this monitoring data at the same time as the control data is sent, and monitors the control status of the terminal device. .

This monitoring data is for the previously sent control data.

Normally, this multiplex transmission control system operates in two cycles: a previous control cycle and a subsequent monitoring cycle. In the control cycle, control data is sent to the repeaters TC1 to TC8 of the address address 8, and in the monitoring cycle, control data is sent to the repeaters TC1 to TC8 of the address address 8. The monitoring data of the repeaters Tc1 to TC8 in the control cycle are taken in, and the monitoring data is not taken in in the control cycle, and the control data is not sent in the monitoring cycle.

A repeater used in such a multiplex transmission control system is configured as shown in FIG. This repeater is of a three-control, three-monitoring type, and is connected to the receiver RC through six transmission lines L1 to L6. The six lines are divided into power supply lines L1, GND (ground line) T, 2, which sends the power supply voltage ++2V, transmission signal line L3, which sends the transmission signal (address data + control data) DP, and sends the return signal (monitoring data) RD. Reply signal line L4, sub synchronization signal CP1
A sub synchronization signal line L5 is used to transmit the synchronization signal cp2, and a main synchronization signal line L6 is used to transmit the main synchronization signal cp2. Secondary synchronization signal CP, main synchronization signal cP2. The transmission signal DP and the reply signal RD are the third
It is transmitted at the timing shown in the figure. Main synchronization signal CP2
is the period I KHz,' high level (power supply voltage)
It is constantly transmitted from the receiver RC at a time of 0.3 msec. The sub synchronization signal CPl is transmitted with the same pulse as the main synchronization signal CP2 with a phase lead of 180 degrees, and is transmitted corresponding to the 1st to 12th pulses of the main synchronization signal CP2, and the 13th to 13th pulses are respectively transmitted. The four pulses in the period corresponding to the 16th pulse are empty pulses, and these four empty pulses cause each repeater TC to be connected.

~TC8 is configured to detect signal transmission/reception star I] information. The transmission signal DP consists of address data from the 1st bit to the 8th bit and control data from the 9th bit to the 12th bit, and these data are generated by the 1st to 12th pulses of the main synchronization signal CP2 are sent sequentially at the same timing. The reply signal RD is sent at the same timing as the 9th to 12th pulses of the main synchronization signal cp2.

This repeater is configured to supply power to each circuit section through a power supply circuit E1. Then, the main synchronization signal cp2 (Fig. 4(B)) and the sub-synchronization signal C sent from the receiver RC.
A timing generation circuit TA generates various timing pulses based on P, (FIG. 4(A)).

This timing generating circuit TA generates a read signal A3 (Fig. 4 (D)) consisting of 12 pulses at the same timing as the 1st to 12th pulses of the main synchronizing signal CP2. , applies this read signal A3 to the clock input terminal CK of the shift register SR,. As a result, the shift register SR, transmits the transmission signal DP (address data + control data: Fig. 4) sent from the receiver RC.
C)) will be read while being shifted sequentially.

This shift register SR, reads the read signal A, 1 (fifth
While reading the transmission signal DP as shown in Figure (A)), specifically, eight pulses are output as the read signal A3, and 8-bit address data of the transmission signal DP is read into the shift register SR1. , shift register SR, in a state where address data is output in parallel from output terminals 01 to 0, that is, the sub synchronization signal CPi between the 8th and 9th pulses of the main synchronization signal CP2. At the same timing as the pulse, the multi-timing generation circuit TA generates an address coincidence timing determination signal A4 (FIG. 5(B)) and sends it to the address coincidence detection circuit AD.

The address match detection circuit AD detects the output terminal Q of the shift register SR1 by the address match timing determination signal A4.
The address data output from 1 to Q8 is compared with the self-address set by the 8 address setting switches/nona group SWs, and when both addresses match, an address match signal is generated at the output terminal Q. , this is output circuit DR
Add to.

Further, even after the address match signal is generated, the shift register SR continues reading the transmission signal DP, and the timing generation circuit TA1 generates the m timing at the same timing as the 9th to t7 12th pulses of the main synchronization signal cp2. Pulse A6. A7. A8 (Figure 5 (F), (G), (H)
)) and apply them to the output circuit DR.

In the state where the address match signal is input, the output circuit DR outputs the output timing pulse A6. A? .

When A8 is added, shift register SR.

is output from the output terminals Q1 to Q3 of the data input terminal D1.
The control data input to ~D3 is outputted from output terminals Q1 to Q3, and relay RY1 is output via delay circuits DL and ~DL3.
~Control RY3.

Further, the timing generation circuit TA generates a main synchronization signal CP2.
The sub-sync signal C between the 12th and 13th pulse of
Reset signal As (
FIG. 5(E)) is generated and applied to the address match detection circuit AD. As a result, the address match detection circuit AD
stops outputting the address match signal.゛The timing generation circuit TA also outputs the main synchronization signal cp2.
a sub-synchronization signal CP between the eighth and ninth pulses of
Read signal A2 that rises at the same timing as the pulse of
(FIG. 5(D)) is generated and added to the shift register SR2. Shift register SR2 reads 3-bit monitoring data applied to input terminals P1 to P4. This monitoring data is input via photocouplers PC1 to PC3.

After this, the timing generation circuit TA1 generates the main synchronization signal CP
A sending timing signal A1 (FIG. 5(C)) is generated at the same timing as the 9th to 12th pulses of No. 2, and the monitoring data is sequentially shifted and sent out from the output terminal Q as a reply signal RD.

Note that the reply signal RD is sent only when an address is specified, and although it is not shown in the circuit diagram, it may be configured such that, for example, monitoring data is generated only when an address matching signal is output. , or by generating the sending timing signal A only when an address match signal is generated.

Specifically, the address match detection circuit AD is realized by a circuit as shown in FIG. 6.7 In FIG. 6, the exclusive OR circuits EX, to EX8 and the AND circuit AN are
The address data (D+ to D8) and the self address (D1 to D8) are compared individually, and when they all match, the output of the AND circuit AN becomes high level, and the output of the AND circuit AN is D flip-flop FFI
is held in response to the address match determination timing signal A4, and the D free knob flop FF is held by the reset signal A5.
Specifically, the output circuit DR in which the output circuit DR is reset is realized by a circuit as shown in FIG. In FIG. 7, AND circuits AN2 to AN4 open when an address match signal is output and control data (DI"D
3), the AND circuits AN5 to AN7 output timing pulses A6. A7. When AB is output, it is opened to pass control data (D, to D3).

Such a multiplex transmission control system is constructed on site, and during construction, sensors are connected to trunk wiring such as signal lines and power lines, and to repeaters.

There are two possibilities of trouble occurring: trouble with the repeater may occur due to incorrect wiring to the damper, etc., or trouble may arise due to a defect in the repeater itself.

In order to quickly determine the cause of such troubles and deal with the troubles, there has been a need for a checker that can check each repeater individually.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a repeater checker for multiplex transmission that can check repeaters individually.

[Disclosure of the invention]

In the multiplex transmission repeater check/tsuka of the present invention, a transmission signal consisting of a power supply voltage, a main synchronization signal, a sub-synchronization signal, address data, and control data is sent from the receiver, and the 7 trace data and the self address match. A multiplex transmission repeater checker for checking a repeater that controls a terminal device according to the control data and sends a return signal consisting of monitoring data of the control state of the terminal device to the receiver. an address data setting switch for setting the address of the repeater to be checked; a control data setting switch for setting control data; a synchronization signal generation circuit for generating the main synchronization signal and the sub-synchronization signal; a power supply circuit that generates a power supply voltage; a transmission start switch; , a second shift register that sequentially shifts and reads the monitoring data of the reply signal sent from the repeater and outputs it in parallel; and a display that displays the output of the second shift register. It is characterized by

Embodiments of the present invention will be described in detail below based on the drawings.

The eighth embodiment of the multiplex transmission repeater according to the present invention is shown in FIG.
This will be explained based on FIGS. 11 to 11.

As shown in FIG. 8, this multiplex transmission repeater checker has six transmission lines L instead of the receiver RC during testing.
It is connected to repeaters TC1 to TC8 via lines 1 to L6. The six internal divisions are as described above.The multiplex transmission repeater checker supplies power supply voltage to each circuit section from the battery power supply BT charged by the AC power supply AC of AClooV, and also connects the repeaters TC1 to TC81.
This voltage of +12V is supplied.

The timing generation circuit T A 2 always outputs the main synchronization signal CP2 (FIG. 9(C)) and the sub-synchronization signal CPi <
Fig. 9(B)) is generated, and the transmission start switch S
When W2 is pressed, the switch input circuit S[ generates a transmission start pulse B6 (FIG. 9(A)) and applies it to the timing generation circuit T A 2. The timing generation circuit 1゛A2 is
Based on the transmission start pulse B6 and the sub-synchronizing signal CP, the read timing signal B? rises at the same timing as the pulse of the sub-synchronizing signal CP half a period before the first pulse of the main synchronizing signal CP2. (FIG. 9(G)) and the sub-sync signal CP half a cycle before the 1st pulse of the main synchronizing signal CP2, and the sub-sync signal CP half a cycle before the 12th pulse from the pulse of the main synchronizing signal CP1. A shift signal B3 (FIG. 9(D)) and a gate control signal B4 (FIG. 9(E)) are generated at the timing of the trailing edge of each pulse up to the pulse. The shift register SR3 reads the address data set by the address data setting switch group SW3 at the timing of the read timing signal B7, and the shift register SR3 reads the address data set by the address data setting switch group SW3.
4 is the control data setting switch group SW4 at the same timing.
The shift registers SR3 and SR4 read in the control data set by the shift register SR3 and SR4, and the shift registers SR3 and SR4 sequentially shift the read address data and control data by the shift signal B3, and output the gate control signal through an AND circuit A N B controlled by the gate control signal B4. Transmission signal D with a pulse width of B4
P (FIG. 9(F)) is output.

Further, the timing generation circuit T A 2 receives the main synchronization signal C
Read signal B5 at the same timing as each of the 9th to 12th pulses of P2 (Figure 10 (A))
The shift register SR5 receives this read signal B.
5, the reply signal RD (FIG. 10(B)) is read in sequence, and the monitoring data is output to the output terminals QO to Q3, thereby driving the display elements LED to LED4, and the monitoring data is output to the display elements LED, ~It will be displayed on LED4. Note that the reply signal RD in FIG. 10(B) indicates that the second control is completed when the pulse indicated by the broken line is not output.

Next, the operating procedure of this multiplex transmission repeater checker will be explained.

■Set the address setting switch group SW3 to the repeater address to be checked.

■Control data setting switch - Set the 7,000 group SV/4 to the desired control state.

■Press the transmission start switch SW3 (control cycle). For example, if the repeater address is 1 and the control is 2, the transmission signal DP will be returned from the repeater TC at address 1, as shown in Fig. 11 (A). The reply signal RD sent by I8 is shown in FIG.
), and the reply signal RD at this time corresponds to the previous control state and does not serve as monitoring data.

■Press the transmission start switch SW3 (monitoring cycle).

The transmission signal DP at this time becomes as shown in FIG. 11 (CB), and the reply signal R returned from the repeater TC of address 1
D becomes as shown in FIG. 11 (D), and the monitoring data of the reply signal RD at this time is the transmission signal DP transmitted in
This shows the result corresponding to the control data of 1. By comparing the control data of 3 with the monitoring data of 2, the operation of control 2 of the repeater TC at address 1 can be checked.

Note that this check is performed on the repeaters TC1 to TC of each address.
As a result of this configuration, the circuits of each repeater TC, to TC8 are checked, and the repeater crossover wires are checked.

You can check the terminal wiring. In addition, since it is operated by the battery power source BT and is small and lightweight, it is easy to carry, and the cause of repeater door pull can be quickly determined.

Another embodiment of the invention will be described based on FIGS. 12 and 13. As shown in FIG.
Figure 13 (A)) is inverted with the inverter IN.
B in Figure CB)? ), this is further differentiated by a differentiating circuit DF (Fig. 13 (C)), and this differentiated signal B7'' and the output signal of the transmission start switch SW3 are sent to the switch input circuit SI via an OR circuit OR. By simply pressing the transmission start switch SW1 once, two cycles of operation including a control cycle and a monitoring cycle can be performed, making the operation easy.

In the above embodiment, there were eight repeaters, but since addresses can be set using a combination of 8-bit data, a maximum of 256 addresses can be set, and control data and monitoring Up to eight types of data can be set.

〔Effect of the invention〕

According to the multiplex transmission repeater checker of the present invention, troubles in each repeater can be quickly resolved.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of a conventional multiplex transmission control system, Figure 2 is a circuit diagram of its repeater, Figures 3, 4, and 5.
6 and 7 are specific circuit diagrams of the main parts of the repeater. FIG. 8 is a circuit diagram of a repeater checker for multiplex transmission according to an embodiment of the present invention. 10 and 11 are timing diagrams of each part thereof, FIG. 12 is a circuit diagram of a main part of a multiplex transmission repeater checker according to another embodiment of the present invention, and FIG. 13 is a timing diagram of each part thereof. be. BT... Power supply, sw3... Start transmission. H, TA2...timing generation circuit, SR3, SR4
゜SR6...Shift register, SW3...Address data setting switch, SW4...Control data setting switch. H, LED, ~L E D 4...Display element * 1
2 3 Figure 10

Claims (1)

[Claims] A transmission signal consisting of a power supply voltage, a main synchronization signal, a sub-synchronization signal, address data, and control data is sent from the receiver, and when the address data and the self-address match, the receiver transmits a transmission signal in response to the control data. A multiplex transmission repeater checker for checking a repeater that controls a terminal device and sends a return signal consisting of monitoring data of the control state of the terminal device to the receiver, the address of the repeater to be checked. an address data setting switch for setting the control data, a control data setting switch for setting the control data, a synchronization signal generation circuit for generating the main synchronization signal and the sub-synchronization signal, and a power supply circuit for generating a power supply voltage for the repeater; A transmission start switch, a first shift register that reads the address data and control data in response to the operation of the transmission start switch, and sends out the data in series as the transmission signal, and monitoring of a reply signal sent from the repeater. A repeater checker for multiplex transmission, comprising a second shift register that reads data while sequentially shifting it and outputs it in parallel, and a display that displays the output of the second shift register.