JPS5916287B2 - Wiring inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring inspection device for a remote-controlled sequence control device, and more particularly to a wiring inspection device that can easily inspect wiring after the sequence control device is installed.

In recent years, as devices have become more complex and larger, the number of input/output points has increased, and the number of wiring between the sequence control device and the input/output points has increased to 10,000.

5. For this reason, stored program type sequence control devices with simplified wiring using time division multiplex transmission are being used.

Generally, after installing this sequence control device, information on each input/output point 0 is displayed in order to check for problems with the sequence, but this is achieved by the sequence control device using time division multiplex transmission. Then,
It will look like Figure 1.

In FIG. 1, reference numeral 1 denotes a central control device, and this central control device 1 has arithmetic control circuits 11 and 5 and a time division control circuit 12, and a signal line 2 is connected from this time division control circuit 12. The time division multiplexed signal is sent to the terminal control device 31 through
It is designed to transmit at a distance of 3m. These terminal systems? Input/output points 311-3mn such as switches, sensors, solenoids, and lamps are connected to the devices 31-3m.

On the other hand, 4 is a timing circuit, and this timing circuit 4 is connected to each input/output point 311 to 3mn via a signal line 2.
It separates the respective timings at which information is transmitted and received, and is connected to the memory circuits 511 to 5mn.

Indicator lamps 611 to 6mn are connected to these memory circuits 511 to 5mn, respectively, and thus the timing circuit 4, the memory circuits 511 to 5mn, and the indicator lamp 61
1 to 6mn constitute an input/output information display device 7.

Next, to explain the operation of the sequence control device shown in FIG.
2 separates the input point information returned as a time division multiplexed signal via the signal line 2 and supplies it to the arithmetic control circuit 11 .

Thereby, the arithmetic control circuit 11 performs logical operations between input point information according to the stored program, and provides output point control information to the time division system circuit 12.

As a result, is the time division system circuit 12 an output point system? The information is converted into a time division multiplexed signal and the time division multiplexed signal is sent to the signal line 2.

On the other hand, the terminal control devices 31 to 3m separate the output point control information transmitted via the signal line 2, and drive the load at the output point according to this information, as well as drive the switches and other devices. The input point information is converted into a time division multiplexed signal and sent to the signal line 2.

Next, to explain the input/output information display device 7, the timing circuit 4 connects each input/output point 311 to 3 via the signal line 2.
The respective timings at which the mn information is transmitted and received are separated and applied to the memory circuits 511 to 5mn.

The storage circuits 511 to 5mn have one-to-one correspondence with each of the input/output points 311 to 3mn, and store information on the signal line 2 at the timing when the above-mentioned input/output point information is transmitted and received.

The information stored in these memory circuits 511-5mn is displayed by display lamps 611-6mn.
Therefore, each of the display lamps 611 to 6mn flashes information about each input/output point 311 to 3mn, so that
Information on each input/output point 311 to 3mn can be confirmed visually.

Now, since the input/output point 311 is a switch as is clear from the figure, the indicator lamp 611 displays the open/closed information of this switch by turning on or off.
Since n is a load, the display lamp 6mn displays drive/stop information of this load by turning on or off.

In this way, information on each input/output point 311-3mn is optically displayed by the display lamps 611-6mn.

By the way, in general, the above-mentioned input/output information display device 7
Sequence system with ? If the sequence is not executed correctly after installing the device, a method is adopted in which the status of each input/output point 311 to 3mn is determined by the input/output report display device 7 and the location of the problem is estimated.

However, although incorrect wiring accounts for a very large proportion of the above-mentioned defective locations, the input/output information display device 7 cannot confirm the wiring, and it takes a long time to discover the defective location caused by incorrect wiring. time is wasted.

Furthermore, since the input/output information display device 7 requires memory circuits and display lamps in a number equal to the number of input/output points,
The problem was that the Ikioi device became larger and more expensive.

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to facilitate inspection of the wiring after the sequence control device with a simple configuration, and to Another object of the present invention is to provide a wiring inspection device that can significantly shorten the time required to discover incorrect wiring, and that can make the entire device small and inexpensive. In order to achieve such an object, the present invention provides a setting device that is configured with a digital switch and sets an address assigned to an input point or an output point in a time division multiplex transmission control section of a central control device, and a setting device that sets an address assigned to an input point or an output point. The input point or output point information of the address set by the setting device is the output of the time division multiplex transmission system and the output of the above time division multiplex transmission system? an address match detection circuit that detects the point of input or output through the controller; a first switch that generates a drive signal for the output point set by the setting device; A second switch that enables transmission of this drive signal when a signal is being generated, the output of the address match detection circuit, and each output of the first and second switches are input, and the logical product of these inputs is take the first
a second AND gate that uses the output of the time division multiplex transmission section and the output of the first switch to logically AND each of these inputs, and the first and second AND gates. and a memory circuit that receives the outputs of the address match detection circuit and the output of the OR gate and stores information on the time division multiplexed signal at the time when the address match detection circuit outputs a match signal. and display means for optically displaying the contents of the memory circuit.

Next, an embodiment of the wiring inspection device of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing only the central control device in one embodiment. ．． Terminal system (goods) device 31 shown in Figure 1
~3mn input/output points 311 to 3mn and the input/output information display device 7 are omitted, or these parts have exactly the same configuration as in FIG. 1 and are connected to the central control device 1. Therefore, the explanation will be omitted.

Now, in this Figure 2, 11 is the same arithmetic control circuit as in Figure 1, and 12 is a time-sharing system? is a circuit, and
13 is the time division monument section.

14 is a test circuit newly added according to the present invention, and this test circuit 14 and the time-sharing feeding control circuit 1
2 constitutes a time division transmission system unit 13. The output of the time division system circuit 12 is sent to an address coincidence detection circuit 15, and the address coincidence detection circuit 15 is connected to input/output points 311 to 3 from a setting device 16.
Address signals corresponding to mn are also being introduced.

As a result, the address match detection circuit 15 compares the output of the time division monument circuit 12 and the address signal, and only when the two match, outputs the "H" level output signal to the AND circuit 1.
7 and a storage circuit 18 .

Further, 19 is a power supply terminal to which a power supply voltage is applied, and this power supply terminal 19 is connected to switches 20 and 21, and both switches 20 and 21 are connected to the output point address set by the setting device 16. The switch 20, which is a switch for generating a drive command, is a switching contact and has a movable contact 201 and two fixed contacts 202 and 203.

The movable contact 201 of this switch 20 is connected to the power terminal 19.
The fixed contact 202 is connected to the second input side of the AND circuit 22, and the fixed contact 203 is connected to the first input side of the AND circuit 17.

The first input side of the AND circuit 22 is the time division control circuit 1
2, the second input side of the AND circuit 17 is connected to the switch 21, and the output sides of both AND circuits 17 and 22 are connected to the first and second input sides of the OR circuit 23. ing.

The output side of this OR circuit 23 is connected to the input side of the signal line 2, the time division control circuit 12, and the memory circuit 18, and the output side of the memory circuit 18 is connected to the display lamp 24.
Next, the operation of the embodiment shown in FIG. 2 will be explained with reference to FIG. The input side becomes "H" level, and at this time, the first input side of the AND circuit 22 is connected to the time-sharing system ? circuit 1
When the output point control signal from 2 is introduced, this signal is introduced to the OR circuit 23 through the AND circuit 22, and further sent to the signal line 2 through the OR circuit 23.

In this state, the central control device 1 operates in the same manner as in FIG.

Next, the movable contact 201 of the switch 20 is connected to the fixed contact 203.
In this state, the fixed contact 202 {the second input side of the AND circuit 22} is switched to “L”.
” level, and the input conditions of the AND circuit 22 are not set.
Therefore, since the output signal of the AND circuit 22 is at the "L" level, the output point control information of the arithmetic control circuit 11 is not sent to the signal line 2.

The time division monument circuit 12 sends an address signal corresponding to each input/output point 311 to 3mn to the address coincidence detection circuit 15 at each point in time when transmitting and receiving signals to each input/output point 311 to 3mn shown in FIG. give.

On the other hand, the footer 16 is constituted by a digital switch, and provides the address coincidence detection circuit 15 with address signals corresponding to the installed input/output points 311 to 3mn.

As a result, the address match detection circuit 15 generates an "H" level output signal when the address signal of the input/output points 311 to 3mn set by the setting device 16 matches the address signal given from the time division control circuit 12. is applied to the third input side of the AND circuit 17, and the memory circuit 18
to be applied.

In this state, if the switch 21 is open, the input conditions for the AND circuit 17 are not set, and therefore the output signal of the AND circuit 17 is at "L" level, and the output signal of the OR circuit 23 is The drive stop signal is sent to all output points.If the switch 21 is open, the address match detection circuit 15 outputs an "H" level output signal. While this is occurring, the output signals of the AND circuit 17 and the OR circuit 23 are at "H" level, and a drive stop signal is sent to the signal line 2 for each output point other than the output point set by the setting device 16. has been done.

In this way, a drive signal can be generated for any output point set by the setting device 16 by closing the switch 21. On the other hand, the storage circuit 18 stores information on the signal line 2 at the time when the address match detection circuit 15 generates an output signal of the "H" level, and causes the display lamp 24 to blink in accordance with the information.

That is, when the switch of the input point set by the setting device 16 is closed, the indicator lamp 24 is lit, and when it is opened, the indicator lamp 24 is lit.
The display lamp 24 is turned off.

Further, when information to drive the output point set by the setting device 16 is being transmitted, the display lamp 24 is lit, and when information to stop the drive is being transmitted, the display lamp 24 is lit.
is lit, and when information to stop driving is being transmitted, the display lamp 24 is turned off. In this way, when the input/output points 311 to 3mn set with the setting device 16 are input points, by manually operating the switch or sensor of the input point and checking that the indicator lamp 24 blinks,
If the input/output points 311 to 3mn set with the setting device 16 are output points, wire the input/output one point at a time by confirming that the load at the output point is driven and stopped by closing and opening the switch 21. It becomes possible to confirm.

As is clear from the above explanation, according to this explanation, the output point set by the setting device can be driven by a switch without using complicated means, and the input point information set by the setting device can be displayed using a display lamp, etc. Wiring can be confirmed with a simple configuration that allows visual confirmation using a suitable display means, making wiring inspection after the sequence control device easier, greatly reducing the time required to discover incorrect wiring, and making it practical. The effect is extremely large. Furthermore, it is extremely effective in that the overall device can be made smaller and cheaper by simplifying the configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional wiring inspection device, and FIG. 2 is a central control diagram of an embodiment of the wiring inspection device of the present invention.
FIG. 3 is a block diagram showing the configuration of parts of the device. DESCRIPTION OF SYMBOLS 1...Central adjustment device, 11...Arithmetic control circuit, 12...Time division needle control circuit, 13...
. . . Time division control unit, 14 . . . Inspection circuit, 15
...Address match detection circuit, 16...
Setting device, 17, 22...AND circuit, 18, 5
11~5mn...Memory circuit, 19...
Power terminal, 2... Signal line, 20, 21...
...Switch, 23...OR circuit, 24,61
1~6m...Indicator lamp, 31~3m...
...Terminal system? Device, 311~3mn... Input/output point, 4... Timing circuit, 7...
Input/output information display device.

Claims (1)

[Claims] 1. A central control device that performs calculations and time-division multiplex transmission control according to stored programs; and a central control device that sends and receives signals in a time-division format to and from the central control device, and transmits information on input points or output points of switches, sensors, etc. to the central control device. In a remote control type sequence control device comprising a terminal control device that sends a reply to a control device and controls a load based on commands from the central control device, the time division multiplex transmission control section of the central control device is configured of a digital switch. to
A setting device for setting an address assigned to an input point or an output point, and input point or output point information of the address set by the setting device, with the output of this setting device and the output of the time division multiplex transmission control unit as inputs. an address coincidence detection circuit that detects when the signal is input or output via the time division multiplex transmission control section; a first switch that generates a drive signal for the output point set by the setting device; 1st
a second switch that enables transmission of the drive signal when the switch is generating the drive signal; a first AND gate that takes the AND of each input; a second AND gate that receives the output of the time division multiplex transmission section and the output of the first switch and takes the AND of each of these inputs; an OR gate which receives the respective outputs of the first and second AND gates; and an OR gate which receives the outputs of the address match detection circuit and the output of the OR gate, and outputs a time division multiplexed signal at the time when the address match detection circuit outputs a match signal. A memory circuit that stores information;
A wiring inspection device comprising display means for optically displaying the contents of the memory circuit.