JPH06141052A - Data transfer method and data reception circuit - Google Patents

Abstract

PURPOSE:To provide a data transfer method capable of transferring data by one signal line in the case of transferring the data from an integrated circuit for control to plural integrated circuits. CONSTITUTION:In this data transfer method, the data, transfer clocks and control signals are sent by connecting the integrated circuit 8 for the control and the plural integrated circuits 9, 10 and 11 by the single signal line 12 and combining three different kinds of voltages on the signal line 12 to be supplied. To do that, one of a first voltage Vcc and a second voltage Vcc/2 is supplied on the signal line based on the respective bit data of the data to be transferred in a first period T1, a third voltage (grounded voltage) is supplied to the signal line in a second period T2 and the first period T1 and the second period T2 are alternately provided on the signal line. Thus, the second period T2 is the transfer clock signal of the data outputted in the first period T1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method for providing necessary data to a plurality of devices and a data receiving circuit for receiving the transferred data.

[0002]

2. Description of the Related Art In recent years, in a system incorporating a plurality of semiconductor integrated circuits, there is a data transfer method for individually transferring data required for each integrated circuit from a control integrated circuit using the same signal line. Has been adopted. Conventionally, the above-described system is configured as shown in FIG. 4, and the control integrated circuit 1 and each integrated circuit 2, 3, 4 are connected by a data line 5, a clock line 6, and a control signal line 7. There is. Here, an address code unique to each integrated circuit 2, 3, 4 is set, and each integrated circuit 2, 3, 4,
When the address added to the transferred data matches the set address, the data is fetched and used.

FIG. 5 shows data transfer in the system of FIG.
3 is a timing diagram of transmission, showing an integrated circuit for control 1
When transferring data, the chip signal is sent to the control signal line 7.
With the enable signal CE output as H level,
Data D on data line 5₀~ D_nAnd address A₀~ A₃The syria
To the transfer clock in synchronization with the output to this data line.
The clock SCK is output to the clock line 6. And the data
D₀~ D_nAnd address A ₀~ A₃When the transfer of
The chip enable signal CE output to the control signal line 7
Set to L level. The rise of this chip enable signal CE
Each integrated circuit 2, 3 and 4 is latched by falling.
Created, and the data transferred by this is addressed to yourself.
Judge whether it is data or not, and collect the data according to the result.
Put in.

As described above, when data is transferred from the control integrated circuit 1, three types of signals, that is, the data, the transfer clock synchronized with the data, and the chip enable signal are required. The signal line of is used. FIG. 6 is a timing chart showing a data transfer method which is an improvement of the data transfer method shown in FIG. 5, and uses two signal lines to transfer data. This method changes the signal output to the data line from the H level to the L level while the transfer clock SCK output to the clock line is at the H level to generate the start signal and the end signal corresponding to the chip enable signal. How to create. That is, as shown in FIG. 6, during the period when the transfer clock is at the H level and the transfer clock is at the H level, the data output to the data line is not changed, and when the transfer clock is at the L level, the data line is Then, when the output of the data is completed, the signal of the data line is changed to the H level while the transfer clock is set to the H level as in the point b. At the point b, the end signal is recognized, and it is determined whether the address of the transferred data matches the address set for itself. If they match, the transferred data is fetched.

According to the data transfer method shown in FIG. 6,
The number of signal lines connecting the control integrated circuit and multiple integrated circuits is 2
You just need a book.

[0006]

As shown in FIGS. 4, 5 and 6, according to the conventional data transfer method, two or three signal lines for transmitting data are required.
There are many wirings that connect the control integrated circuit and the plurality of integrated circuits, and the number of terminals of the integrated circuit is occupied by two or three for data transfer.

[0007]

The present invention was created in view of the above-mentioned points, and a control integrated circuit and a plurality of integrated circuits are connected by a single signal line, and different signals are provided on the signal line. By combining and supplying three different voltages,
A data transfer method for sending data, a transfer clock, and a control signal. In addition, one of the first voltage and the second voltage is output onto one signal line based on each bit data of the data to be transferred in the first period, and the first voltage and the second voltage are output in the second period. By outputting a third voltage lower (or higher) than the second voltage on the signal line and alternately providing the first period and the second period on the signal line, the second voltage
The data transfer method provides a data transfer clock signal for the data output during the first period.
Further, a first level determination circuit that compares the voltage level set between the first voltage and the second voltage with the voltage on the signal line, and the first level determination circuit set between the second voltage and the third voltage. A second level determination circuit that compares the voltage level on the signal line with the voltage level of the signal line, a delay circuit that delays the output of the second level determination circuit, and an output of the first level determination circuit to maintain a predetermined state. A holding circuit that is released by the output of the delay circuit, and a shift register in which an output of the holding circuit is connected to a data input and an output of the second level determination circuit is connected to a clock input, The data corresponding to the first voltage or the second voltage output to the signal line based on each bit data of the data to be transferred during the period is held in the holding circuit, and continues to the first period. In the second period, A signal receiving circuit in which the data of the holding circuit is taken into the shift register by a signal output from the second level determination circuit according to the third voltage output on the line is provided. The line enables data transfer.

[0008]

According to the above-mentioned means, the logical values "0" and "1" of each bit of the data to be transferred are represented by the first voltage and the second voltage output in the first period, and The transfer clock signal is represented by the third voltage output in the second period following the first period. In the device that receives the data transferred by this method, the first level determination circuit determines the first voltage and the second voltage output in the first period, and the logical value is held in the holding circuit according to the determination result. When the third voltage output by the second level determination circuit is determined by the second level determination circuit, the logical value retained in the retention circuit is shifted to the shift register by the output signal. . Furthermore, the holding state of the holding circuit is reset by the output of the delay circuit that delays the output of the second level determination circuit, and the holding of the logical value based on the voltage output during the next first period is prepared. In this way, the data and the transfer clock can be transferred by one signal line.

[0009]

1 is a block diagram showing an embodiment of the present invention, in which a control integrated circuit 8 and a plurality of integrated circuits 9, 10 and 11 for receiving data from the control integrated circuit 8 form one signal. Connected by line 12. When the control integrated circuit 8 transfers data to the plurality of integrated circuits 9, 10, 11, it is performed by supplying three different types of voltages on the signal line 12 in a temporally combined manner.

FIG. 3 shows an embodiment of the present invention for data transfer.
It is a timing chart, which will be described with reference to FIG.
The data transfer in this embodiment is performed by alternately providing the first data.
Period T₁And the second period T₂And after data transfer is completed
The third period T₃Composed of. The first period is
It represents each bit data of the data to be transferred,
The voltage V that is the first voltage_CCAnd the second voltage V_CC
/ 2 is output according to each bit data. That is,
When the logical value of the bit data is "0", the voltage V _CC/ 2
When the selected bit is output and the logical value of the bit data is "1",
Voltage V_CCIs selectively output. Therefore, the voltage on the signal line
V_CCOr V_CCBy determining if it is / 2
Can recognize bit data. First period T₁The second following
Period T₂Output the ground voltage, which is the third voltage.
The transfer clock is represented by and. That is, the voltage on the signal line
Determines that is the ground voltage and creates a transfer clock.
You can This second period T₂Created by
The transfer clock is the first period T immediately before.₁Sent to
It becomes the synchronization clock of the output data. After data transfer is complete
Of the voltage V_CCAnd voltage V_CC/ 2 alternate
It is output twice. This prevents the transfer clock from being detected.
If multiple logical values “1” are detected in
It is recognized as a latch signal.

As described above, by combining and outputting the voltages V _CC , V _CC / 2, and the ground voltage on one signal line, it becomes possible to send data, a transfer clock, and a latch signal. FIG. 2 is a data receiving circuit for receiving the data transferred by the data transfer method shown in FIG. The signal line to which the data is transferred is connected to the input terminal 13, and the input terminal 13 is connected to the inputs of the comparison circuits 14 and 15. The comparison circuit 14 outputs the voltage V _CC /
2 is a circuit for comparing an input voltage with a reference voltage E ₁ set between 2 and V _{CC. When} the input voltage is higher than the reference voltage E ₁ , a power supply voltage level, that is, a logic “1” is output,
When it is smaller, the ground voltage, that is, the logic "0" is output. Therefore, the logical value indicated by the voltage is determined by the voltage output in the first period T ₁ shown in FIG. 1, and the data signal SD is output. On the other hand, the comparison circuit 15 is a circuit for comparing the input voltage with the reference voltage E ₂ set between the voltage V _CC / 2 and the ground voltage, and outputs the ground voltage when the input voltage is higher than the reference voltage. A circuit that outputs a power supply voltage when it is small. Therefore, by outputting the ground voltage in the second period T ₂ shown in FIG. 3A, the transfer clock SC which becomes the power supply voltage in this period is output.
K is output.

The output SD of the comparison circuit 14 is connected to an inverter.
RS flip-flop 1 composed of NAND gates
6 is connected to the set input S and the counter 17
It is connected to the count input CP. This RS flip flop
Rop 16 is in the first period T ₁Bitday output to
For holding the transfer clock SC, which will be described later.
The delay signal DLY of K causes each first period T₁End of
Will be reset later. In addition, the counter 17 also delay signal D
Reset by LY, transfer clock SC
By counting the data signal SD without K
And the third period T₃To judge. In the case of the example,
Output Q of Unta 17₁Is used as the judgment output, so counting
When the value becomes "2", the latch signal LTP is output.
Be done. On the other hand, the transfer clock output from the comparison circuit 15
SCK is applied to the delay circuit 18. Delay circuit 18
Delays the transfer clock SCK,
R is detected as rising edge by detecting rising edge
-Output to S flip-flop 16 and counter 17
It The transfer clock SCK from the comparison circuit 15 is
It is applied to the clock input CP of the shift register 19.

The shift register 19 transfers the data held in the RS flip-flop 14 to the transfer clock SC.
The bits are sequentially shifted based on K, and have a sufficient number of bits to hold the data sent by the data transfer and the address data, and the outputs Q _{0 to} Q _{3 of the} bits holding the address data are Output of bit Q ₄ applied to address coincidence detection circuit 20 and holding data
˜Q _n are applied to the latch circuit 21. The address match detection circuit 20 has an address set for each integrated circuit, and when the address held in the shift register 19 matches the set address, it is latched by the latch circuit 21 based on the latch signal LTP. The clock LCP is output. Specifically, the address match detection circuit 15 selectively applies the outputs Q _{0 to} Q ₃ of the shift register 19 and its inverted signal to the inputs of the AND gates to which the latch signal LTP is applied, thereby individually addressing each address. The data is set. The latch circuit 21 latches the data held in Q _{4 to} Q _n of the shift register 19 when the latch clock LCP is supplied.

The data receiving operation of the data receiving circuit shown in FIG. 2 will be described with reference to the timing chart of FIG. When sending data, first, n-bit data D _{0 to} D _n-1 to be sent to the integrated circuit is sent first, and then 4-bit address data A _{0 to} A ₃ is sent. In the data receiving circuit, the RS flip-flop 16 and the counter 17 are reset by the initial reset signal INT generated when the power is turned on. After that, the data transfer is started, and the voltage output in the first first period T ₁ is determined by the comparison circuit 14. When the voltage of the signal line is V _CC , the output of the comparison circuit 14 sets the RS flip-flop 16,
If it is V _CC / 2, the RS flip-flop 16 remains in the reset state. That is, the logical value "1" is held in the former case, and the logical value "0" is held in the latter case. Then, in the second period T ₂ , the comparison circuit 1
When the transfer clock SCK from 5 rises, the output Q of the RS flip-flop 16 is taken into the shift register 19 and held therein. Further, the RS flip-flop 16 and the counter 17 are reset by the delay signal DLY which is generated slightly after the rise of the transfer clock SCK. Therefore, the RS flip-flop 16 is brought into a state of holding the data output in the next first period T ₁ , and the counter 17 is reset before the count value reaches “2”. The latch signal LTP is never generated.

By repeating the above operation, the transferred data is sequentially shifted to the shift register 19. Then, when the transfer of the address data is completed, the address data is output to the outputs Q _{0 to} Q ₃ of the shift register 19. After the transfer of the address data is completed, in the third period T ₃ , the signal lines are changed to V _CC and V _CC /
2. Change in the order of V _CC . At this time, the comparison circuit 14 sequentially outputs “1”, “0”, and “1”, and the counter 17
Since the count value of 2 becomes "2", the latch signal LTP is generated. When the address set in the address match detection circuit 20 matches the transferred address by the latch signal LTP, a latch pulse LCP is generated, and data is held in the latch circuit 21 at the rising edge of the latch pulse LCP. However, in the case of a mismatch, the latch pulse LCP is not generated, so that the data is not held in the latch circuit 21.

By the above operation, the data output on one signal line is discriminated, and when the addresses match, the transferred data is held.

[0017]

As described above, according to the present invention, it is possible to send data, a transfer clock, and a latch signal on one signal line by combining three different kinds of voltages.
Since only one signal line is required to transfer data from the control integrated circuit to the plurality of integrated circuits, the wiring is simple and the number of terminals of the integrated circuit occupied for data transfer is only one. There are advantages.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a timing diagram illustrating the operation of FIGS. 1 and 2.

FIG. 4 is a system block diagram using a conventional data transfer method.

5 is a timing diagram illustrating the data transfer method shown in FIG.

FIG. 6 is a timing diagram illustrating an improved conventional data transfer method.

[Explanation of symbols]

 13 Input Terminals 14 and 15 Comparison Circuit 16 RS Flip-Flop 17 Counter 18 Delay Circuit 19 Shift Register 20 Address Match Detection Circuit 21 Latch Circuit

Claims (6)

[Claims] 1. A data transfer method for transferring data from a control integrated circuit to a plurality of integrated circuits, wherein the control integrated circuit and the plurality of integrated circuits are connected by a single signal line,
A data transfer method, wherein data, a transfer clock, and a control signal are sent to the signal line by a combination of three different types of voltages. 2. One of a first voltage and a second voltage is supplied to one signal line based on each bit data of data to be transferred in the first period, and the first voltage is supplied in the second period. And a third voltage lower (or higher) than the second voltage on the signal line, and by alternately providing the first period and the second period on the signal line, The data transfer method, wherein the period is a transfer clock signal of the data output in the first period. 3. After transferring data by alternately providing the first period and the second period on the signal line,
3. The data according to claim 2, wherein a third period for alternately supplying the first voltage and the second voltage is provided on the signal line, and the third period serves as a latch signal for the data. Transfer method. 4. A first level determination circuit for comparing a voltage level set between a first voltage and a second voltage with a voltage on a signal line, and between the second voltage and the third voltage. A second level determination circuit that compares the voltage level set on the signal line with the voltage on the signal line; a delay circuit that delays the output of the second level determination circuit; and a predetermined level determined by the output of the first level determination circuit. A holding circuit that holds the state and is released by the output of the delay circuit, and a shift register in which the output of the holding circuit is connected to a data input and the output of the second level determination circuit is connected to a clock input , The data corresponding to the first voltage or the second voltage supplied to the signal line based on each bit data of the data to be transferred in the first period is held in the holding circuit, In the second period following the period The third signal supplied on the signal line
The data receiving circuit, wherein the data of the holding circuit is taken into the shift register by a signal output from the second level determination circuit according to the voltage of. 5. A counter to which the output of the first level judgment circuit is applied and the output of the delay circuit is applied to a reset input, and the data of the shift register by the output when the counter reaches a predetermined number. A latch circuit for holding the shift register is provided, and when a predetermined number of the first voltage and the second voltage are alternately output to the signal line, the data of the shift register is held in the latch circuit. Item 4. The data receiving circuit according to item 4. 6. A detection circuit for detecting that a part of the data taken in the shift register has a predetermined value is provided, and the detection output of the detection circuit and the output when the counter reaches a predetermined number are used. The data receiving circuit according to claim 5, wherein the data of the counter is latched in the latch circuit.