JPH0666468B2 - Output protection circuit - Google Patents
Output protection circuitInfo
- Publication number
- JPH0666468B2 JPH0666468B2 JP56185807A JP18580781A JPH0666468B2 JP H0666468 B2 JPH0666468 B2 JP H0666468B2 JP 56185807 A JP56185807 A JP 56185807A JP 18580781 A JP18580781 A JP 18580781A JP H0666468 B2 JPH0666468 B2 JP H0666468B2
- Authority
- JP
- Japan
- Prior art keywords
- protection circuit
- diffusion layer
- output
- substrate
- output protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims 6
- 239000012535 impurity Substances 0.000 claims 5
- 230000000694 effects Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000005669 field effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】 本発明は出力保護回路に係り、特に絶縁ゲート電界効果
トランジスタ回路による半導体集積回路における出力保
護回路に関する。The present invention relates to an output protection circuit, and more particularly to an output protection circuit in a semiconductor integrated circuit including an insulated gate field effect transistor circuit.
絶縁ゲート電界効果トランジスタによる半導体集積回路
（以下MOS LSIという）の出力端子は、通常第１図に示
すごとく電源電圧Vccと接地GND間に直列に配置されるト
ランジスタM1とM2との接続部Ｘに接続されている。Ｘは
M1,M2のソースあるいはドレインであり、酸化膜によっ
てゲート電極と絶縁されている。The output terminal of a semiconductor integrated circuit (hereinafter referred to as a MOS LSI) using an insulated gate field effect transistor is normally a connecting portion between the transistors M 1 and M 2 which are arranged in series between the power supply voltage Vcc and the ground GND as shown in FIG. It is connected to X. X is
These are sources or drains of M 1 and M 2 , and are insulated from the gate electrode by an oxide film.
ところで、ゲート酸化膜の破壊電圧は約７×106V／cmと
いわれているが、近年MOS LSIにおいてはゲート酸化膜
厚が数100〜1000Å程度であり数10V程度で破壊されるこ
とになる。この破壊はたった一度の過電圧で回復不能と
なる。このようにゲート酸化膜が破壊され、ゲート電極
と基板、あるいはソースドレイン領域とが短絡し、トラ
ンジスタの動作が不能になってしまう。通常MOS LSIに
対し、衣服やプラスチック容器、その他、保存中に発生
する静電気によって高い電圧が加わりやすい。また、誤
って加えられる過電圧もあり、特にMOS LSIの入力端子
においては種々の入力保護回路が設けられている。By the way, it is said that the breakdown voltage of the gate oxide film is about 7 × 10 6 V / cm, but in recent years, the gate oxide film thickness is about several hundred to 1000 Å in a MOS LSI, and it is destroyed at about several tens of V. . This breakdown is irreversible with just one overvoltage. Thus, the gate oxide film is destroyed and the gate electrode and the substrate or the source / drain region are short-circuited, and the operation of the transistor is disabled. Normally, high voltage is easily applied to MOS LSI by clothes, plastic containers, and other static electricity generated during storage. In addition, there is also an overvoltage that is erroneously applied, and various input protection circuits are provided especially at the input terminals of the MOS LSI.
一方、出力端子においても同様に過電圧等に対する保護
は重要であり、正常な動作電圧範囲では電流を流さず、
異常電圧に対しては破壊電圧よりも十分低い電圧で電流
を流してこれをクランプし、更にサージ電圧に対して速
やかに応答する必要がある。第１図は出力端子に上記条
件を満たすものとして、Ｘ点との間に直列抵抗Ｒ及びPN
接合ダイオードD1をそう入した等価回路を示すものであ
り、第２図（ａ）にMOS LSIにおいて実際に実現されて
いるパターンレイアウト例を示す。On the other hand, also in the output terminal, protection against overvoltage is important as well, and current does not flow in the normal operating voltage range.
For an abnormal voltage, it is necessary to pass a current at a voltage sufficiently lower than the breakdown voltage to clamp it, and to respond quickly to a surge voltage. Fig. 1 shows that the output terminal satisfies the above conditions, and the series resistance R and PN between point X and
FIG. 2 shows an equivalent circuit in which the junction diode D1 is inserted, and FIG. 2 (a) shows an example of a pattern layout actually realized in a MOS LSI.
第１図はＮチャネルMOSの例であり、基板に対して負電
圧が加えられるとPN接合ダイオードの順方向特性によっ
てこれをクランプし、正電圧が加えられたときには、ダ
イオードの回復可能なブレークダウンによってこれをク
ランプする。このとき、抵抗Ｒがないと出力端子の異常
電圧をダイオードD1ですべて吸収しなければならないた
め、充分なクランプ効果が得られない。それ故に、抵抗
Ｒを設けこの抵抗Ｒの存在により異常電圧の一部を抵抗
Ｒでもたせ低減させたＸ点の電圧をダイオードD1でクラ
ンプしている。第２図（ａ）は以上の効果を発揮すべく
設計されたパターンレイアウト例であり、第２図（ｂ）
はＡ−Ａ′矢視断面図であり、第２図（ｃ）はＢ−Ｂ′
矢視断面図である。Ｐ型半導体基板１の表面に酸化膜５
を設け、活性領域全体の酸化膜を除去し、ゲート酸化膜
を形成する。６の破線部を開口１、ポリシリコン層3,
3′,3″を設ける。該酸化膜５とポリシリコン層3,3′,
3″をマスクとしてリンを拡散してN+層2,2′を形成す
る。熱酸化により押込みと酸化膜による被覆の後、コン
タクト穴7,7′をホトエッチングにより形成し、最後に
アルミニウム等の配線4,4′,4″,4を行なう。Fig. 1 shows an example of N-channel MOS, which clamps the negative voltage to the substrate by the forward characteristic of the PN junction diode, and recovers the breakdown of the diode when a positive voltage is applied. Clamp this by. At this time, if there is no resistor R, the abnormal voltage at the output terminal must be completely absorbed by the diode D1, and a sufficient clamp effect cannot be obtained. Therefore, a resistor R is provided, and the presence of the resistor R clamps a voltage at the point X, which is caused by causing the resistor R to reduce a part of the abnormal voltage. FIG. 2 (a) is an example of a pattern layout designed to exert the above effects, and FIG. 2 (b)
FIG. 2C is a sectional view taken along the line AA ′, and FIG. 2C is BB ′.
FIG. An oxide film 5 is formed on the surface of the P-type semiconductor substrate 1.
Is provided, the oxide film in the entire active region is removed, and a gate oxide film is formed. 6, the broken line portion is the opening 1, the polysilicon layer 3,
3 ', 3 "are provided. The oxide film 5 and the polysilicon layer 3, 3',
Phosphorus is diffused using 3 "as a mask to form N + layers 2, 2 '. After indentation by thermal oxidation and coating with an oxide film, contact holes 7, 7'are formed by photoetching, and finally aluminum etc. Wirings 4, 4 ′, 4 ″, 4 of FIG.
以上のごとく、第１図のＲ及びD1は第２図の２のN+層に
よってＲが２の側面と基板１との間でD1が形成されたこ
とになる。しかし、第２図（ａ）のパターンレイアウト
例において、出力端子であるが為に、第１図のＲを大き
くすることは、出力レベルの悪化につながり、あまりＲ
を大きくすることは出来ない。すなわち、出力端子には
外部負荷が接続されることからその駆動電流、すなわち
出力端子に流れる電流はかなり大きく、このため抵抗Ｒ
を大きくすると抵抗Ｒでの電圧降下が大きくなり、その
結果として駆動に必要な電圧レベルが得られなくなる。
また、外部負荷は一種の負荷容量でありその容量値が大
きいために駆動に時間を要する。よって、出力端子の保
護においては、抵抗Ｒの抵抗値はある程度に抑え、ダイ
オードD1の面積を大きくしてその電流容量を大きくし異
常電圧の印加による電流をすばやく流出させることが出
力トランジスタの保護効果を大きくすることになる。と
ころが、抵抗Ｒを適当な値に抑えダイオードD1の面積を
大きくすることは、第２図（ａ）において２のN+層の面
積の増大になってしまい、レイアウト上好ましいといえ
ない。As described above, R and D1 in FIG. 1 are formed by the N + layer 2 in FIG. 2 between the side surface of R 2 and the substrate 1. However, in the pattern layout example of FIG. 2A, since it is an output terminal, increasing R in FIG.
Cannot be increased. That is, since an external load is connected to the output terminal, its drive current, that is, the current flowing to the output terminal is considerably large.
When is increased, the voltage drop across the resistor R is increased, and as a result, the voltage level required for driving cannot be obtained.
Further, the external load is a kind of load capacitance and its capacitance value is large, so that it takes time to drive. Therefore, in the protection of the output terminal, the resistance value of the resistor R is suppressed to a certain degree, the area of the diode D1 is increased to increase the current capacity thereof, and the current due to the application of the abnormal voltage is quickly discharged. Will be increased. However, increasing the area of the diode D1 by suppressing the resistance R to an appropriate value increases the area of the N + layer 2 in FIG. 2A, which is not preferable in terms of layout.
本発明はこのような問題を解決した出力保護回路を提供
することにある。The present invention is to provide an output protection circuit that solves such a problem.
本発明の出力保護回路は、出力トランジスタと出力端子
間にそう入させる直列抵抗とPN接合ダイオードにおい
て、直列抵抗の抵抗値を変えないで、PN接合ダイオード
のPN接合面積の増大を計り、実質的なPN接合ダイオード
の大きさを大きくし、本ダイオードによるクランプ効果
を高めたものである。The output protection circuit of the present invention measures the increase in the PN junction area of the PN junction diode without changing the resistance value of the series resistor in the series resistance and the PN junction diode inserted between the output transistor and the output terminal, and substantially The size of the PN junction diode is increased to enhance the clamping effect of this diode.
以下、本発明を図面を参照して説明する。Hereinafter, the present invention will be described with reference to the drawings.
第３図（ａ）は本発明の一実施例を示すパターンレイア
ウトである。製造工程は第２図（ａ）の場合と同一であ
るが、２のN+層の形状が本パターンレイアウト例におい
ては異なる。すなわち、直列抵抗及びPN接合ダイオード
を形成するN+層２の形状をスリットのある形状にする。
第３図（ｂ）に示すＣ−Ｃ′矢視断面図のごとく、第２
図（ｃ）のＢ−Ｂ′矢視断面図と比較して、N+層２が３
つの部分に分離されたことになる。ここで述べるスリッ
トとは第３図（ａ）では矩形を用いているが、円形、だ
円形等N+層の一部を中ぬきにするような形状全てを含ん
だものである。FIG. 3A is a pattern layout showing an embodiment of the present invention. The manufacturing process is the same as in the case of FIG. 2A, but the shape of the N + layer 2 is different in this pattern layout example. That is, the shape of the N + layer 2 forming the series resistance and the PN junction diode is made to have a slit.
As shown in the sectional view taken along the line CC ′ of FIG.
Compared to B-B 'arrow sectional view of FIG. (C), N + layer 2 is 3
It has been separated into two parts. The slit described here uses a rectangular shape in FIG. 3 (a), but includes all shapes such as a circular shape and an elliptical shape that hollow out a part of the N + layer.
本発明によれば、第３図（ａ）のＸ点とＹ点との間に３
つの抵抗領域が並列に接続されたことになり各々の抵抗
領域については従来の抵抗よりも抵抗値が大きくなる
が、その抵抗領域が並列接続されることからＸおよびＹ
点間の全体の抵抗としては要求される従来の抵抗とほぼ
同一の抵抗値をとることになる。一方、ダイオードを構
成するためのPN接合面積としては、基板とN+層側面との
接合面、特に基板表面近傍での接合面積がより大きくな
る。以上のことから、PN接合ダイオードのクランプ効果
及び、直列抵抗分による分圧効果は従来に比べ格段に効
果を増し、出力保護として十分のその効果を発揮すると
共に、出力端子に接続される負荷の駆動能力を確保する
ものである。According to the present invention, there are 3 points between the X point and the Y point in FIG. 3 (a).
Since the two resistance regions are connected in parallel, the resistance value of each resistance region is larger than the conventional resistance, but since the resistance regions are connected in parallel, X and Y
The total resistance between the points will be almost the same as the required conventional resistance. On the other hand, as the PN junction area for forming the diode, the junction area between the substrate and the side surface of the N + layer, particularly in the vicinity of the substrate surface, becomes larger. From the above, the clamping effect of the PN junction diode and the voltage dividing effect due to the series resistance component are much more effective than the conventional ones, and the effect is sufficient as output protection, and the load connected to the output terminal is It is to secure the driving ability.
上記実施例はＰ型基板について説明したがＮ型基板また
は真性半導体基板の場合も同様に実施できる。Although the above-described embodiments have been described with respect to the P-type substrate, the same can be applied to the case of the N-type substrate or the intrinsic semiconductor substrate.
第１図は出力保護回路の等価回路図、第２図（ａ）は従
来の保護回路の場合におけるパターンレイアウト例、第
２図（ｂ）は第２図（ａ）のＡ−Ａ′矢視断面図、第２
図（ｃ）は第２図（ａ）のＢ−Ｂ′矢視断面図、第３図
（ａ）は本発明の実施例のパターンレイアウト、第３図
（ｂ）は第３図（ａ）のＣ−Ｃ′矢視断面図、である。 尚、図において、M1,M2……出力段のトランジスタ、Ｒ
……直列抵抗、D1……PN接合ダイオード、１……Ｐ型半
導体基板、2,2′……N+層、3,3′,3″……ポリシリコン
層、4,4′,4″,4……金属配線、５……酸化膜、６…
…N+層−ポリシリコン層コンタクト、７……金属−ポリ
シリコン層コンタクト、７′……金属−N+層コンタク
ト、である。1 is an equivalent circuit diagram of the output protection circuit, FIG. 2 (a) is a pattern layout example in the case of a conventional protection circuit, and FIG. 2 (b) is a view taken along the line AA 'in FIG. 2 (a). Sectional view, second
FIG. 3C is a sectional view taken along the line BB ′ of FIG. 2A, FIG. 3A is the pattern layout of the embodiment of the present invention, and FIG. 3B is FIG. 3A. 6 is a cross-sectional view taken along the line CC ′ of FIG. In the figure, M 1 , M 2 ... output stage transistors, R
...... Series resistance, D1 ...... PN junction diode, 1 ...... P type semiconductor substrate, 2,2 '...... N + layer, 3,3', 3 "...... Polysilicon layer, 4,4 ', 4" , 4 ... Metal wiring, 5 ... Oxide film, 6 ...
... N + layer-polysilicon layer contact, 7 ... metal-polysilicon layer contact, 7 '... metal-N + layer contact.
Claims (1)
ンジスタと出力端子間にそう入される出力保護回路であ
って、帯状の平面形状を有する逆導電形不純物拡散層に
よって形成される該不純物拡散層の抵抗と該不純物拡散
層と基板との間のPN接合ダイオードとを有し、前記出力
端子に印加される異常電圧に対し前記PN接合ダイオード
の回復可能なブレークダウンにより前記出力トランジス
タを保護する出力保護回路において、該不純物拡散層の
帯状の平面形状内部にスリット部を設け、該スリット部
において前記不純物拡散層の側面と前記半導体基板とが
接触するようにして該拡散層と基板との間のPN接合面積
を大きくしたことを特徴とする出力保護回路。1. An output protection circuit inserted between an output transistor and an output terminal provided on a semiconductor substrate of one conductivity type, wherein the impurity is formed by an opposite conductivity type impurity diffusion layer having a strip-shaped planar shape. A resistance of the diffusion layer and a PN junction diode between the impurity diffusion layer and the substrate are provided, and the output transistor is protected by a recoverable breakdown of the PN junction diode against an abnormal voltage applied to the output terminal. In the output protection circuit, the slit portion is provided inside the strip-shaped planar shape of the impurity diffusion layer, and the side surface of the impurity diffusion layer and the semiconductor substrate are brought into contact with each other in the slit portion so as to connect the diffusion layer and the substrate. An output protection circuit characterized by increasing the PN junction area between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185807A JPH0666468B2 (en) | 1981-11-19 | 1981-11-19 | Output protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185807A JPH0666468B2 (en) | 1981-11-19 | 1981-11-19 | Output protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5886773A JPS5886773A (en) | 1983-05-24 |
| JPH0666468B2 true JPH0666468B2 (en) | 1994-08-24 |
Family
ID=16177227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56185807A Expired - Lifetime JPH0666468B2 (en) | 1981-11-19 | 1981-11-19 | Output protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666468B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0525250Y2 (en) * | 1985-10-08 | 1993-06-25 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52143778A (en) * | 1976-05-25 | 1977-11-30 | Toshiba Corp | Input protection circuit |
| JPS56116658A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor resistance element and manufacture thereof |
-
1981
- 1981-11-19 JP JP56185807A patent/JPH0666468B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52143778A (en) * | 1976-05-25 | 1977-11-30 | Toshiba Corp | Input protection circuit |
| JPS56116658A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor resistance element and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5886773A (en) | 1983-05-24 |
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