JPS5886773A - Output protecting circuit - Google Patents

Abstract

PURPOSE:To obtain a large output protecting effect in an output protecting circuit for an IGFET having a series resistor and a P-N junction diode between an output transistor and an output terminal by increasing the junction area of the diode without varying the resistance value of the resistor. CONSTITUTION:The source and drain of two output stage transistors M1, M2 are connected in series with each other, the drain of the transistor M1 is connected to an electrode voltage Vcc, and the source of the transistor M2 is grounded. The series connecting midpoint of the source and the drain is connected through a series transistor R to an output terminal, one terminal of a P-N junction diode D1 is connected to the midpoint of the resistor R, and the other terminal is grounded, thereby forming an output protecting circuit. In this structure, the shapes of the series resistor and an N<+> type layer 2 for the P-N junction diode formed on a P type semiconductor substrate 1 is constructed to have rectangular, circular elliptical slits. In this manner, the series resistor between the points X and Y is determined as an ordinary value, and the junction area in the vicinity of the surface of the substrate is increased, thereby enhancing the protecting effect.

Description

DETAILED DESCRIPTION OF THE INVENTION The present defense relates to an output protection circuit, with an insulated gate of 1.
This invention relates to an output protection circuit in a semiconductor integrated circuit using a valve effect transistor circuit.

The output terminal of a semiconductor integrated circuit (hereinafter referred to as MO8LSI) using an insulated gate as a valve-effect transistor is usually connected to the junction X between transistors M1 and M2, which are arranged in series between the power supply voltage Vcc and the ground GND, as shown in Figure 1. It is connected. X is the source or drain of Mle M2, and is insulated from the gate electrode by an oxide film.

By the way, the breakdown voltage of the gate oxide film is approximately 7XIO'v/
It is called cIL, but in recent years in MO8LSI, the gate oxide film thickness is about several 100 to 10001.
It will be destroyed by Z at 0 V@degree. This destruction becomes irreversible with just one overvoltage. In this way, the gate oxide film is destroyed, causing a short circuit between the gate electrode and the substrate or source/drain region.

The transistor becomes inoperable. Normal MO8
High voltages are likely to be applied to LSIs due to static electricity generated during storage, such as from clothes or plastic containers.

Also, there is an overvoltage that is applied by mistake, and MO8LS is at 1%.
Various input protection circuits are provided at the input terminal of I.

On the other hand, the output terminals are also protected against overvoltage, etc.
is important; in the normal operating voltage range, vLIN is allowed to flow; for abnormal voltages, current is passed at a voltage that is sufficiently lower than the breakdown voltage, and this is re-amplified.

Furthermore, it is necessary to quickly respond to surge voltage.

Figure 1 shows an equal number of circuits in which a series resistor R and a PN junction diode DI are connected between the output terminal and the point X, as the output terminal satisfies the above conditions.
An example of a pattern layout actually realized in S LSI? show.

Figure 1 shows an example of an N-channel MO8, in which when a negative voltage is applied to the substrate, the forward characteristic of the PN junction diode clamps it, and when a positive voltage is applied, the diode recoverable breakdown occurs. This is cranked by using the voltage divider effect created by the series resistor to further increase the cranking effect. Figure 2 (31 is an example of a pattern layout designed to achieve the above effect; It is a cross-sectional view of a P-type semiconductor substrate l.
BIAn oxide is provided on the surface of the active region, the oxide film over the entire active region is removed, and the entire gate oxide film is formed. 6 broken line partial opening 11
A polysilicon layer 3.3', 3 is provided. Using the oxide film 5 and polysilicon layers 3.3', 3' as masks, phosphorus is diffused to form N+ layers 2, 2'. After pressing in by thermal oxidation and covering with an oxide film, contact holes 7, 7' are formed by photoetching, and finally wiring 4.4', 4"4/// of aluminum or the like is formed.

As described above, DI is formed between R and DI in FIG. 1 and the substrate 1 by the soil layer 2 in FIG. 2. However, in the pattern layout example of FIG. 2(a), since it is an output terminal, R of FIG.
, f increases leads to deterioration of the output level,
It is not possible to increase the sweet Rf. Therefore, in protecting the output terminal, it is highly effective to make Kl' thicker, but keep Kl to an appropriate value and Dlff
Increasing i results in an increase in the area of the soil layer 2 in FIG. 2(a), which is not desirable in terms of layout.

The object of the present invention is to provide an output pupil keeping circuit that solves all of these problems.

In the output protection circuit of the present invention, the PN junction area of the PN junction diode is increased tdt without changing the resistance value of the series resistor in the series resistor and PN junction diode placed between the output transistor and the output terminal. The actual size of the PN junction diode is large, and the Clantz effect due to a single diode is fully enhanced, as is the voltage dividing effect due to the multilayer resistor.

Hereinafter, the present invention will be explained with reference to the drawings.

8443Is Figure (a) an embodiment of the present invention? This is the pattern layout shown. The manufacturing process is the same as in the case of AT, but the shape of the 2ON 10 layers is different in this pattern layout example. In other words, the shape of 1 layer 2 that forms all the series resistors and PN junction diodes, and the shape with slits. As shown in the C-C/arrow cross-sectional view shown in Figure 3(b), compared with the B-B' arrow cross-sectional view in Figure 2 (cl),
This means that N''/12 has been separated into three parts.The slit described here is shown in Figure 3 (Al uses a rectangular shape in al, but it is a slit in which a part of the N+ layer is hollowed out, such as a circular or oval shape. It includes all such shapes.

According to the present invention, even though the series resistance between point X and point Y in FIG. The bonding area with the substrate, especially near the substrate surface, becomes larger.

From the above, the crank effect of the PN junction diode and the voltage dividing effect of the %11 series resistor are much more effective than in the past, and are fully effective in maintaining the output.

Although the above embodiments have been described with respect to a P-type substrate, the same can be applied to an N-type substrate or an intrinsic semiconductor substrate.

[Brief explanation of the drawing]

Figure 1 is an equal-part schematic diagram of the output protection circuit, Figure 2 (a) is an example of the pattern layout for a conventional protection circuit, and Figure 2 (b) is the same pattern as in Figure 2 (a). A-A' arrow sectional view,
Figure 2 (cl) Figure 2 (at (D This is shown in the cross-sectional view taken along the line C-C'.In Figure 1, Ml, M2...output stage transistors, R...series resistance, D...P
N-junction diode, l...P-type semiconductor substrate,
2, 2'...N ten bites =, 3.3', 3"...
...Polysilicon layer, 4,4.4'. 4″...Metal wiring, 5...Oxide film, 6
・・・・・・N+ layer-polysilicon layer contact, 7.
...Metal-polysilicon layer contact, 7'...
... Gold M-N" 7m contact. No. ZX (b)

Claims (1)

[Claims] The resistance of the impurity diffusion layer formed by the opposite conductivity type impurity diffusion layer and the side surface of the impurity diffusion layer and the substrate are In an output protection circuit using a PN junction diode between the layers, an arbitrary slit is provided in the impurity diffusion layer to increase the PN junction between the side surface of the diffusion layer and the substrate without changing the value of the resistance. An output protection circuit characterized by: