JPH0664555B2 - Bus control method in information processing device - Google Patents

Description

DETAILED DESCRIPTION [Overview] The present invention is configured to communicate with the outside using a data bus, operate according to a start / stop instruction from the outside, and read or write any register from the outside. In the bus control method of the information processing device, in order to solve the problem that the processor cannot be controlled when the data bus fails, by providing a control data bus in addition to the normal general data bus, the general data bus fails, for example. Even so, the control data bus is used to access the control register from the outside to control the processor.

[Industrial application field]

The present invention relates to a bus control system in an information processing device provided with a control data bus in addition to a normal data bus.

[Conventional technology]

Generally, the access from the outside to the processor specifies the address of the register provided in the processor,
Data to be read / written is exchanged with the outside via a data bus provided in the processor. A brief description will be given below with reference to FIG.

In FIG. 2, a processor (information processing device) 11 performs various arithmetic processes. The general registers 1 to M provided in the processor 11 are registers (for example, WB, RB, WR, etc.) necessary for executing instructions, and the control registers 1 to N are start instructions, masks for the processor,
It holds and controls status information and the like. In order to access these general registers 1 to M and control registers 1 to N, a register address is supplied from the outside to the decoder 14 to be decoded and one of them is selected, and at the same time from the outside via the data bus 12. Predetermined data is written or read out to the outside via the data bus 12.

The RUN mode in the figure is a mode when the processor 11 is performing normal processing. The TEST mode is
The debug register 16 is connected to the control register 1 via the data bus 12 to transfer predetermined data from the keyboard 17-2.
To N or the general registers 1 to M, or the mode is a mode in which the processor 11 is debugged by reading or reading and displaying on the display 17-1.

[Problems to be solved by the invention]

As shown in FIG. 2, the data bus in the conventional information processing apparatus communicates with the outside through the common data bus 12 for both the control registers 1 to N and the general registers 1 to M. When some trouble occurs in the data bus 12, for example, when a part of the data bus 12 is disconnected, or when the enable of the data bus 12 is abnormally operated due to a runaway of a microprogram, the data bus 12 is externally used. Therefore, since the control registers 1 to N cannot be accessed, the control becomes completely impossible. In particular, the processor is LS
When converted to I, set the probe of the measuring instrument to the control register 1
There is also a problem that debugging cannot be performed because the internal state cannot be read by directly connecting to the N terminal or the like.

[Means for solving problems]

According to the present invention, in order to solve the above problems, a control data bus is provided independently of the general data bus normally used.

Means for solving the problem will be described with reference to FIG.

In FIG. 1, a general data bus 2 is used to write data to the general registers 1 to M from the outside or send data read from the general registers 1 to M to the outside.

The control data bus 3 writes data to the control registers 1 to N from the outside or sends data read from the control registers 1 to N to the outside.

The decoder 4 decodes the register address supplied from the outside and makes the corresponding register accessible.

[Action]

 Next, the operation will be described.

In FIG. 1, even if the general data bus 2 becomes unusable due to some trouble, by accessing the control registers 1 to N from the outside through an independently provided control data bus 3, the processor 1 It becomes possible to control.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be described in detail with reference to FIG.

In FIG. 1, a general data bus 2 is used to write data to the general registers 1 to M from the outside and to send data read from the general registers 1 to M to the outside. The data width of the general data bus 2 is wide.

The control data bus 3 is used to write data to the control registers 1 to N from the outside and to send the data read from the control registers 1 to N to the outside. The data width of this may be narrow. In particular, when the number of pins is limited in an LSI, the control data bus 3 itself does not significantly affect the performance of the processor 1.
The number of pins may be reduced by configuring the access so as to be divided into several times.

The decoder 4 decodes the register address notified from the outside and writes the data to any one of the registers via the general data bus 2 or the control data bus 3, or reads from any one of the registers. Multiplexer data, 3 state buffer and general data bus 2 or control data bus 3
It is sent to the outside via the. The general enable signal or the control enable signal supplied to the 3-state buffer at the time of reading is generated by decoding the value stored in the general register 1 as shown by the dotted line in the figure, or by the control register 1
The value of the predetermined bit of may be used.

Next, the operation will be described.

During normal processing, communication is performed between the outside and the general registers 1 to M via the general data bus 2, and predetermined processing is executed. When performing interrupt processing, etc., the control register 1 and the outside are connected via the control data bus 3.
Through N (writing to a control register for mask control of predetermined mask data, etc.).

In this state, the general data bus 2 can be used for some reason, for example, when a part of the general data bus 2 is disconnected, or when the enable signal is held in the active state due to a runaway microprogram. Even if it disappears, the control data bus 3 is provided independently
It is possible to control the processor 1 by independently accessing the control registers 1 to N via.

As described above, even if the control data bus 3 is newly provided in addition to the general data bus 2, since the width of the control data bus 3 is narrower than the width of the general data bus 2, the LSI pin The rate of increasing the number is small. Moreover, the register address for selecting the control registers 1 to N is the same as the conventional register address shown in FIG.
The number of bus enable circuits also does not increase. Furthermore,
When the number of pins of the LSI is limited, the number of pins may be reduced by accessing the LSI several times.

〔The invention's effect〕

As described above, according to the present invention, since the control data bus is provided separately from the ordinary general data bus, even if the general data bus fails due to some cause, for example. The processor can be controlled by accessing the control register from the outside by using an independently provided control data bus. Therefore, the reliability of the control of the processor can be improved and the debugging can be efficiently performed.

[Brief description of drawings]

FIG. 1 shows a block diagram of one embodiment of the present invention, and FIG. 2 shows a block diagram of a conventional system. In the figure, 1 is a processor (information processing device), 2 is a general data bus, 3 is a control data bus, and 4 is a decoder.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroshi Kamisaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenichi Abo, 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kazuyasu Nonomura, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor, Ryo-shi Nishimachi, 1015, Uedanaka, Nakahara-ku, Kawasaki, Kanagawa, Japan (72) Inventor, Sakurai Yasuchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (1)

[Claims] 1. A bus control system in an information processing device, which is configured to communicate with the outside using a data bus, operate according to a start / stop instruction from the outside, and read / write an arbitrary register from the outside, In addition to the general data bus (2) for reading and writing to the general registers (1) to (M), the control register (1)
Or (N) is equipped with a control data bus (3) for reading and writing independently, and the information is characterized by being configured so that the processor can be externally controlled using this control data bus (3). Bus control method in processor.