JPH066240A - Frequency-divider circuit and serial/parallel conversion circuit using the same - Google Patents

Abstract

PURPOSE:To shift the phase of the frequency-division output of a signal equivalent to a high speed bit rate only in the desired number of clocks by the addition of a simple circuit, with respect to a frequency-divider circuit in which plural frequency- dividing means are connected in cascade and a serial/parallel conversion circuit using the pertinent frequency-divider circuit. CONSTITUTION:This circuit is equipped with inverting means 2a-2c at each stage which input the output of each frequency-divider circuit 1a-1c, and whose inverting functions are controlled by a shift amount control signal, and each phase varying means 4a and 4b which inputs the outputs of the inverting means 2b and 2c after the second stage, and which generates each frequency-division clock phase-controlled by each driving signal. The output of the inverting means 2a at the first stage is supplied as the driving signal of the phase varying means 4a at the second stage, and afterwards the output of the phase varying means at the (n)th stage is supplied as the driving signal of the inverting means at the (n+1)th stage. The shift amount control signal corresponding to desired shift amounts is supplied to the inverting means at each stage, and the phase of each frequency-division clock generated from output of the inverting means at the first stage and the output of each phase varying means is shifted only by the desired shift amounts.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit and a serial-parallel conversion circuit using the frequency dividing circuit. In recent years, the multiplicity of signals has increased as the transmission capacity of transmission lines such as optical fibers has increased. In addition, wideband ISDN is also used in CCITT.
In order to comply with the standard, the synchronous digital hierarchy (SD
H: Synchronous Digital Hierarchy) has been standardized as a synchronous interface with a new multiplexing method. This SDH also includes a multiplexed signal with an extremely high bit rate, and in order to process such a high-speed multiplexed signal, it is converted into a plurality of channel signals by demultiplexing to be a low-speed signal. Therefore, a serial-parallel conversion circuit that performs demultiplexing at high speed is required.

[0002]

2. Description of the Related Art In order to separate a multiplexed signal and process a header and data contained in the signal, it is necessary to output each separated signal to a predetermined channel. Therefore, it is necessary to check the contents of the signal to establish frame synchronization and output the separated signals to each channel in order. The synchronization is detected by detecting the synchronization pattern of the frame, and each channel is normally separated. When the frame synchronization pattern cannot be detected, the frame synchronization loss is detected. However, the signal transmission rate of the optical communication system used in the trunk line system is very high, and for example, 2.4 G [b
ps] (giga bits per second). It is difficult to establish frame synchronization for such a high speed signal without channel separation.

Therefore, a structure is adopted in which the signals are separated from each other by a serial / parallel conversion circuit without synchronizing the frames, a frame is detected for a signal having a slow transmission speed, the signals are exchanged, and each signal is output to a predetermined channel. I am taking it. There are roughly (1) and (2) methods to realize this. (1) The separation detection information is fed back to the separation circuit, and the separation circuit shifts each output channel. This method can be further divided into the following.

When shifting a channel, the separation circuit inhibits the input clock for 1 bit and shifts the channel by 1 bit. When shifting a channel, the channel is shifted by resetting the separation circuit and releasing the reset at an appropriate time. When shifting the channel, the channel is shifted by inverting the state of the frequency divider circuit in the separation circuit. This multiplexed signal separation circuit (serial / parallel conversion circuit) is shown in FIG. 14, and its configuration and operation will be described later.

(2) A channel switching circuit is connected after the frame synchronization detecting circuit, and when the loss of frame synchronization is detected, the channel switching is performed using the information. The method of (1) above must generate a single-shot pulse signal or step signal with rise and fall times that are similar to the input clock to the separation circuit. Moreover, since these signals must be input in synchronization with the state of the separation circuit, a complicated circuit and delicate timing setting are required. That is, there is a problem in that the pulse signal (similar to the clock signal) used in this case has a speed of GHz (gigahertz).

Further, the method (2) has a drawback that the circuit scale becomes large although a high-speed circuit is not required.
FIG. 14 shows a block diagram of a conventional example using the above method.
A timing chart with the configuration of FIG. 14 is shown in FIG. In FIG. 14, D-FF1 to D-FF14 are D-type flip-flops, T-FF1 to T-FF3 are T-type flip-flops, DL1 to DL8 are delay circuits, and INV is an inverting circuit. T / 2, T, 2
T and 4T are each 1/2 the cycle T of the clock signal
It means delaying by the time of one cycle, one cycle, two cycles, and four cycles.

A timing chart of the signals a to s of each part shown in the circuit of FIG. 14 is shown in FIG. 15, and the operation will be described below with reference to the example shown in FIG. A frequency divider circuit composed of T-FF1, DL8, T-FF2, and T-FF3 surrounded by a dotted line is provided on the lower side of FIG. 14, and each circuit provided on the upper side of the frequency-divided signal of each channel from the multiplexed signal. A separation circuit for separating signals is configured.

The clock input b supplied to the frequency dividing circuit is divided in half by the T-FF1 in the first stage, and a half clock time (T / T) is set so that it rises at the center position of each signal of the data input a.
2) Delay and generate signal c. This signal c is further divided by the next T-FF2 to generate a signal f having a cycle of 1/4 of the clock, and further divided by the next T-FF3 to generate a signal k having a cycle of 1/8 of the clock. To do.

A binary input signal (... n, n + 1, n + 2, ...) that has been multiplexed (in this example, 8 channels) is input to the separation circuit in series to the data input a. It is supplied to D-FF1 and D-FF2. The data input signal is alternately extracted and held in the D-FF1 and D-FF2 by the output signal c of the DL8 and the signal obtained by inverting the phase of the signal c by INV.
And the output signal e of the D-FF2 is generated as shown in FIG. The signal d is then D-FF3, D-FF4
And the signal e is supplied to D-FF5 and D-FF6.

D-FF3 and D-FF5 are extracted by the signal f from the T-FF2, D-FF4 and D-FF6 are extracted by the phase inversion output of the signal f, and D-FF3 and D-FF are extracted.
The signal of FF5 is delayed by two cycles in DL2 and DL3, respectively, and signals g and i are generated.
Signals h and j are generated from FF6. This signal g, h,
As shown in FIG. 15, i and j are outputs in which each signal of the data input is sequentially held for four cycles, and the data input is serial-parallel converted into four outputs.

Next, each of the signals g to j is supplied to two D-FFs in the subsequent stage, as shown in FIG. Each DF
D-FF7, D-FF9, D in F7 to D-FF14
The -FF11 and D-FF13 are driven by the output signal k of the T-FF3 of the frequency dividing circuit to extract the signals g, h, i and j, and pass through the delay circuits DL4 to DL7 of 4T, respectively.
Signals l, n, p, to the output terminals A, C, B, D of the separation circuit
generate r. In addition, D-FF8, D-FF10, D-
The FF12 and D-FF14 are driven by the phase inversion signal of the output signal k of the T-FF3 of the frequency dividing circuit to generate signals g, h,
i, j are extracted and signals m, o, q, s are generated at the output terminals E, G, F, H of the separation circuit.

The output signals 1 to s are obtained by serial-parallel converting the signal of the data input a into eight signals as shown in FIG. 15, and the data signals generated every eight clocks in each output signal. Is extracted and held for 8 clocks. And the output terminals A, B, C, D, E, F, G, H
Of the data signals that occur in (1, l, p ...
-Q, o, s) is n-4, n-3, n-2 ... n +
As is clear from 2, n + 3, the input data sequentially generate channel signals whose phases differ by one clock.

When loss of synchronism is detected in the configuration of FIG. 14, the channel is shifted by inverting the state of the frequency dividing circuit.

[0014]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
According to the conventional example described in 1 above, when the state of the frequency dividing circuit is inverted, if the inversion is performed asynchronously with the frequency dividing circuit, the state of the frequency division subsequent to the next stage becomes uncertain, so the channel shift There is a problem that the amount cannot be determined. Explaining the reason for this, it is assumed that the data of channels 1, 2 ... 8 are output to the output terminals A, B, C ... H, respectively. Here, when the output signal k of the T-FF3 of the frequency dividing circuit is inverted,
Signals l (el) and m, signals n and o, signals p and q, signal r
And s are exchanged, and the data of channels 5, 6, 7, 8, 8, 1, 2, 3, 4 are output to the output terminals A, B, C, ... H, and are shifted by 4 bits from the state before that. be able to. Next, considering the case where the output signal f of the T-FF2 of the frequency dividing circuit is inverted, the signals g and h and the signals i and j are interchanged as in the above case, but the signal f before the inversion is "H". ”
TF depending on (high level) or "L" (low level)
Since the state of F3 is different, it cannot be determined which channel of data is output to the output terminals A to H.

Of the outputs of T-FF2, D-FF3
If only the signal going to D-FF6 is inverted, the indeterminacy of the state of T-FF3 disappears, but D-FF7 to D-FF14
The phase relationship between the data and the clock changes, and it will not operate normally. In addition, if an attempt is made to invert in synchronization with the frequency dividing circuit, there is the problem that a complicated circuit is required as in (1) above.

The present invention uses a frequency dividing circuit and a frequency dividing circuit that can shift only an arbitrary channel without adding a simple circuit to a high-speed channel switching speed corresponding to the bit rate, eliminating uncertainties in the frequency dividing state. An object is to provide a serial-parallel conversion circuit.

[0017]

[Means for Solving the Problems] In order for the serial-parallel conversion circuit to operate normally and to shift only an arbitrary channel, the following conditions must be satisfied. The phase relationship between the divided clocks does not change. All divided clocks nT at the same time for input data
Be able to shift by (n: integer from 0 to N-1, T: cycle of input data).

This can be considered to be the same as the case where the data is shifted with respect to the clock in FIG. For example, when the data is delayed by 3 bits, n, n + 1, n + 2 ...
, And the channel is shifted by 3 bits. The present invention makes it possible to specify an arbitrary channel shift amount by constructing the signal generated from the frequency dividing circuit so as to satisfy the above conditions and supplying it to the separation circuit.

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1a, 1b, 1c ... Are frequency dividing means for performing frequency division by 2, and 2a, 2b, 2c ... Are control signals 5a, 5
b, 5c ... Inverting means for controlling whether or not the inversion operation is performed, 3 is a delaying means for delaying by a half cycle of the clock, 4a is a signal of the inverting means 2b depending on the phase of the output signal of the delaying means 3. Phase variable means 4b for extracting and outputting, phase variable means 4b for extracting and outputting the signal of the inverting means 2c according to the phase of the output signal of the preceding phase variable means 4a, and 5 for each inversion corresponding to the desired shift amount. Means 2a, 2b, 2c
.. is a shift amount control unit for generating a control signal. In this configuration, the frequency dividing means 1a, 1b, 1c, ... Are provided in N stages, and each frequency division output signal obtained by this configuration can be used to separate the multiplexed signal into 1: 2 ^N.

Next, the second invention will be described. Figure 2 is the second
2 is a principle configuration diagram of the invention of FIG. In FIG. 2, 1a is a frequency dividing means for performing a frequency division by 2, 1b, 1c, ... are frequency dividing means for outputting a main output divided by 2 and a sub output obtained by shifting the phase by a half cycle, 7a, 7b, 7c. ... is frequency dividing means 1
a, 1b, 1c ...
Selection means 4a for selecting by the control signals 5a, 5b, 5c, ... And outputting as a divided clock of each stage is a selection means 7b.
The phase variable means for extracting and outputting the signal of No. 2 according to the phase of the signal of the inverting means 2b, and other symbols are the same as above. It should be noted that the multiplexed signal can be separated into 1 to 2 ^N by using each frequency-divided output signal obtained by this configuration.

The third invention will be described. FIG. 3 is a block diagram showing the principle of the third invention. In FIG. 3, 1 is a frequency dividing means for performing frequency division by 2, and 6a, 6b ... are respectively 2 ^N-1 different deviations in which the phase is shifted by the period T of 2 ^N times the period T of the reference clock. Different phase clock generation means for generating phase clocks, 7a, 7b, 7c ...
2 from a, 1b, 1c ...
^{One of the N-1} different phase clocks is used as the control signal 5a, 5
Selection means for selecting by b, 5c ... And outputting as a divided clock of each stage, other symbols are the same as above. The multiplexed signal can be separated into 1 to 2 ^N even by using each frequency-divided output signal obtained by this configuration.

[0022]

First, in the invention shown in FIG. 1, when the clock signal is supplied to the frequency dividing means 1a in the first stage, its frequency division output is supplied to the frequency dividing means 1b in the next stage and the inverting means 2a. It The frequency dividing means 1b further divides the output of the frequency dividing means 1a into two, the output thereof is supplied to the inverting means 2b and the frequency dividing means 1c of the next stage, and the output thereof is the inverting means 2.
In addition to being supplied to c, it is also supplied to a frequency dividing means at a subsequent stage (not shown), and thereafter is supplied to a similar circuit at the subsequent stage.

Each of the inverting means 2a, 2b, 2c ... Has a control signal 5a, 5b, 5c ... "1", "0" set corresponding to the shift amount set in the shift amount control section 5. "Invert or pass it as it is.
With this configuration, the output signal of the frequency dividing means 1a is inverted by the inverting means 2a.
The output is changed at the central position of the data signal by inverting or passing through and being supplied to the delay means 3 and being delayed by a half cycle of the clock signal. Further, since the output signal controls the operation of the phase varying means 4a of the output signal of the inverting means 2b in the subsequent stage, the operation of the separation circuit (corresponding extraction circuit of FIG. 15) by the output signal of the phase varying means 4a is determined. be able to. Further, the phase varying means 4a to which the signal generated by the frequency dividing means 1b passes through the inverting means 2b is inputted, and the phase varying means 4a generates a signal having a phase having a fixed relationship with the phase of the output signal of the frequency dividing means 1a. You can

The signal generated by the frequency dividing means 1c through the inverting means 2c is supplied to the phase varying means 4b, or the phase varying means 4b outputs an output signal whose phase is adjusted by the output of the phase varying means 4a. Occurs. Similarly, the frequency dividing means at the subsequent stage operates in the same manner. For example, when shifting only one clock, the shift amount control unit 5 controls the control signal 5a.
, And the other control signals 5b, 5c ... Are generated as "0". In this case, only the inverting means 2a performs the inverting operation, and the signal is delayed by the delay means 3 to drive the phase varying means 4a, and the frequency dividing circuit 1 in the subsequent stage is driven.
The outputs of b and 1c are not driven by the inverting means 2b and 2c, the phase of the output signal of the delay means 3 is adjusted, and the phase varying means 4 is supplied.
Output signals are generated from a and 4b. Therefore, the frequency dividing output signals 1/2, 1 for generating the channel signals obtained by shifting the separation circuit by one clock from the original signal are output from the delay means 3, the phase varying means 4a, and the phase varying means 4b.
Outputs of / 4, 1/8, 1/16 ...

When shifting only two clocks,
Only the reversing means 2b is reversed from the shift amount control section 5,
The inverting means 2a, 2c, ... Supply a non-inverting control signal. Further, in the case of shifting by 3 clocks, the inverting means 2a and 2b are inverted and the other control signals are non-inverted, and other shift amounts can be realized by the same principle.

Next, the second invention shown in FIG. 2 will be described. FIG. 2 shows each frequency dividing means in the first invention shown in FIG.
According to the configuration as described above, the serial-parallel conversion circuit operates normally, the above conditions and conditions for shifting only an arbitrary channel are satisfied, and the following action is obtained. That is,
The operating speed of the frequency dividing means other than the first stage is f / 2 [bps] or less (f: the speed of the input data), and the frequency division of each stage is extremely simple and the phase margin is improved. With this configuration, high speed operation can be supported.

Next, the third invention shown in FIG. 3 will be described. FIG. 3 shows each frequency dividing means in the first invention shown in FIG.
With such a configuration, the serial-parallel conversion circuit operates normally, the above conditions and conditions for shifting only an arbitrary channel are satisfied, and the following actions are obtained. That is, in the configuration as shown in FIG. 3, the operating speed of the frequency dividing means other than the first stage is f / 2 [bps], and the phase adjustment is not necessary due to the configuration in which the different phased clocks of each stage are selected. ,
Can support high-speed operation.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment of Frequency Dividing Circuit FIG. 4 is a block diagram of an embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing operation waveforms of respective parts corresponding to respective shift amounts (part 1). ),
(Part 2). The embodiment of FIG. 4 shows an example of a frequency dividing circuit in which a circuit for performing frequency division by 2 has three stages.
It can be used as a frequency dividing circuit surrounded by a dotted line. That is, in the configuration of FIG.
This corresponds to the case where (N ≧ 2) is 3, and can be used in the case of performing the separation of 1: 2 ^N from the multiplexed signal, that is, 1: 8 by the frequency division output.

Reference numerals 20a to 20c in FIG. 4 are T-type flip-flops (T-FFs) corresponding to the frequency dividing means (1a, 1b, 1c) in FIG. 1, and 21a to 21c are inverting means (2 in FIG. 1).
a, 2b, 2c) and an exclusive OR circuit (EXOR), 2 for performing a logical operation of an exclusive OR of the shift amount control signals s0, s1, s2 and the respective input signals.
2 corresponds to the delay means 3 in FIG. 1, and the delay circuits (DL) 23a, 23b having a clock half-cycle time delay function correspond to the D-type flip-flops (4a, 4b) in FIG. D-FF).

In the configuration of FIG. 4, D-FFs 23a, 2
3b and T-FFs 20a to 20c are composed of individual ICs and use a delay circuit 22 to delay a signal.
It can also be delayed by a cable or D-FF. The operation waveform of each unit corresponding to each shift amount using the configuration of FIG. 4 will be described with reference to FIGS. 5 and 6. Each symbol b, t, u, v, w, x, y, c, f, k shown in FIGS. 5 and 6 represents a signal represented by the same symbol output from each circuit of FIG. 4, b is a clock input, t is the output signal of the T-FF 20a, u is T-F
F20b output signal, v is T-FF20c output signal, w to y are EXOR21a to EXOR21c output signals, c is DL22 output signal, and f and k are D-FF23.
a and 23b are output signals, and these signals c, f, and k are frequency-divided output signals of the same sign shown in FIG. 14 and are supplied to respective parts of the separation circuit (serial / parallel conversion circuit) of FIG. Is output.

5 and 6, (1) is an output signal of each T-FF corresponding to the clock input of FIG. 4, (2) to
(9) is 0, 1, 2, 3 ...
The signal waveforms when each value of 7 (corresponding to the number of clock pulses) is set. As shown in (1) of FIG. 5, the clock input b is divided by 2 in the T-FF 20a, and its output signal t is further supplied to the T-FF 20b to be divided by 2 to generate an output signal u. -FF20c
, And the signal v is obtained from its output. Shift control of the separation operation in the separation circuit (the upper circuit excluding the frequency divider circuit in FIG. 14) using this frequency divider circuit can be performed by adjusting the values of the shift amount control signals s0, s1, and s2. it can.

When the shift amount is 0, the value of the shift amount control signal {s2, s1, s0} shown in (2) of FIG. 5 is "0" (= {0, 0, 0). }). In this case, the output signal t of each circuit of (1) above,
u and v are not inverted in the EXORs 21a to 21c and are output as the signals w, x and y as they are, and the signal w is DL2.
2, the signal c is delayed by a half clock period, the rising edge of the signal x holds the signal x in the D-FF 23a, and the rising edge of the signal f holds the output signal y in the D-FF 23b. . In this case,
As shown in (2), the signals c, f, and k rise at the same time within the first clock period of the signal w, and the separation circuit does not shift them.

Next, the case where the shift amount is 1 (one clock) is shown in (3) of FIG. In this case, each shift control signal is set to {s2, s1, s0} = {0, 0, 1}. That is, only the control signal s0 is set to "1" and the EXOR
The inversion operation is performed only for 21a. As a result, the signal w is inverted and generated from the DL 22 as shown in FIG.
The phase of the signal waveforms of f and k is 1 as compared with the case of the shift amount of 0 shown in (2) above, as is clear from the relationship between the timings at which these three signals rise (indicated by the upward arrows).
It is offset by the clock. As a result, the divided outputs c, f,
k can shift the entire phase by a designated 1 bit without changing the mutual phase.

FIG. 5D shows the case where the shift amount is 2. Shift amount control signal at this time {s2, s1, s0}
= {0,1,0}, the phase is inverted only by the EXOR 21b to generate the signal x, and the output signals c, f, k are (4)
As shown in (4), the signals t, u, and v when the shift amount is 0 rises all together at a timing shifted by two clocks (at a time point indicated by an upward arrow). When the shift amount is 3, as shown in (5) of FIG. 5, the shift control signals {s2, s
1, s0} = {0, 1, 1}, and EXOR 21a, 2
1b is reversed. In this case, can be shifted by 3 clocks as indicated by the upward arrow.

Similarly, the set values of the shift amount control signals {s2, s1, s0} and the waveforms of the respective output signals when the shift amounts are designated as 4, 5, 6, 7 are shown in (6) of FIG. ),
This is as shown in (7), (8) and (9).
As is clear from the above, the shift amount control signal is obtained by binarizing the shift amount and changing the value of each bit to s2, s1, s0.
Should be set as For example, when the shift amount is 6, as shown in (8) of FIG. 6, {s2, s1, s0} =
It becomes {1,1,0}.

In the example shown in FIGS. 5 and 6, three T-Fs are used.
It is assumed that the outputs are all "0" as the initial state of F20a to 20c, but in the case of other initial states, the same waveform can be obtained if the time chart is shifted by a few bits. Although the element delay time is considered to be 0 in FIGS. 5 and 6, the element delay time cannot be neglected in practice, so a delay element is appropriately used where necessary. (2) Second Embodiment of Divider Circuit FIG. 7 is a block diagram of an embodiment of the second invention, and FIGS. 8 and 9 are diagrams showing operation waveforms of respective parts corresponding to respective shift amounts in FIG. 1) and (2).

In the second embodiment shown in FIG. 7 also, in principle, an example of a frequency dividing circuit in which a circuit for performing frequency division by 2 is constituted by three stages is shown, and this circuit is surrounded by a dotted line in FIG. It can be used as a frequency divider. That is, this embodiment is shown in FIG.
This corresponds to the case where the number N of stages of frequency dividing elements N (N ≧ 2) is 3 and can be used for 1 to 8 separation. Reference numerals 20a to 20c in FIG. 7 are T-type flip-flops (T-FFs) corresponding to the frequency dividing means (1a) and the different phase frequency dividing means (1b, 1c) in FIG. 2, and 21a to 21c are inversions in FIG. An exclusive OR circuit (EXO) corresponding to the means (2a, 2b, 2c) and performing an exclusive OR operation of the shift amount control signals s0, s1, s2 and the respective input signals.
R), 23a is a D-type flip-flop (D-FF) corresponding to the phase changing means (4a) in FIG. 2, and 24a, 24b is a selector (S) corresponding to the selecting means (7a, 7b) in FIG.
EL).

The T-FFs 20b and 20c are of the master-slave type, and the master output (main output) and the slave output (slave output) are drawn out to obtain SEL7.
a and 7b. The operation waveform of each unit corresponding to each shift amount using the configuration of FIG. 7 will be described with reference to FIGS. 8 and 9. Each symbol b, t, u, v, w, x, shown in FIG. 8 and FIG.
y, z, c, f, and k represent signals output from each circuit of FIG. 7 and represented by the same symbols, b is a clock input, and t is T-FF.
20a is an output signal, u is a master output signal of the T-FF 20b, v is a slave output signal of the T-FF 20b, and w is T-.
FF20c master output signal, x is T-FF20c slave output signal, y and z are SEL24a and 24b output signals, c, f and k are EXOR21a to 21c output signals, and these signals c, f and k are When the frequency-divided output signal having the same sign shown in FIG. 14 is supplied to each part of the separation circuit (serial / parallel conversion circuit) of FIG. 14, the signal of each channel is output.

Also in this case, the shift amount control signal may be binarized by the amount to be shifted in the same manner as in the first embodiment, and the value of each bit may be set as s2, s1, s0. As in the frequency divider circuit shown in FIG. 7, the shift amount control signal s
According to the configuration in which the output signal is inverted by 0, s1, and s2, the desired clock is selected from the two divided clocks having different phases, and the extraction is performed by the divided clock output of the preceding stage, the high speed corresponding to the bit rate is achieved. A channel shift operation that does not require switching speed can be realized. Figure 8 above
In the example of FIG. 9, it is assumed that the outputs are all “0” as the initial states of the three T-FFs 20a to 20c, but even in the other initial states, the time chart can be seen by shifting a few bits. For example, the same waveform can be obtained. Although the element delay time is considered to be 0 also in FIGS. 8 and 9, delay elements are appropriately used where necessary. (3) Third Embodiment of Divider Circuit FIG. 10 is a block diagram of an embodiment of the second invention, FIG. 11 and FIG.
2A and 2B are diagrams (No. 1) and (No. 2) showing the operation waveform of each unit corresponding to each shift amount in FIG.

In the third embodiment shown in FIG. 10, an example of a frequency dividing circuit in which a circuit for performing frequency division by 2 is constructed in three stages is shown in principle, and this circuit is surrounded by a dotted line in FIG. It can be used as a frequency divider. That is, this embodiment also corresponds to the case where the number of stages N of the frequency dividing element N (N ≧ 2) is 3 in the configuration of FIG. 2, and can be used when performing 1 to 8 separation.

Reference numerals 20a and 20b in FIG. 10 correspond to the frequency dividing means (1a) and the different phase frequency dividing means (1b) in FIG.
Type flip-flop _{(T-FF), 20 1} c, 20 1 c is a D-type flip-flops constituting the circuit corresponding to a different phase of dividing unit of FIG. 3 (1c) (D-FF ), 21a~21c
Corresponds to the inverting means (2a, 2b, 2c) in FIG. 3, and is an exclusive OR circuit (EXOR) for performing a logical operation of an exclusive OR of the shift amount control signals s0, s1, s2 and the respective input signals. ), 24a, 24b are selectors (SEL) corresponding to the selection means (7a, 7b) of FIG.

[0042] In addition, T-FF20b, D-FF20 1 c,
20 ₁ c should be designed master-slave, drawer master output (main output) and a slave output (secondary output), respectively and inputs SEL7a, to 7b. The operation waveform of each unit corresponding to each shift amount using the configuration of FIG. 10 will be described with reference to FIGS. 11 and 12. The symbols b, t, u, v, w, x, y, z, c, f, and k shown in FIGS.
Represents a signal output from each circuit of the same symbol, b is a clock input, t is an output signal of the T-FF 20a, and u is T.
The master output signal of -FF20b, v is the slave output signal of the T-FF20b, w is D-FF20 ₁ c master output signal, x is the slave output signal of the D-FF20 ₁ c, y is D-
FF20 ₂ c master output signal, z is the slave output signal of the _{D-FF20 2 c, c,} f, k is EXOR21a~
21c is an output signal, and these signals c, f and k are shown in FIG.
When the frequency-divided output signal of the same sign as shown in (4) is supplied to each part of the separation circuit (serial / parallel conversion circuit) of FIG.

Also in this case, the shift amount control signal may be binarized by the amount to be shifted in the same manner as in the first embodiment, and the value of each bit may be set as s2, s1, s0. As in the frequency dividing circuit shown in FIG. 10, the output signal is inverted by the shift amount control signals s0, s1 and s2, and
According to the configuration in which a desired clock is selected from 2 ^N divided clocks having different phases, it is possible to realize a channel shift operation that does not require a high switching speed corresponding to the bit rate.

Although the element delay time is considered to be 0 in FIGS. 11 and 12, delay elements are actually used where necessary. (4) Embodiment of Frame Synchronizing Circuit FIG. 13 shows a frame synchronizing circuit using the frequency dividing circuit according to the present invention. This circuit in FIG. 13 is provided with the frequency dividing circuit shown in FIG. 4 or 7 or 10 in FIG. 13, and when the multiplexed data (DATA) signal is input, it is separated into eight channel signals. Serial-parallel conversion circuit, 51
Is a shift amount control signal s for detecting the shift of the frame synchronization signal from each of the eight channel signals and adjusting the phase.
2, s1 and s0 are output to the serial-parallel conversion circuit 50 to output each of the eight channel data and generate a clock (1/8 CLK) at a speed 1/8 of the clock signal (CLK) synchronized with the multiplexed data. It is a frame detection circuit that does.

The operation of FIG. 13 will be described. First, the frame detection circuit 51 sends the shift amount control signal to {s2, s1, s.
0} = {0,0,0}. If the number of bits deviated from the normal state is found by detecting the deviation of the synchronization pattern in this state, it is expressed as a binary number and set as {s2, s1, s0}, and the serial-parallel conversion circuit 50 is set. Output. Then, in the frequency division circuit of the serial-parallel conversion circuit 50, the frequency division clock outputs c, f, and k are assigned to the data without changing the mutual phase relationship by the corresponding shift function as described above. Since the phase is shifted by the number of bits, an output in which the channel is shifted by the specified number of bits is generated from each data output. When the divider circuit according to the present invention is configured with a separation circuit to form a serial-parallel conversion circuit, each circuit of D-FF and T-FF is an individual IC.
In addition to the configuration of
It can also be converted to C.

[0046]

According to the present invention, since the circuit scale is increased by about one D-type flip-flop per stage after the second stage of the frequency dividing circuit, a high channel switching speed corresponding to the bit rate is not required. ， Achieved channel shift operation,
Since an arbitrary amount of channel shift can be designated, quick frame synchronization can be established.

Further, according to the second invention, it is possible to realize a channel shift operation which does not require a high switching speed corresponding to a bit rate, and to quickly establish frame synchronization. Furthermore, according to the third invention, a high-speed channel shift operation with a greatly improved phase margin is realized,
It is possible to quickly establish frame synchronization.

[Brief description of drawings]

FIG. 1 is a principle configurational diagram of a first invention.

FIG. 2 is a principle configuration diagram of a second invention.

FIG. 3 is a principle configuration diagram of a third invention.

FIG. 4 is a configuration diagram of an embodiment of the first invention.

FIG. 5 is a diagram (No. 1) showing an operation waveform of each unit corresponding to each shift amount.

FIG. 6 is a diagram (No. 2) showing the operation waveform of each unit corresponding to each shift amount.

FIG. 7 is a configuration diagram of a second embodiment.

FIG. 8 is a diagram (No. 1) showing operation waveforms of respective portions corresponding to respective shift amounts in FIG. 7.

9 is a diagram (No. 2) showing operation waveforms of respective portions corresponding to respective shift amounts in FIG. 7.

FIG. 10 is a configuration diagram of a third embodiment.

FIG. 11 is a diagram (No. 1) showing operation waveforms of respective parts corresponding to respective shift amounts in FIG.

FIG. 12 is a diagram (No. 2) showing the operation waveform of each unit corresponding to each shift amount in FIG.

FIG. 13 is a frame synchronization circuit using the frequency dividing circuit according to the present invention.

FIG. 14 is a configuration diagram of a conventional example.

FIG. 15 is a timing chart of a configuration of a conventional example.

[Explanation of symbols]

 1a, 1b, 1c ··· Dividing means 2a, 2b, 2c ··· Inverting means 3 Delaying means 4a, 4b · · Phase changing means 5 Shift amount control section 6a, 6b ..Selection means

Claims (5)

[Claims] 1. A multi-stage frequency dividing circuit in which a plurality of frequency dividing means are connected in cascade, wherein each output of each frequency dividing means is input and the inverting function is controlled by a shift amount control signal. The output of the inverting means of each subsequent stage is input, and each phase variable means for generating each divided clock whose phase is controlled by each drive signal is provided, and the output of the inverting means of the first stage is changed to the phase changing means of the second stage. And a connection for supplying the output of the phase varying means of the nth stage as a drive signal of the inverting means of the (n + 1) th stage, and a shift amount control signal corresponding to a desired shift amount of each stage. A frequency divider circuit for shifting the phase of each divided clock generated from the output of the first-stage inverting means and the output of each phase varying means by the desired shift amount by being supplied to the inverting means. 2. A main output obtained by dividing the input by 2 and a sub output obtained by shifting the main output by a half cycle are connected, and a frequency dividing means having the sub output of the preceding stage as the input is connected in cascade, and N ( N ≧ 2) selecting means for selecting the main output and the sub-output of the frequency dividing means of the stage by a shift control signal and outputting as the frequency dividing clock of each stage, and the frequency dividing clock from the frequency dividing means of the first stage. And the inverting means of each stage for inverting the divided clock of each stage by the shift control signal, and the output clock of the inverting means of the N (N ≧ 2) th stage, from the selecting means of the (N + 1) th stage. And a phase variable means for controlling the phase of the divided clock of each of the stages to match each other. 3. A multi-stage frequency dividing circuit for generating a frequency-divided clock obtained by frequency-dividing a reference clock by a desired amount by means of a multi-stage frequency dividing means, wherein the frequency-divided clock of each stage obtained by frequency-dividing the reference clock is converted by a shift control signal. Inverting means at each stage for inverting, and different phase clock generating means for generating 2 ^N-1 different phase clocks whose phases are shifted by the cycle T at a cycle 2 ^N times the cycle T of the reference clock, A multi-stage frequency dividing circuit, comprising: selecting means for selecting the desired different phase clock according to a shift control signal input to the inverting means from the first stage to the previous stage and outputting it as a divided clock of each stage. . 4. A frequency dividing circuit for generating each frequency-divided clock by inputting a clock synchronized with the multiplexed signal and the frequency-divided clock to sequentially separate the multiplexed signal into 2 ^N (N ≧ 2).
A serial-parallel conversion circuit for a multiplexed signal, comprising: a separation circuit for separating the individual signals, wherein the frequency division circuit according to any one of claims 1, 2, and 3 is used as a frequency division circuit of the serial-parallel conversion circuit. A circuit is provided, and the N signals output from the separation circuit are each shifted by an arbitrary bit from 0 to N-1 by a shift amount control signal of the frequency dividing circuit. Serial-parallel conversion circuit using the frequency divider circuit. 5. The shift amount for correcting the bit shift detected by the frame detection circuit according to claim 4, further comprising a frame detection circuit for receiving N signals of the serial-parallel conversion circuit and detecting the amount of bit shift. When the control signal is generated, the frequency dividing circuit generates each frequency-divided clock shifted by a corresponding bit to correct the deviation of N signals. A serial-parallel conversion circuit using the frequency dividing circuit.