JPH0661373A - Resin sealed semiconductor device and manufacturing equipment thereof - Google Patents

Resin sealed semiconductor device and manufacturing equipment thereof

Info

Publication number
JPH0661373A
JPH0661373A JP21248292A JP21248292A JPH0661373A JP H0661373 A JPH0661373 A JP H0661373A JP 21248292 A JP21248292 A JP 21248292A JP 21248292 A JP21248292 A JP 21248292A JP H0661373 A JPH0661373 A JP H0661373A
Authority
JP
Japan
Prior art keywords
ejector pin
resin
mark
semiconductor device
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21248292A
Other languages
Japanese (ja)
Other versions
JP2993583B2 (en
Inventor
Yoshio Urasaki
善雄 浦崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP21248292A priority Critical patent/JP2993583B2/en
Publication of JPH0661373A publication Critical patent/JPH0661373A/en
Application granted granted Critical
Publication of JP2993583B2 publication Critical patent/JP2993583B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable the positions of lead pins to be visually and easily discriminated so as to realize resin scaling of high reliability by a method wherein index marks are indicated only by dents of ejector pins and projections different from each other in shape. CONSTITUTION:Ejector pin marks 1a and 1b are recessed, and as the mark 1a is mirror finished, it can be visually and clearly observed, and on the other hand, as the mark 1a is satin finished, it is hardly discriminated from its surroundings and can not be observed. By this process, the ejector pin 1a clearly observed is arranged by a terminal pin 3, and the ejector pin mark 1b is arranged by other terminal pins, whereby index marks can be indicated by only dents of elector pins. Therefore a semiconductor device can be sealed up with resin high in reliability without deteriorating resin in fluidity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップを樹脂で
覆った、樹脂封止型半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device in which a semiconductor chip is covered with resin.

【0002】[0002]

【従来の技術】樹脂封止型半導体装置の1ピン端子の方
向を示すために、パッケージ表面の特定エリアにインデ
ックスマークを入れることを決められているが、従来の
技術では前記インデックスマークとして樹脂封止された
成形品の離型用イジェクターピンを入れることによって
パッケージ表面にできたイジェクターピン跡等のくぼみ
もしくはでっぱりを利用するケースがあるが通常、イジ
ェクターピン跡は、図7,図9のくぼみ1aの様に同形
状で複数個存在し、インデックスマークとして使用する
ためには、図7,図8のテーパーカット7や図9のノッ
チ8等との組合せにより前記イジェクターピン跡をイン
デックスマークであると意思表示する方法が一般的に用
いられる。
2. Description of the Related Art In order to indicate the direction of a 1-pin terminal of a resin-sealed semiconductor device, it has been decided to put an index mark in a specific area on the package surface. There are cases where recesses or protrusions such as ejector pin marks formed on the package surface by using the ejector pin for releasing the molded product that has been stopped are used, but normally the ejector pin mark is the recess 1a in FIGS. 7 and 9. In order to use as the index mark, the ejector pin marks are used as index marks in combination with the taper cut 7 shown in FIGS. 7 and 8 and the notch 8 shown in FIG. A method of expressing intention is generally used.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記のよ
うな方法では、パッケージ裏面を表にして使用する、リ
バースタイプの場合にノッチ及びテーパーカットを裏面
にも入れなければならなくなり、その場合、樹脂封止の
際に樹脂の流動性が悪くなり、ボイド及び未填を誘発
し、信頼性を著しく低下させるなどの問題があった。
However, in the above method, the reverse side of the package is used, and in the case of the reverse type, notches and taper cuts must be made on the back side as well. There was a problem that the fluidity of the resin was deteriorated at the time of stopping, voids and unfilling were induced, and the reliability was significantly lowered.

【0004】また、薄型のパッケージにおいてもノッチ
及びテーパーカット等を入れることによって同様の問題
があった。
Further, even in a thin package, there is a similar problem due to the inclusion of notches and taper cuts.

【0005】本発明は、上記従来の問題点を解決するも
のでノッチやテーパーカットを入れずにインデックスマ
ークを表示することを目的とする。
An object of the present invention is to solve the above conventional problems and to display an index mark without notches or taper cuts.

【0006】[0006]

【課題を解決するための手段】上記問題点を解決するた
めに本発明は、複数本のイジェクターピン等によってで
きるくぼみやでっぱりのみでインデックスマークを示す
ことができる様にイジェクターピンに一本もしくは、複
数本に手を加えることによってインデックスマークとな
る、イジェクターピン跡が他のイジェクターピン跡と視
覚的に見て異なることを特徴とするものである。
SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides one ejector pin or one ejector pin so that an index mark can be shown only by a dent or a protrusion formed by a plurality of ejector pins or the like. It is characterized in that the ejector pin mark, which becomes an index mark by modifying a plurality of lines, is visually different from other ejector pin marks.

【0007】[0007]

【作用】この構成によって、イジェクターピン跡のみで
インデックスマーク表示できるため、樹脂封止の際、樹
脂の流動性をそこなわず、信頼性の高い樹脂が行なえ
る。
With this structure, since the index mark can be displayed only by the ejector pin mark, the resin can be made highly reliable without impairing the fluidity of the resin when the resin is sealed.

【0008】[0008]

【実施例】以下に本発明の一実施例について図面をもと
に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0009】図1は、本発明の実施例における樹脂封止
型半導体装置の斜視図である。図1において、2はパッ
ケージ表面(梨地面)、1aはイジェクターピン跡(鏡
面)、1bはイジェクターピン跡(梨地面)、3は1ピ
ン端子、4はその他の端子を示す。図2は、図1の平面
図でこの時イジェクターピン跡1a,1bはどちらもく
ぼみを有しているにもかかわらず、イジェクターピン跡
1aは、視覚的に見てはっきり映り、イジェクターピン
跡1bは、くぼみも梨地面になっており、周囲と同化し
ほぼ見えなくなっている。図3は、図2の断面図で上記
現象の原理を示す、視覚的に見てはっきり見えるイジェ
クターピン跡1aの底面は、鏡面加工が施してあり、ま
わりとほぼ同化して見えるイジェクターピン跡1bの底
面は、周囲の表面とほぼ同等の凸凹でなる梨地面を有し
ている。このため上記の様な現象となる、これを利用
し、1ピン端子3側にはっきり見えるイジェクターピン
跡1aを配置し、それ以外のイジェクターピン跡1bに
すれば、前記イジェクターピン跡のくぼみのみでインデ
ックス表示が可能となる。
FIG. 1 is a perspective view of a resin-sealed semiconductor device according to an embodiment of the present invention. In FIG. 1, 2 is a package surface (matte surface), 1a is an ejector pin mark (mirror surface), 1b is an ejector pin mark (matte surface), 3 is a 1-pin terminal, and 4 is another terminal. 2 is a plan view of FIG. 1, at this time, the ejector pin traces 1a and 1b both have depressions, but the ejector pin traces 1a are clearly visible and the ejector pin traces 1b are visible. The hollow is also a pear-skin, and is almost invisible as it is assimilated with the surrounding area. FIG. 3 shows the principle of the above phenomenon in the cross-sectional view of FIG. The bottom surface of the has a textured surface that is as rough as the surrounding surface. For this reason, the phenomenon as described above is used. By using this, if the ejector pin traces 1a clearly visible on the 1-pin terminal 3 side are arranged and the other ejector pin traces 1b are formed, only the recesses of the ejector pin traces are formed. The index can be displayed.

【0010】前記実施例は、くぼみにより説明したがこ
れが突起ないしはでっぱりであってもなんら問題はな
い。
Although the above-mentioned embodiments have been described with the indentation, there is no problem even if this is a protrusion or a protrusion.

【0011】次に、前記くぼみの製造装置について説明
する。図4は、上記くぼみ製造装置の断面図である。5
aはイジェクターピン(鏡面)、5bはイジェクターピ
ン(梨地面)で、9は上金型、10は下金型を示す。1
1はワイヤーボンド済のフレームで12の半導体チップ
に13のAuワイヤーが結線された状態のものを上金型
9と下金型10ではさみ込んで、できた14の金型空間
に樹脂を流し込み封止する、イジェクターピン5a,5
bは、成形品を上金型9から離型させるため、Aの方向
へ下降しする動きをするものであるが、このイジェクタ
ーピン5aの底面に鏡面加工を施し、イジェクターピン
5bに上金型9の表面とほぼ同一の加工この場合梨地加
工を施す。この状態で封止するとパッケージ表面に前記
へこみを作ることができる。但し、この場合のイジェク
ターピンは、イジェクター機構(型から離型させる機
構)がなくても同様とする。
Next, the manufacturing apparatus for the recess will be described. FIG. 4 is a cross-sectional view of the recess manufacturing device. 5
a is an ejector pin (mirror surface), 5b is an ejector pin (matte surface), 9 is an upper die, and 10 is a lower die. 1
1 is a wire-bonded frame in which 12 semiconductor chips and 13 Au wires are connected by an upper mold 9 and a lower mold 10, and resin is poured into the 14 mold spaces formed. Ejector pins 5a, 5 to be sealed
b moves downward in the direction of A in order to release the molded product from the upper mold 9, but the bottom surface of the ejector pin 5a is mirror-finished so that the ejector pin 5b has an upper mold. Processing substantially the same as the surface of No. 9 In this case, satin processing is performed. If sealed in this state, the dent can be formed on the surface of the package. However, the ejector pin in this case is the same even if there is no ejector mechanism (a mechanism for releasing from the mold).

【0012】同様の要領で第2、第3の実施例を説明す
る。前記実施例では、パッケージ表面を梨地面とした
が、図5の様に、表面が鏡面の場合、1ピン端子3を示
すためにくぼみ1bを梨地加工とし、くぼみ1aを鏡面
加工としてインデックスマークとして表示する。また図
6の様にインデックスマークとなるくぼみ6の形状を他
と異ならせることでもよいものとする。
Second and third embodiments will be described in the same manner. In the above-mentioned embodiment, the package surface is satin-finished, but when the surface is mirror-finished as shown in FIG. 5, the recess 1b is satin-finished to show the 1-pin terminal 3, and the recess 1a is mirror-finished as an index mark. indicate. Further, as shown in FIG. 6, the shape of the indentation 6 serving as an index mark may be different from other shapes.

【0013】[0013]

【発明の効果】本発明は、互いに形状を異ならせたイジ
ェクターピン跡等のくぼみ及びでっぱりのみでインデッ
クスマークを表示することができ、安価な製造装置また
成形性に優れた樹脂封止型半導体装置を実現できるもの
である。
According to the present invention, the index mark can be displayed only by the dents and protrusions such as ejector pin marks having different shapes, which is an inexpensive manufacturing apparatus and a resin-sealed semiconductor device excellent in moldability. Can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における樹脂封止型半導体装
置の斜視図
FIG. 1 is a perspective view of a resin-sealed semiconductor device according to an embodiment of the present invention.

【図2】図1の平面図FIG. 2 is a plan view of FIG.

【図3】図2の断面図FIG. 3 is a sectional view of FIG.

【図4】本発明の一実施例における製造装置の断面構造
FIG. 4 is a sectional structural view of a manufacturing apparatus according to an embodiment of the present invention.

【図5】他の実施例の平面図FIG. 5 is a plan view of another embodiment.

【図6】他の実施例の平面図FIG. 6 is a plan view of another embodiment.

【図7】従来の樹脂封止型半導体装置の平面図FIG. 7 is a plan view of a conventional resin-encapsulated semiconductor device.

【図8】図7の側面図8 is a side view of FIG.

【図9】従来の樹脂封止型半導体装置の平面図FIG. 9 is a plan view of a conventional resin-sealed semiconductor device.

【符号の説明】 1a イジェクターピン跡又はくぼみ(鏡面加工) 1b イジェクターピン跡又はくぼみ(梨地加工) 2 パッケージ表面(梨地加工) 2a パッケージ表面(鏡面加工) 3 1ピン端子 4 1ピン以外の端子 5a イジェクターピン(鏡面加工) 5b イジェクターピン(梨地加工) 6 イジェクターピン(異形状) 7 テーパーカット 8 ノッチ 9 封止成形用上金型 10 封止成形用下金型 11 リードフレーム 12 半導体チップ 13 Auワイヤー 14 金型空間(型をしめ込んだ時の)[Explanation of symbols] 1a Ejector pin mark or dent (mirror finish) 1b Ejector pin mark or dent (matte finish) 2 Package surface (matte finish) 2a Package surface (mirror finish) 3 1-pin terminal 4 4 Pin other than 1 pin 5a Ejector pin (mirror finish) 5b Ejector pin (finished finish) 6 Ejector pin (different shape) 7 Tapered cut 8 Notch 9 Upper mold for sealing molding 10 Lower mold for sealing molding 11 Lead frame 12 Semiconductor chip 13 Au wire 14 Mold space (when the mold is closed)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】全表面に複数個のくぼみもしくはでっぱり
を有し、前記くぼみもしくはでっぱりが視覚的に見て異
なることを特徴とする樹脂封止型半導体装置。
1. A resin-sealed semiconductor device having a plurality of depressions or protrusions on the entire surface, the depressions or protrusions being visually different.
【請求項2】請求項1に記載のくぼみもしくはでっぱり
を製造する、製造装置。
2. A manufacturing apparatus for manufacturing the depression or the protrusion according to claim 1.
JP21248292A 1992-08-10 1992-08-10 Resin-sealed semiconductor device Expired - Fee Related JP2993583B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21248292A JP2993583B2 (en) 1992-08-10 1992-08-10 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21248292A JP2993583B2 (en) 1992-08-10 1992-08-10 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH0661373A true JPH0661373A (en) 1994-03-04
JP2993583B2 JP2993583B2 (en) 1999-12-20

Family

ID=16623384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21248292A Expired - Fee Related JP2993583B2 (en) 1992-08-10 1992-08-10 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2993583B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
US6420790B1 (en) * 1999-12-02 2002-07-16 Oki Electric Industry Co., Ltd. Semiconductor device
JP2008252133A (en) * 2008-07-10 2008-10-16 Sanyo Electric Co Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
EP0895287A3 (en) * 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US6420790B1 (en) * 1999-12-02 2002-07-16 Oki Electric Industry Co., Ltd. Semiconductor device
JP2008252133A (en) * 2008-07-10 2008-10-16 Sanyo Electric Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2993583B2 (en) 1999-12-20

Similar Documents

Publication Publication Date Title
JPH05144982A (en) Integrated circuit device
US6469369B1 (en) Leadframe having a mold inflow groove and method for making
US4801997A (en) High packing density lead frame and integrated circuit
US6472729B1 (en) Semiconductor device
JPH0661373A (en) Resin sealed semiconductor device and manufacturing equipment thereof
JPH04215464A (en) Improved lead frame for package of integrated power device
KR100618541B1 (en) Method for fabricating multi-chip semiconductor package
US20040178483A1 (en) Method of packaging a quad flat no-lead semiconductor and a quad flat no-lead semiconductor
KR0151828B1 (en) A package molding apparatus
JPH07214600A (en) Die for molding transparent resin sealing-type semiconductor device
JPH01268036A (en) Molding die
KR100351921B1 (en) lead frame for fabricating semiconductor package
JP2560194B2 (en) Method of manufacturing packaged semiconductor device
KR200177346Y1 (en) Semiconductor package
JPH0878596A (en) Lead frame use resin-encapsulating device and semiconductor device use lead frame
JPS63170949A (en) Semiconductor device
JPH1187565A (en) Semiconductor device
KR100192329B1 (en) Lead frame process for semiconductor device
JPH05235070A (en) Resin sealing device of semiconductor integrated
JPH07130940A (en) Structure of lead frame for quad type semiconductor device
KR0157870B1 (en) Semiconductor package
JPH04334418A (en) Mold
JPH02205061A (en) Lead frame
JPH012329A (en) Mold for resin sealing
JPH0247855A (en) Semiconductor device

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081022

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091022

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091022

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20101022

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 12

Free format text: PAYMENT UNTIL: 20111022

LAPS Cancellation because of no payment of annual fees