JPH0247855A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0247855A
JPH0247855A JP19921988A JP19921988A JPH0247855A JP H0247855 A JPH0247855 A JP H0247855A JP 19921988 A JP19921988 A JP 19921988A JP 19921988 A JP19921988 A JP 19921988A JP H0247855 A JPH0247855 A JP H0247855A
Authority
JP
Japan
Prior art keywords
package
semiconductor device
circuits
circuit
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19921988A
Other languages
Japanese (ja)
Inventor
Kazutoyo Akase
赤瀬 一豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19921988A priority Critical patent/JPH0247855A/en
Publication of JPH0247855A publication Critical patent/JPH0247855A/en
Pending legal-status Critical Current

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To facilitate the distinction of semiconductor devices and the confirmation of leads by forming a package of a plurality of the same circuits packaged in series in one resin mold and arranging marks corresponding to each circuit on the package to be cut by one or a plurality of circuits. CONSTITUTION:A semiconductor device comprises a package 1 in which, for example, the same six circuits are arranged in series and integrally molded. Cutting the package 1 at the broken lines provides up to six semiconductor devices. Marks 3 are formed at the parts, corresponding to each circuit, of the upper surface of the package 1. For example, when the package 1 is cut by one circuit, one mark 3 exists on the upper surface of each package, and when the package 1 is cut by two circuits, two marks 3 exist on the upper surface of each package. The number of the circuits can be confirmed by confirming the number of the marks 3 to enable the judgement of the sort thereof.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂モールド型半導体装置に関し、特に同一回
路を複数個有するマルチ回路構成の半導体装置に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin molded semiconductor device, and particularly to a semiconductor device having a multi-circuit configuration having a plurality of identical circuits.

〔従来の技術] 従来、マルチ回路構成の半導体装置は、同一回路を複数
個直列状態にかつ一体的に樹脂モールドした構成とされ
、これを1個又は複数の回路を単位として切断すること
により、夫々1つの回路又は複数の回路を含む半導体装
置として構成されている。この場合、従来の半導体装置
では各回路に対応する目印等は設けてはおらず、そのパ
ッケージの切断長さ等によって回路構成を判断する構成
となっている。
[Prior Art] Conventionally, a semiconductor device with a multi-circuit configuration has a configuration in which a plurality of identical circuits are connected in series and integrally molded with resin, and by cutting this into one or more circuits as a unit, Each of the semiconductor devices is configured as a semiconductor device including one circuit or a plurality of circuits. In this case, conventional semiconductor devices do not provide marks or the like corresponding to each circuit, and the circuit configuration is determined based on the cut length of the package or the like.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のマルチ回路構成の半導体装置では、外観
上の特徴が存在しないため、1つの回路又は複数の回路
を単位として切断した後に、これらの切断した半導体装
置に対して捺印を行う等のために各半導体装置を見分け
ようとした場合、半導体装置の長さやリード数から判断
せざるを得す、判断に熟練を要する等極めて難しいもの
となっている。また、リードの位置を確認することも困
難である。
In the conventional multi-circuit configuration semiconductor device described above, there are no external features, so after cutting one circuit or multiple circuits as a unit, it is necessary to stamp the cut semiconductor device. In order to identify each semiconductor device, it is extremely difficult to make a judgment based on the length of the semiconductor device and the number of leads, and requires skill to make the judgment. It is also difficult to confirm the position of the lead.

本発明は一目で半導体装置の見分は及びリード位置の確
認を容易に行うことができる半導体装置を提供すること
を目的としている。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that allows easy identification of the semiconductor device and confirmation of lead positions at a glance.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、同一の回路を複数個連続して1
つのモールド樹脂で一体的にパッケージを形成し、かつ
このパッケージを1つ又は複数個の回路を単位として切
断する半導体装置のパッケージに、各回路に対応する複
数個の目印を配列している。
In the semiconductor device of the present invention, a plurality of identical circuits are connected in series.
A plurality of marks corresponding to each circuit are arranged on a package of a semiconductor device in which a package is integrally formed with one molded resin and the package is cut into one or more circuits.

〔作用] 上述した構成では、パッケージを切断したときにも、各
回路に対応する目印がパッケージ面で確認でき、切断し
た半導体装置に含まれる回路数を確認して半導体装置の
見分は及びリードの確認を容易に行うことが可能となる
[Function] With the above configuration, even when the package is cut, marks corresponding to each circuit can be confirmed on the package surface, and the number of circuits included in the cut semiconductor device can be confirmed to identify the semiconductor device and lead. It becomes possible to easily confirm the following.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示しており、第1図(a)
は平面図、第1図(b)はその側面図である。この半導
体装置は、6個の同一回路を直列配置して一体的に樹脂
モールドしたパッケージ1を有しており、パッケージ1
の側面からは各回路に対応する夫々複数本のリード2を
突出した構成としている。この例では、図示破線の位置
でパッケージ1を切断することにより、最大で6個の半
導体装置を得ることができる。そして、このパッケージ
1の上面には、1つの回路に対応する位置に、目印3を
形成している。この目印3は、ここではパッケージ1の
上面一部を凹設して他の面と区別できるように構成して
いる。
FIG. 1 shows an embodiment of the present invention, and FIG. 1(a)
is a plan view, and FIG. 1(b) is a side view thereof. This semiconductor device has a package 1 in which six identical circuits are arranged in series and integrally molded with resin.
A plurality of leads 2 corresponding to each circuit protrude from the side. In this example, a maximum of six semiconductor devices can be obtained by cutting the package 1 at the positions indicated by broken lines in the figure. A mark 3 is formed on the top surface of the package 1 at a position corresponding to one circuit. Here, the mark 3 is configured so that a part of the upper surface of the package 1 is recessed so that it can be distinguished from other surfaces.

なお、この目印3は、パッケージ1の上面と面一に形成
した上で、目印3の部分の表面荒さを他の部分と相違さ
せることによっても構成できる。
The mark 3 can also be formed by forming the mark 3 flush with the top surface of the package 1 and then making the surface roughness of the mark 3 different from that of other parts.

例えば、パッケージ1の表面全体を鏡面仕上げとし、目
印3の表面を粗に形成すればよい。勿論、逆の表面状態
としてもよい。
For example, the entire surface of the package 1 may be mirror-finished, and the surface of the mark 3 may be formed roughly. Of course, the surface state may be reversed.

この構成によれば、例えば1つの回路を単位にしてパッ
ケージ1を切断したときには、第2図(a)のように、
半導体装置11のパッケージ上面に1つの目印3が存在
される。また、2つの回路を単位にしてパッケージ1を
切断したときには、第2図(b)のように、半導体装1
12のパッケージ上面に2つの目印が存在される。した
がって、切断された後の半導体装置に対して、この目印
3の個数を確認することにより、その半導体装置に含ま
れる回路数を直ちに確認することができ、半導体装置の
種類の判断を迅速に実行できる。
According to this configuration, when the package 1 is cut into one circuit unit, for example, as shown in FIG. 2(a),
One mark 3 is present on the top surface of the package of the semiconductor device 11. Furthermore, when the package 1 is cut into two circuits, the semiconductor device 1 is cut as shown in FIG.
There are two landmarks on the top of the 12 packages. Therefore, by checking the number of marks 3 on a semiconductor device after it has been cut, the number of circuits included in the semiconductor device can be immediately confirmed, and the type of semiconductor device can be quickly determined. can.

また、目印3の位置により複数本のリード2の位置を確
認することも可能となる。
Furthermore, it is also possible to confirm the positions of the plurality of leads 2 by the positions of the marks 3.

なお、目印3を利用して半導体装置の見分けやそのリー
ド位置の確認を行うためには、目印3は1つの回路を含
む半導体装置のパッケージの174以下の寸法で形成す
ることが好ましい。また、目印3はパッケージの裏面側
に設けてもよい。
Note that in order to identify the semiconductor device and confirm the lead position using the mark 3, it is preferable that the mark 3 is formed with a size of 174 mm or less of the package of the semiconductor device including one circuit. Further, the mark 3 may be provided on the back side of the package.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体装置のパッケージ
に、各回路に対応する複数個の目印を配列しているので
、パッケージを切断したときにも、各回路に対応する目
印をパッケージ面で確認することができ、切断した半導
体装置に含まれる回路数を確認して半導体装置の見分は
及びリード位置の確認を容易に行うことができる効果が
ある。
As explained above, in the present invention, a plurality of marks corresponding to each circuit are arranged on the package of a semiconductor device, so even when the package is cut, the marks corresponding to each circuit can be confirmed on the package surface. This has the advantage that it is possible to easily identify the semiconductor device by checking the number of circuits included in the cut semiconductor device and to check the lead positions.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示しており、第1図(a)
は平面図、第1図(b)は側面図、第2図(a)は1つ
の回路の単位で切断した半導体装置の平面図、第2図(
b)は2つの回路の単位で切断した半導体装置の平面図
である。 1・・・パッケージ、2・・・リード、3・・・目印、
11゜12・・・半導体装置。 区 Cす 綜
FIG. 1 shows an embodiment of the present invention, and FIG. 1(a)
is a plan view, FIG. 1(b) is a side view, FIG. 2(a) is a plan view of the semiconductor device cut into one circuit unit, and FIG.
b) is a plan view of the semiconductor device cut into two circuit units; 1...Package, 2...Lead, 3...Mark,
11゜12...Semiconductor device. Ward C

Claims (1)

【特許請求の範囲】[Claims] 1、同一の回路を複数個連続して1つのモールド樹脂で
一体的にパッケージを形成し、かつこのパッケージを1
つ又は複数個の回路を単位として切断する半導体装置に
おいて、前記パッケージには各回路に対応する複数個の
目印を配列したことを特徴とする半導体装置。
1. Multiple identical circuits are integrally formed in one molded resin package, and this package is
1. A semiconductor device that is cut into one or more circuits as a unit, characterized in that a plurality of marks corresponding to each circuit are arranged on the package.
JP19921988A 1988-08-10 1988-08-10 Semiconductor device Pending JPH0247855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19921988A JPH0247855A (en) 1988-08-10 1988-08-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19921988A JPH0247855A (en) 1988-08-10 1988-08-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0247855A true JPH0247855A (en) 1990-02-16

Family

ID=16404121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19921988A Pending JPH0247855A (en) 1988-08-10 1988-08-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0247855A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5337216A (en) * 1992-05-18 1994-08-09 Square D Company Multichip semiconductor small outline integrated circuit package structure
US7199306B2 (en) 1994-12-05 2007-04-03 Freescale Semiconductor, Inc. Multi-strand substrate for ball-grid array assemblies and method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5337216A (en) * 1992-05-18 1994-08-09 Square D Company Multichip semiconductor small outline integrated circuit package structure
US7199306B2 (en) 1994-12-05 2007-04-03 Freescale Semiconductor, Inc. Multi-strand substrate for ball-grid array assemblies and method
US7397001B2 (en) 1994-12-05 2008-07-08 Freescale Semiconductor, Inc. Multi-strand substrate for ball-grid array assemblies and method

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