JPH066009A - Mounting structure of integrated circuit - Google Patents
Mounting structure of integrated circuitInfo
- Publication number
- JPH066009A JPH066009A JP15662792A JP15662792A JPH066009A JP H066009 A JPH066009 A JP H066009A JP 15662792 A JP15662792 A JP 15662792A JP 15662792 A JP15662792 A JP 15662792A JP H066009 A JPH066009 A JP H066009A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- ceramic substrate
- multilayer wiring
- soldering
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/145—Material
- H01L2224/14505—Bump connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81194—Lateral distribution of the bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路の実装構造に
関し、特に、集積回路の半田付けの構造に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit mounting structure, and more particularly to a structure for soldering an integrated circuit.
【０００２】[0002]
【従来の技術】従来の集積回路の実装構造は、図３に示
すように、多層配線セラミック基板２上に、半田１０に
よって集積回路１を接続する。冷却部材１７は、ねじ１
８を締めつけることにより外側に開く構造となってい
て、熱伝導ブロック７に設けられた穴に固定され、高さ
方向の位置が自由に変えられるようになっている。よっ
て半田付けされた集積回路１は、個々に高さが異なる
が、集積回路１と冷却部材１７の間隔は一定にできるよ
うな構造となっていた。2. Description of the Related Art In a conventional integrated circuit mounting structure, an integrated circuit 1 is connected to a multilayer wiring ceramic substrate 2 by solder 10 as shown in FIG. The cooling member 17 is a screw 1
It has a structure in which it is opened to the outside by tightening 8 and is fixed in a hole provided in the heat conduction block 7, so that the position in the height direction can be freely changed. Therefore, although the soldered integrated circuits 1 have different heights, the distance between the integrated circuit 1 and the cooling member 17 can be made constant.
【０００３】集積回路１から発生する熱は、熱伝導性コ
ンパウンド１１を介し、冷却部材１７に伝わる。さら
に、冷却部材１７と密着している熱伝導ブロック７に伝
わり、さらに、冷媒６が流れる流路５を有するコールド
プレート４に伝導されることにより、集積回路１が冷却
される。多層配線セラミック基板２が接着される枠８に
熱伝導ブロック７とコールドプレート４がねじで固定さ
れる。多層セラミック基板２にはピン３が植設されてい
る。The heat generated from the integrated circuit 1 is transmitted to the cooling member 17 via the heat conductive compound 11. Further, the integrated circuit 1 is cooled by being transmitted to the heat conduction block 7 in close contact with the cooling member 17 and further conducted to the cold plate 4 having the flow path 5 through which the coolant 6 flows. The heat conduction block 7 and the cold plate 4 are fixed by screws to the frame 8 to which the multilayer wiring ceramic substrate 2 is bonded. Pins 3 are implanted in the multilayer ceramic substrate 2.
【０００４】[0004]
【発明が解決しようとする課題】従来の集積回路の実装
構造では、集積回路と多層配線セラミック基板の間隔を
調整することが困難であった。そのため、半田ショート
などの不良などが発生していた。また、個々の集積回路
の高さが異なることから、冷却部材の高さを個々に調整
しなければならないため、かなりの時間を要するという
問題点があった。In the conventional integrated circuit mounting structure, it was difficult to adjust the distance between the integrated circuit and the multilayer wiring ceramic substrate. Therefore, defects such as solder shorts have occurred. Further, since the heights of the individual integrated circuits are different, the height of the cooling member has to be individually adjusted, which causes a problem that a considerable time is required.
【０００５】[0005]
【課題を解決するための手段】本発明は、集積回路を多
層配線セラミック基板に半田接続する実装構造におい
て、前記集積回路に設けられた複数の高温半田付用パッ
ドを高温半田により前記多層配線セラミック基板に設け
られた高温半田付用パッドに接続し、前記集積回路に設
けられた複数の低温半田付用パッドを低温半田により前
記多層配線セラミック基板に設けた低温半田付用パッド
に接続したことを特徴とする。According to the present invention, in a mounting structure in which an integrated circuit is connected to a multilayer wiring ceramic substrate by soldering, a plurality of high temperature soldering pads provided on the integrated circuit are soldered to the multilayer wiring ceramic substrate by high temperature soldering. Connected to a high temperature soldering pad provided on the substrate, and connecting a plurality of low temperature soldering pads provided on the integrated circuit to the low temperature soldering pad provided on the multilayer wiring ceramic substrate by low temperature soldering. Characterize.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００７】図１は、本発明の一実施例の集積回路の実
装構造を示す。図２は、本実施例の製作工程図である。FIG. 1 shows a mounting structure of an integrated circuit according to an embodiment of the present invention. FIG. 2 is a manufacturing process diagram of this embodiment.
【０００８】まず、図２により集積回路の取付け工程を
説明する。集積回路１の高温半田付用パッド１２に高温
半田９を一定の高さで供給する。供給方法は、あらかじ
め集積回路１の高温半田付用パッド１２に半田ゴテなど
で高温半田９を供給する（図２（ａ））。First, the process of mounting the integrated circuit will be described with reference to FIG. The high temperature solder 9 is supplied to the high temperature soldering pad 12 of the integrated circuit 1 at a constant height. As a supply method, the high-temperature solder 9 is previously supplied to the high-temperature soldering pad 12 of the integrated circuit 1 with a soldering iron or the like (FIG. 2A).
【０００９】この時点では、集積回路１ごとに高さの違
いがあるため、図２（ｂ）に示すように治具１６の水平
面には半田接続面を上向きにして集積回路１をのせ、さ
らにその上から平板１５とおもり１４をのせる。そし
て、そのまま、リフロー炉などにより、高温半田９をリ
フローすることにより、平板１５とおもり１４が治具１
６に設けた台１９に当たるまで下がり、集積回路１を台
１９により規定される高さにすることができる。At this time, since the heights of the integrated circuits 1 are different, the integrated circuit 1 is mounted on the horizontal surface of the jig 16 with the solder connection surface facing upward, as shown in FIG. A flat plate 15 and a weight 14 are placed on it. Then, the high-temperature solder 9 is reflowed as it is in a reflow furnace or the like, so that the flat plate 15 and the weight 14 are moved to the jig 1.
It is possible to lower the integrated circuit 1 to the height defined by the table 19 by hitting the table 19 provided on the table 6.
【００１０】そして図２（ｃ）に示すように、集積回路
１は、低温半田１０により、多層配線セラミック基板２
上に半田付けされる。低温半田１０は、多層配線セラミ
ック基板２の低温半田付用パッド１３にスクリーン印刷
などによりあらかじめ供給されている。また、集積回路
１の低温半田付用パッド１３にも低温半田１０を供給し
ておくことにより、容易に半田付けを行うことができ
る。この半田付けの際、先に供給した高温半田９がスペ
ーサとなり、集積回路１と多層配線セラミック基板２の
間隔が、最適の間隔で半田付けされ、半田オープンやシ
ョートが防止できる。また、すべての集積回路１の実装
後の高さが均一となるよう半田付けされる。Then, as shown in FIG. 2C, the integrated circuit 1 is formed by the low-temperature solder 10 by using the multilayer wiring ceramic substrate 2
Soldered on. The low temperature solder 10 is previously supplied to the low temperature soldering pad 13 of the multilayer wiring ceramic substrate 2 by screen printing or the like. Further, by supplying the low temperature solder 10 to the low temperature soldering pads 13 of the integrated circuit 1 as well, the soldering can be easily performed. At the time of this soldering, the high-temperature solder 9 previously supplied serves as a spacer, and the integrated circuit 1 and the multilayer wiring ceramic substrate 2 are soldered at an optimum interval, and solder open or short circuit can be prevented. Further, all integrated circuits 1 are soldered so that their heights after mounting are uniform.
【００１１】半田は、高温半田９と低温半田１０の融点
の差が大きいほどよい。例えば、高温半田９がＡｕ／Ｓ
ｎ共晶半田、低温半田１０がＳｎ／Ｐｂ共晶半田であれ
ば、融点に約１００°Ｃの差があるため半田付けが容易
に行える。The larger the difference in melting point between the high temperature solder 9 and the low temperature solder 10, the better the solder. For example, high temperature solder 9 is Au / S
If the n eutectic solder and the low temperature solder 10 are Sn / Pb eutectic solders, there is a difference of about 100 ° C. in melting point, so that soldering can be easily performed.
【００１２】次に、図１の集積回路の実装構造について
説明する。Next, the mounting structure of the integrated circuit of FIG. 1 will be described.
【００１３】熱伝導ブロック７は、熱伝導が良い金属で
作られる。アルミや銅などが良いが、作業性の面からア
ルミが良い材料である。表面は、腐食防止のため、メッ
キ処理を行っておくとよい。熱伝導ブロック７の集積回
路１側の面は、平面となっており、両者の間に一定の微
小間隔が保てる構造となっている。コールドプレート４
も熱伝導性の良い金属材料で作られていて、内部に冷媒
６がつねに循環するための流路５を有している。熱伝導
ブロック７とコールドプレート４を面粗度０．６ｓぐら
いの粗さで密着させることにより、熱伝導性の構造を図
っている。The heat conduction block 7 is made of a metal having good heat conduction. Aluminum and copper are good, but aluminum is a good material in terms of workability. The surface may be plated to prevent corrosion. The surface of the heat conduction block 7 on the integrated circuit 1 side is a flat surface, and has a structure in which a constant minute gap can be maintained between the two. Cold plate 4
Is also made of a metal material having a good thermal conductivity, and has a flow path 5 through which a coolant 6 always circulates. The heat conductive block 7 and the cold plate 4 are brought into close contact with each other with a surface roughness of about 0.6 s to achieve a heat conductive structure.
【００１４】熱伝導ブロック７とコールドプレート４
は、多層配線セラミック基板２に接着された枠８にねじ
で固定される。集積回路１と熱伝導ブロック７の微小間
隔には、熱伝導性コンパウンド１１を充填し、冷却性能
の向上を図っている。また低温半田付用パッド１３を集
積回路１と多層配線セラミック基板の電気的接続に用
い、高温半田付用パッド１２は電気的接続に用いていな
い。Heat conduction block 7 and cold plate 4
Are fixed to the frame 8 adhered to the multilayer wiring ceramic substrate 2 with screws. A heat conductive compound 11 is filled in a minute space between the integrated circuit 1 and the heat conductive block 7 to improve cooling performance. The low-temperature soldering pad 13 is used for electrical connection between the integrated circuit 1 and the multilayer wiring ceramic substrate, and the high-temperature soldering pad 12 is not used for electrical connection.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、２種類の
融点の異なる半田を使用して集積回路を実装することに
より、集積回路と多層配線セラミック基板とのすき間を
適当な間隔で保つことができ、半田付オープン・ショー
トの防止ができる効果がある。また、すべての集積回路
の高さを均一に半田付けできるので、熱伝導ブロックと
の微小間隔の形成が容易になり作業時間の短縮や、部材
費の低減を図ることができる。As described above, according to the present invention, by mounting an integrated circuit by using two kinds of solders having different melting points, the gap between the integrated circuit and the multilayer wiring ceramic substrate is maintained at an appropriate interval. This has the effect of preventing soldering open / short circuits. Further, since the heights of all the integrated circuits can be soldered uniformly, it is easy to form a minute gap between the integrated circuit and the heat conduction block, and it is possible to reduce the working time and the cost of members.
【図１】（ａ）および（ｂ）はそれぞれ本発明の一実施
例の断面図および半田付け部分の拡大断面図である。1A and 1B are a sectional view and an enlarged sectional view of a soldering portion of an embodiment of the present invention, respectively.
【図２】（ａ）及至（ｃ）は図１に示す実施例の半田付
けを工程順に示す図である。2 (a) to 2 (c) are views showing the soldering of the embodiment shown in FIG. 1 in the order of steps.
【図３】従来の集積回路の実装構造の断面図である。FIG. 3 is a cross-sectional view of a conventional integrated circuit mounting structure.
１ 集積回路 ２ 多層配線セラミック基板 ３ ピン ４ コールドプレート ５ 流路 ６ 冷媒 ７ 熱伝導ブロック ８ 枠 ９ 高温半田 １０ 低温半田 １１ 熱伝導性コンパウンド １２ 高温半田付用パッド １３ 低温半田付用パッド １４ おもり １５ 平板 １６ 治具 １７ 冷却部材 １８ ねじ 1 Integrated Circuit 2 Multilayer Wiring Ceramic Substrate 3 Pins 4 Cold Plate 5 Flow Path 6 Refrigerant 7 Thermal Conduction Block 8 Frame 9 High Temperature Solder 10 Low Temperature Solder 11 Thermal Conductive Compound 12 High Temperature Soldering Pad 13 Low Temperature Soldering Pad 14 Weight 15 Flat plate 16 Jig 17 Cooling member 18 Screw
Claims (1)
田接続する実装構造において、前記集積回路に設けられ
た複数の高温半田付用パッドを高温半田により前記多層
配線セラミック基板に設けられた高温半田付用パッドに
接続し、前記集積回路に設けられた複数の低温半田付用
パッドを低温半田により前記多層配線セラミック基板に
設けた低温半田付用パッドに接続したことを特徴とする
集積回路の実装構造。1. A mounting structure for soldering an integrated circuit to a multilayer wiring ceramic substrate, wherein a plurality of high temperature soldering pads provided on the integrated circuit are soldered to the multilayer wiring ceramic substrate by high temperature soldering. Mounting structure for an integrated circuit, characterized in that a plurality of low temperature soldering pads provided on the integrated circuit are connected to low temperature soldering pads provided on the multilayer wiring ceramic substrate by low temperature soldering. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15662792A JPH066009A (en) | 1992-06-16 | 1992-06-16 | Mounting structure of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15662792A JPH066009A (en) | 1992-06-16 | 1992-06-16 | Mounting structure of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH066009A true JPH066009A (en) | 1994-01-14 |
Family
ID=15631835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15662792A Withdrawn JPH066009A (en) | 1992-06-16 | 1992-06-16 | Mounting structure of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH066009A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245863B2 (en) | 2012-09-28 | 2016-01-26 | Samsung Electronics Co., Ltd. | Semiconductor packaging apparatus formed from semiconductor package including first and second solder balls having different heights |
-
1992
- 1992-06-16 JP JP15662792A patent/JPH066009A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245863B2 (en) | 2012-09-28 | 2016-01-26 | Samsung Electronics Co., Ltd. | Semiconductor packaging apparatus formed from semiconductor package including first and second solder balls having different heights |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |