JPH0659029B2 - PLL circuit for down converter - Google Patents

Description

The present invention relates to a down converter PLL circuit for extracting a clock in a down converter for converting a MUSE video signal into an NTSC video signal.

[Outline of Invention]

In the present invention, the signal output from the phase comparison circuit is
PW by a PWM circuit consisting of a counter and a size comparison circuit
It is converted into an M signal and supplied to the integrating circuit.

[Background technology]

FIG. 2 shows a so-called high-definition television having a large number of horizontal scanning lines, which is included in a digital signal in a down converter which receives a MUSE video signal and converts it into an NTSC video signal having a small number of horizontal scanning lines. 1 shows the configuration of a conventional PLL circuit for a down converter used when extracting a clock.

In the figure, reference numeral 1 is an A / D conversion circuit, which A / D converts an input TV signal of, for example, an analog MUSE system, and outputs the digital signal. The digital signal is supplied to a processing circuit (not shown) and down-converted into an NTSC video signal of the NTSC system having a smaller number of horizontal scanning lines.

Further, the digital signal is input to a PLL circuit including a phase comparison circuit 2, a D / A conversion circuit 3, an integration circuit (LPF) 4, a voltage controlled oscillation circuit 5 and a frequency divider circuit 6. The PLL circuit extracts the clock contained in the input digital signal and outputs it to the A / D conversion circuit 1.

[Problems to be Solved by the Invention]

In the conventional down converter PLL circuit, the digital error of the phase comparison circuit 2 is D / A converted by the D / A conversion circuit 3 and supplied to the integration circuit 4.
As a result, the D / A conversion circuit 3 is required, and the circuit configuration becomes simple, but digital systems and analog systems coexist, making it difficult to form an IC.

Therefore, the present invention realizes a down converter PLL circuit that can be digitally integrated into an IC.

[Means for Solving the Problems]

A down converter PLL circuit of the present invention is a down converter PLL circuit for extracting a clock in a down converter for converting a MUSE video signal into an NTSC video signal, and a phase of an input digital signal and a frequency-divided signal. , A phase comparison circuit that generates a clock, a generation circuit that generates a clock, a counter that counts the clock, a size comparison circuit that compares the output of the phase comparison circuit with the size of the output of the counter, and the output of the size comparison circuit is integrated. An integrating circuit, a voltage controlled oscillator circuit that generates a signal having a frequency corresponding to the output of the integrated circuit, and a divider circuit that divides the output of the voltage controlled oscillator circuit and outputs the divided signal.

[Action]

The output of the phase comparison circuit is input to the magnitude comparison circuit, and the magnitude of the output of the counter is compared. The counter repeats the clock counter between the first value and the second value. As a result, the output of the magnitude comparison circuit becomes a PWM signal corresponding to the digital error.

Therefore, the digital signal can be processed as it is, and the IC
Can be realized.

〔Example〕

FIG. 1 shows the configuration of a PWM circuit used in the PLL circuit of the present invention. This PWM circuit is connected between the phase comparison circuit 2 and the integration circuit 4 instead of the D / A conversion circuit 3 in FIG. In FIG. 1, 11 is a magnitude comparison circuit, which compares the output of the phase comparison circuit 2 and the output of the counter 13. The counter 13 counts clocks generated by the generation circuit 12. The output of the magnitude comparison circuit 11 is supplied to the integration circuit 4.

The operation will be described with reference to FIG. Generation circuit 1
2 generates a predetermined clock, and the counter 13 counts this clock. The counter 13 resets the count value to 0 when the clock counts up to 255, and repeats the count-up operation again (FIG. 3 (c)).

The phase comparison circuit 2 outputs, for example, 8 from the A / D conversion circuit 1.
Data in bits and 8 output from the frequency dividing circuit 6
The phase of the frequency-divided signal of the bit is compared digitally. Digital error signal output from the phase comparator 2 (see FIG. 3
(a) is input to the magnitude comparison circuit 11 and compared with the output of the counter 13. The magnitude comparison circuit 11 is the phase comparison circuit 2
When the output of is larger than the output of the counter 13, for example, a signal corresponding to the high level is output, and when it is smaller, the signal corresponding to the low level is output. That is, the magnitude comparison circuit 11 uses P corresponding to the error signal.
The WM signal (Fig. 3 (c)) is output.

The output of the magnitude comparison circuit 11 is integrated by the integration circuit 4 and then supplied to the voltage controlled oscillation circuit 5. The voltage controlled oscillator circuit 5 generates a clock having a frequency corresponding to the signal from the integration circuit 4. This clock is frequency-divided by the frequency dividing circuit and output to the phase comparison circuit 2.

As a result, the clock output from the frequency dividing circuit 6 corresponds to the signal included in the digital signal output from the A / D conversion circuit 1. This clock is supplied to the A / D conversion circuit 1 and used as a clock for the A / D conversion operation.

〔effect〕

As described above, according to the present invention, in the down converter, the output of the phase comparison circuit is supplied to the integration circuit as a PWM signal, so that the digital signal can be processed as it is, which is advantageous for digital integration. .

[Brief description of drawings]

1 is a block diagram of a PWM circuit used in the PLL circuit of the present invention, FIG. 2 is a block diagram of a conventional PLL circuit,
FIG. 3 is a waveform diagram of the circuit of FIG. 1 ... A / D conversion circuit 2 ... Phase comparison circuit 3 ... D / A conversion circuit 4 ... Integration circuit 5 ... Voltage controlled oscillation circuit 6 ... Dividing circuit 11 ... Size comparison circuit 12 ... Generation Circuit 13 ... Counter

Claims (1)

[Claims] 1. A down converter PLL circuit for extracting a clock in a down converter for converting an MUSE video signal into an NTSC video signal, the phase comparison comparing phases of an input digital signal and a divided signal. Circuit, generating circuit that generates clock, counter that counts clock, size comparison circuit that compares the output of the phase comparison circuit and the output of the counter, integration circuit that integrates the output of the size comparison circuit, and integration A PLL circuit for a down converter, comprising: a voltage-controlled oscillation circuit that generates a signal having a frequency corresponding to the output of the circuit; and a frequency-dividing circuit that divides the output of the voltage-controlled oscillation circuit and outputs the frequency-divided signal.