JP2539932B2 - MUSE-NTSC system converter - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MUSE-NTSC system converter, and more particularly to a PLL circuit that reproduces a resampling clock of a MUSE signal. [Prior Art] In high-definition broadcasting, MUSE, which was developed to send high-definition information that is more than 5 times that of NTSC broadcasting in one channel of satellite broadcasting, that is, multiple sub-nyst sampling encoding (Multiple Sub-ny
quist Sampling Encoding) is used for band compression. For this MUSE method, see NHK Technical Research (Sho 62, No. 39).
Volume 2, No. 172), "Development of MUSE Method". The MUSE transmission is sample value analog transmission, and it is basically that the sample values D / A converted by the encoder are accurately sampled without interfering with each other by the A / D conversion of the decoder. The condition that interference between sample values does not occur is known as Nyquist's first criterion. This means that the frequency characteristic of the transmission line is point-symmetrical at a position half the sampling frequency (16.2 MHz), that is, at 8.1 MHz, and the group delay characteristic is uniform within the band. FIG. 4 is a diagram for explaining the re-sampling condition. FIG. 4 (a) shows an original sample waveform, and FIG. 4 (b) shows the re-sampling condition in time series. .
Consider an impulse sampled with a circle as shown in FIG. When this is analog-transmitted, a solid line A is obtained.
The condition that this signal is resampled and returns to the impulse B marked with a circle is that the ringing frequency is equal to the sampling frequency.
When it coincides with 1/2, that is, when the zero crossing point of ringing is resampled. All signals are such impulses superimposed in time. This means that if one impulse satisfies the resample condition, waveform interference does not occur for all sample values. By the way, if the characteristic of FIG. 4 (b) is deviated, waveform interference between sample values occurs, which causes ringing interference on the screen, and the error rate of the audio signal deteriorates, and abnormal noise occurs. In order to ensure an accurate phase under such severe conditions, the MUSE method uses a horizontal period signal waveform as shown in FIG. Note that only the rising waveform is shown here. This horizontal sync signal has a level of 50% of the video, and its polarity is also inverted for each line. The reason for inverting each line is to cancel the DC component and avoid the influence of harmonic distortion. To regenerate the 16.2MHz resampling clock in a high-definition receiver, PLL (Phase locked Loop)
The horizontal synchronizing signal of FIG. 5 is used as the phase reference signal of this PLL. In the MUSE method, the midpoint of the horizontal sync signal waveform is specified to be resampled with respect to the resync phase of the horizontal sync signal. It is now assumed that the horizontal synchronizing signal is sampled at a clock of 16.2 MHz and the levels a, b, and c are obtained every other point as shown in FIG. At this time, the phase error is , So that this phase error becomes zero in PLL,
That is, the sampling phase is controlled so that the level b becomes the average value of the levels a and c. However, the sign of ± is inverted every 1H depending on the polarity of the horizontal synchronization signal. However, in order to construct a PLL in which the phase error is always zero using the equation (1), the loop gain in the low frequency band must be set to infinity. That is, the phase of the input waveform to the PLL is θ _i [rad], the phase of the output waveform reproduced by the PLL is θ ₀ [rad], the gain of the phase comparator is kφ [V / rad], and the VCO (voltage controlled oscillator) The free-running oscillation angular frequency is ω ₀ [rad / s], and its angular frequency modulation sensitivity is k _v
If [rad / sec / V] is set, the output oscillation angular frequency of the PLL in the steady state of the PLL is Can be expressed by When the frequency of the input waveform deviates from the free-running oscillation frequency of the VCO, feedback is applied so as to compensate by the product of the loop gain k _v · kφ and the steady phase error θ _i −θ ₀ . That is, in the steady state, k _v · k φ · (θ _i −θ ₀ ) = Const (3) holds, and in order to set the steady phase error θ _i −θ ₀ to 0, the loop gain k _v · k φ is ∞. Need to [Problems to be Solved by the Invention] In order to reliably realize transmission by the MUSE method as described above, the loop filter is configured by an ideal integrator, that is, a digital filter so that the low-frequency gain of the PLL becomes infinite. Must. However, this type of digital filter has the problems of large scale, complexity, and high cost. Therefore, if the equipment must be compact and inexpensive, the PLL using the above digital filter cannot be applied, and when converting HDTV to NTSC for viewing, waveform interference will occur even if some phase error occurs. Since it is difficult to understand the ringing interference on the screen due to, it is conceivable to use an analog filter. However, in this case, there is a problem in that performance with respect to temperature drift, power supply fluctuation, disturbance, etc. must be secured in order to gain gain with the phase error signal after D / A conversion. The present invention has been made to solve the above problems, and a PLL circuit that can realize a PLL control system for reproducing a resampling clock of a MUSE signal with a simple configuration without using a high-performance loop filter. With MUSE-N
The purpose is to obtain a TSC converter. In addition, the present invention prevents the steady phase error of the PLL from occurring.
You can easily adjust the offset of the circuit.
The purpose is to obtain a MUSE-NTSC converter with a simple L circuit configuration. [Means for Solving the Problem] A MUSE-NTSC system converter according to the present invention is a PLL circuit, which performs A / D conversion of a MUSE signal by a resampling clock, and calculates a phase error signal from a digital horizontal synchronization signal. 1 and the digital phase error signal D /
A signal processing is performed by an A converter and an analog filter, and a second circuit configuration section that regenerates the resampling clock by controlling a voltage controlled oscillator by an analog phase error signal of the filter output is further provided. A digital amplifying means for amplifying only the effective bit of the digital value phase error signal as a digital value is provided between the second circuit components. In addition, the PLL circuit is composed of the first and second circuits,
Further, an error detector for detecting a zero phase error value and a predetermined level before and after the zero phase error signal from the digital phase error signal is provided, and an offset adjuster for adjusting an offset voltage in the D / A converter and the loop filter. Is provided. [Operation] In the present invention, the circuit configuration part of the PLL circuit for generating the resampling clock based on the digital phase error signal is a D / A converter for the digital phase error signal, and an analog for processing the analog output thereof. A digital amplifying means for amplifying only the effective bit of the digital phase error signal as a digital value is provided in the preceding stage of the circuit configuration section, which comprises a filter and a VCO for regenerating the resampling clock by the output of the filter. As a result, the loop filter can be used as an analog filter to make the circuit configuration simple and inexpensive, and does not impose any burden on the analog system. Increase the loop gain without ensuring the performance for etc. You can In addition, the PLL circuit is configured to process the digital phase error signal with an A / D converter and a loop filter, and control the VCO with the obtained analog phase error signal to reproduce the resampling clock. Decoding the phase error signal, an error detecting means for detecting a phase error zero value and a predetermined level before and after the zero value and an offset adjuster for adjusting the offset voltage in the D / A converter and the loop filter are provided, If the PLL control system has a steady phase error, the offset of the PLL circuit can be easily adjusted. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining a PLL circuit of a MUSE-NTSC system converter according to an embodiment of the present invention. In the figure, 1 is an input terminal for a MUSE signal, and 2 is a resampling reproduced by a PLL. An A / D converter that samples the MUSE signal with a clock, and 3 are phase error detectors that calculate the phase error according to the above equation (1). From these A / D converter 2 and phase error detector 3, A first circuit configuration unit that calculates a digital phase error signal from the signal is configured. 4,5,6,7,10 are flip-flops that latch data by the resampling clock reproduced by the PLL,
12 is an 8-bit adder, 9 is the calculation result of adder 8 1/2
Bit shifter, 11 is an inverter that inverts the value latched in the flip-flop 10, and 13 is a flip-flop that holds the phase error signal obtained from the current horizontal sync signal until the next horizontal sync signal arrives. , 14 are line-inversion of the horizontal synchronizing signal, and therefore line-inversion of the phase error signal, and therefore EX-OR for obtaining a phase error signal of a constant polarity. The circuits 4 to 14 constitute the phase error detector 3. Further, reference numeral 15 is a multiplier for converting only the effective bit of the output signal of the phase error detector 3 into a digital value of 8 times by using a bit shifter or the like. Only the effective bit of the phase error signal of the above digital value is amplified as the digital value. It constitutes a digital amplifying means for 16 is a D / A converter for obtaining an analog phase error signal, 17 is a lag lead type loop filter of PLL, 18 is a D / A
An offset adjuster for correcting the offset voltage in the converter 16 and the loop filter 17, 19 is a VCO that oscillates a resampling clock (16.2 MHz), and 20 is an output terminal of the resampling clock. And the above D / A converter 1
The filter 17, the offset adjuster 18, and the VCO 19 constitute a second circuit configuration unit that reproduces the resampling clock of the MUSE signal based on the digital phase error signal. Further, 21 is a decoding circuit for decoding the digital phase error signal centering on the value of zero phase error and detecting the phase error zero and the values before and after it, 22 is the value of zero phase error

A display device for displaying [0] and values [−1] and [+1] before and after it, and 23 is a frame synchronization detection circuit for detecting the frame synchronization signal and determining the approximate position of the horizontal synchronization signal. Next, the operation will be described. The MUSE signal input from the input terminal 1 is converted into a digital signal by the A / D converter 2 and input to the phase error detector 3. The phase error detector 3 executes digital calculation according to the above equation (1). Flip-flops 4,5,6,7
Is latched by the resampling clock, so the point Pc in FIG.
When the data c comes, the data a at the point P _A four samples before is output to the output of the flip-flop 7. At this time, the data a and c at the points P _A and P _c are input to the adder 8, and the data a + c is obtained at the output. This data has a value of (a
+ C) / 2, which is once latched in the flip-flop 10. The flip-flop 10 plays a role of a pipeline memory as a countermeasure against a circuit delay generated in the adder 8 or the like. The output signal (a + c) / 2 of the flip-flop 10 is inverted by the inverter 11 and added with the data b at the point P _B output from the flip-flop 6 at the adder 12. The data b- (a + c) / 2 obtained by the adder 12 is held by the flip-flop 13 for one frame, has a constant polarity by the EX-OR 14, and is output as a 9-bit phase error signal.
Here, the latch timing in the flip-flop 13 is created by the frame synchronization detection circuit 23. FIG. 2 shows the relationship between the phase error value and the output of the phase error detector 3, which has a characteristic that the PLL can be accurately pulled in the range of −2π to 2π. However, it can be seen that, although the number of bits of the output signal is 9, the output signal varies only in the value of -32 to 32, that is, the effective number of bits is 6 bits. Therefore, a dynamic range is obtained through the multiplier 15 which converts this signal into a digital value (9 bits) of 8 times. Then, the phase error signal that has become an analog signal in the D / A converter 16 passes through a lag lead type loop filter 17 that maximizes the reduction gain and is input to the VCO 19. Here, the offset adjuster 18 can adjust the offset including the offset generated in the D / A converter 16 and the loop filter 17 so that the free-run frequency of the VCO 19 becomes a desired frequency. Since an analog filter cannot make a perfect integrator due to problems such as leakage and drift, the low-pass gain must be limited. Therefore, although the expression (3) cannot be satisfied with the gain that can be obtained by the analog filter, the phase error can be sufficiently suppressed by the MUSE-NTSC converter so that the ringing interference of the image cannot be detected. The resampling clock reproduced by the QVCO19 is transmitted from the clock output terminal 20 to each signal processing block of the MUSE-NTSC converter, and the A / D
It is fed back to the converter 2 and the PLL loop is established. In the decoder 21 and the display 22, the phase error is zero from the digital phase error signal.

When [0] is reached, and before and after that, [-1] and [+1] are displayed. The offset adjuster 18 can be easily adjusted by looking at this display. When the steady state of the PLL circuit to which such an offset voltage V _offset can be added is expressed by the above equation (2), Becomes The second term of the right type is in a state where the PLL is locked equation (3) _{Similarly, k v · {kφ · θ} i -θ 0) + V offset} = Const ... (5) Since k _v and k φ are constants, it can be seen that the offset voltage V _offset and the steady phase error θ _i −θ ₀ are proportional. FIG. 3 shows an example of measuring the stationary phase error and the bit error rate of the voice signal by varying the offset voltage. The horizontal axis shows the steady phase error value by the angle (degree) and the digital value of the output of the phase error detector 3 in FIG. The speech error rate on the vertical axis shows what was measured using the decoding result of the error correction code of the MUSE speech signal and further converted into the bit error rate. The curve in this figure changes depending on the S / N of the input MUSE signal. Judging from Fig. 3, the error rate is the best when the digital phase error signal is 0, that is, when the phase error is zero. Recognize. Since the offset voltage V _offset and the steady phase error θ _i −θ ₀ are proportional to each other, the digital phase error display [−1],

[0],
The offset adjuster 18 may be adjusted so that the phase error becomes zero while observing [1]. Thus, in this embodiment, the digital phase error signal is
The D / A converter 16 and the analog filter 17 perform signal processing to obtain an analog phase error signal, and the VCO 19 regenerates the resampling clock based on the analog phase error signal, and in the preceding stage of the D / A converter 16. , A multiplier 15 for converting only the effective bit of the digital phase error signal into an eightfold digital value by using a bit shifter or the like, and
Since the phase error information can be obtained over the full dynamic range of the A converter 16, the loop filter can be used as an analog filter and the PLL circuit configuration can be made simple and inexpensive. The loop gain can be increased without ensuring the performance against temperature drift, power supply fluctuation, disturbance, etc., which is required when the loop gain is gained by the error signal. Further, while providing an offset adjuster 18 for adjusting the offset voltage in the D / A conversion 16 and the loop filter 17, the digital phase error signal is decoded, and the phase error zero and the values before and after the phase error [−1], [ Since the decode circuit 21 for detecting +1] and the phase error display 22 for displaying these values are provided, the offset adjustment of the analog system can be easily performed while observing the error display. In the above embodiment, the offset adjustment was manually performed while observing the phase error display, but the decoding result of the phase error, that is, the output signal of the decoder 21 is fetched into the microcomputer or the like, and arithmetic averaging or the like is performed by calculation. A system in which the offset adjuster 18 is adjusted by a D / A converter or the like built in the microcomputer may be used. Of such a system
If a microcomputer is used in the entire MUSE-NTSC converter, diversion of this microcomputer will not increase the hardware scale. This is equivalent to raising the low-frequency gain by using a kind of digital filter, and can further improve the performance. [Effects of the Invention] As described above, according to the MUSE-NTSC system converter according to the present invention, the circuit configuration unit that generates the resampling clock based on the digital phase error signal of the PLL circuit is D / A converter, an analog filter for signal processing the analog output, and a VCO for reproducing the resampling clock by the filter output
Further, since the digital amplifying means for amplifying only the effective bit of the digital phase error signal as a digital value is provided in the preceding stage of the circuit configuration section, the circuit configuration is simple and inexpensive as an analog filter. It can be done, and does not burden the analog system at all,
That is, the loop gain can be increased without ensuring the performance against temperature drift, power supply fluctuation, disturbance, etc., which is required when the loop gain is gained by the analog phase error signal. This makes it possible to obtain an inexpensive MUSE-NTSC converter with a small PLL circuit scale and sufficient performance. According to the MUSE-NTSC converter of the present invention,
The PLL circuit is configured to process the digital phase error signal with an A / D converter and a loop filter, and control the VCO with the obtained analog phase error signal to reproduce the resampling clock. Since the error detection means for decoding the signal and detecting the phase error zero value and the predetermined level before and after it and the offset adjuster for adjusting the offset voltage in the D / A converter and the loop filter are provided, the PLL If there is a steady phase error of, there is an effect that the offset of the PLL circuit can be easily adjusted.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit of a MUSE-NTSC converter according to an embodiment of the present invention, FIG. 2 is a diagram showing input / output characteristics of a phase error detector, and FIG. 3 is a steady phase error and voice. FIG. 4 is a diagram showing the relationship with the signal bit error rate, FIG. 4 is a diagram for explaining the principle of sampled value analog transmission, and FIG. 5 is a waveform diagram of a horizontal synchronizing signal. 2 ... A / D converter, 3 ... Phase error detector, 15 ... Digital multiplier (digital amplification means), 16 ... D / A converter, 17 ...
Loop filter, 18 ... Offset adjuster, 19 ... VCO, 21
... Decoding circuit (error detection display means), 22 ... Display (error detection display means). The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. The MUSE signal is A / D by a resampling clock.
A first circuit configuration unit that converts and calculates a phase error signal from a horizontal synchronization signal that has been converted into a digital value, and the phase error signal is converted into an analog phase error signal and input to a voltage controlled oscillator through a loop filter. Then, in a MUSE-NTSC converter having a PLL circuit composed of a second circuit configuration section for regenerating the resampling clock by the voltage controlled oscillator, between the first and second circuit configuration sections of the PLL circuit. A MUSE-NTSC system converter characterized by comprising digital amplifying means for amplifying only the effective bit of the phase error signal of the digital value as it is as a digital value. 2. The MUSE signal is A / D by a resampling clock.
A first circuit component that converts and calculates a phase error signal from the horizontal synchronizing signal converted into a digital value, and the phase error signal is processed by a D / A converter and a loop filter and input to a voltage controlled oscillator. Then, in the MUSE-NTSC system converter having a PLL circuit composed of the second circuit configuration section for regenerating the resampling clock by the voltage controlled oscillator, a phase error zero value from the phase error signal of the digital value The MUSE-NTSC system converter comprising: an error detecting means for detecting a predetermined level of 1. and an offset adjusting means for adjusting an offset voltage in the D / A converter and the loop filter.