JPH04349796A - Timing detection circuit - Google Patents

Abstract

PURPOSE:To detect a stable SC-H phase with excellent matching even in a digital signal processing circuit by providing a 2nd phase detection means detecting a phase of a color burst signal from an output signal of a coding means and outputting its phase information to the detection circuit. CONSTITUTION:A synchronizing phase detection circuit 2 detects an amplitude Vs of a synchronizing signal at first to detect a reference timing of a synchronizing signal and obtains a level of Vs/2. Then a point where a trailing edge of the synchronizing signal crosses the level of Vs/2 is obtained by interpolation or the like from sampled values and a data representing a phase of a timing with respect to a sampling phase is outputted. A chrominance subcarrier phase detection circuit 3 obtains the amplitude of a color burst in orthogonal sampling phases from a sample data string of a color burst. A phase difference detection circuit 4 compares an output of the circuit 2 with an output of the circuit 3 to detect the SC-H phase.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more particularly to a timing detection circuit suitable for converting an analog composite video signal into a digital signal for processing.

0002

2. Description of the Related Art The waveform of a composite video signal varies depending on the standard of the television signal. The relationship between frequencies is such that 2 frames are required for the NTSC standard, and 4 frames are required for the PAL standard. That is, the synchronization signal is completed in one frame, but the color subcarrier is completed in two to four frames, and the frame in which the color subcarrier is completed is called a color frame. The phase relationship between the color subcarrier and the synchronization signal is called SC-H and is defined in each television signal standard.

When processing such a composite video signal, it is necessary to create various timing signals necessary for processing using reference information of color subcarriers, that is, color burst signals, and synchronization information. In particular, when determining the color frame mentioned above, the phase or polarity of the color subcarrier relative to the synchronization signal must be detected. However, if the SC-H of the input composite video signal deviates significantly due to the characteristics of the transmission path or output device, the correct phase or polarity of the color subcarrier with respect to the synchronization signal cannot be detected, making it difficult to distinguish between color frames. There is a possibility of making a mistake. Therefore, the amount of SC-H in the incoming composite video signal is detected, the amount is displayed to the user, and the phase of the synchronization signal and color subcarrier is corrected according to the amount of detected SC-H. A method is being considered in which the color frame is determined after

An example of an SC-H detection circuit used for the above purpose is shown in US Pat. No. 4,860,089. A block diagram of a conventional SC-H detection circuit is shown in FIG. In FIG. 10, the analog composite video signal input from the terminal (50) is input to the synchronization extraction circuit (51).
) and a color burst extraction circuit (52). The synchronization extraction circuit (51) extracts only the synchronization signal component from the analog composite video signal and converts it into a binary digital signal (SYN).
C) and output to the phase difference detection circuit (54). The color burst extraction circuit (52) extracts only the color burst signal component from the analog composite video signal, converts it into a binary digital signal, and outputs it to the subcarrier reproduction circuit (53). The subcarrier regeneration circuit (53) generates a continuous clock (fsc) that is phase-synchronized with the color burst signal using a phase-locked loop (PLL) circuit or the like, and outputs it to the phase difference detection circuit (54). The phase difference detection circuit (54) receives SYNC, which is the output signal of the synchronization extraction circuit (51),
fsc which is the output signal of the subcarrier regeneration circuit (53)
Detect the phase relationship of and send data indicating the amount of SC-H to the terminal (
55).

FIG. 11 is a block diagram of a conventional example of a phase difference detection circuit (54). The terminal (56) receives SYNC, which is the output signal of the synchronization extraction circuit (51), and the terminal (57) receives fs, which is the output signal of the subcarrier regeneration circuit (53).
c is input. The phase adjustment circuit (58) fixedly or adaptively adjusts the phase of SYNC with respect to fsc and outputs it to the pulse generation circuit (59). Pulse generation circuit (
59) generates a pulse with a width from the falling edge of phase adjusted SYNC to the rising or falling edge of fsc. Normally, when the SC-H of the input video signal is appropriate, the phase adjustment circuit (
58). The integrating circuit (60) integrates the output pulse waveform of the pulse generating circuit (59), converts it into a voltage value, and outputs the voltage value to the encoding circuit (62). An integration circuit (60) is connected from the terminal (61) to integrate the next pulse waveform.
) is input with a pulse to clear the integral value. The encoding circuit (62) encodes the integration result of the integrating circuit (60) and outputs data representing SC-H to the terminal (55).

FIG. 12 shows signal waveforms at various parts of the phase difference detection circuit shown in FIG. 11. In FIG. 12,
Waveform (a) is the SYNC signal input from the terminal (56), waveform (b) is the output signal of the phase adjustment circuit (58), and waveform (c
) is the fsc input from the terminal (57), waveform (d) is the output signal of the pulse generation circuit (59), waveform (e) is the clear signal input from the terminal (61), and waveform (f) is the integration circuit. (60) is the output signal.

[0007]

[Problems to be Solved by the Invention] In conventional SC-H detection means, even in the case of proper SC-H, the pulse width is narrow, at most several tens of nanoseconds, and when converting the pulse width into voltage, noise and circuit component accuracy, temperature drift, leakage current,
It was easily affected by the amplifier's offset current, etc. Furthermore, if the pulse width becomes narrower in accordance with the SC-H of the incoming composite video signal, the effects of circuit delay and edge change time cannot be ignored, making it difficult to detect SC-H with stability and good linearity. There was a problem.

[0008] In particular, in devices that convert analog composite video signals into digital signals for processing, SC-
Since the H detection circuit is mixed with the digital signal processing circuit, it is easily affected by noise from the digital signal processing circuit, and measures to prevent the influence of such noise, such as magnetic and electrostatic It is necessary to take measures such as shielding and separating the power supply and ground lines from the digital circuit system, which complicates the design of the entire system. SUMMARY OF THE INVENTION It is an object of the present invention to provide a timing detection circuit that improves the above-mentioned problems, has good consistency even in a digital signal processing circuit, and is capable of stable SC-H detection.

[0009]

[Means for Solving the Problems] In order to solve the above problems, the timing detection circuit according to the present invention provides an encoding means (1 ), and the encoding means (1
), which detects the reference phase of the synchronization signal from the output signal of the encoder (2) and outputs the phase information, and detects the phase of the color bust signal from the output signal of the encoder (1). A second phase detection means (3) that outputs phase information of the above-mentioned phase detecting means (3) calculates a position by calculating the phase information of the first phase detection means (2) and the phase information of the second phase detection means (3). and means (4) for obtaining phase difference information.

0010

In the present invention, after converting an analog composite video signal into a digital signal, SC-H is detected by calculating the phase relationship between the synchronizing signal and the color subcarrier by numerical calculation. Therefore, SC-H can be detected stably and with good linearity without being affected by the amount of SC-H of an incoming composite video signal or the performance of circuit components such as temperature drift. Furthermore, since it is not affected by noise and can be easily integrated into a circuit, it has the advantage of being very compatible with devices that perform digital signal processing.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a timing detection circuit according to an embodiment of the present invention, in which (5) is an input terminal for an analog composite video signal, and (1) is an A/D for converting the analog composite video signal into a digital signal. The conversion circuit (2) is A/
The synchronization phase detection circuit (3) calculates the reference timing for synchronization from the output signal of the D conversion circuit (1) (hereinafter referred to as digital composite video signal) by digital calculation and outputs the result. Color subcarrier phase reference, for example, a color subcarrier phase detection circuit that detects and outputs the phase from the data of the color burst part by digital calculation, (4) is the output signal of the synchronous phase detection circuit (2) and the color subcarrier phase A phase difference detection circuit detects the phase difference between the output signal of the detection circuit (3) by digital calculation, and (6) is an output terminal that outputs the signal from the phase difference detection circuit (4).

FIG. 2 shows an example of the relationship between the synchronization signal and the color burst signal specified in the television signal standard. In FIG. 2, the NTSC studio standard will be explained as an example. In FIG. 2, waveform (a) shows the horizontal synchronization signal and color burst portion of the composite video signal, and waveform (b) shows the color subcarrier having the same phase as the color burst. Since the frequency of the color subcarrier is 227.5 times the horizontal line frequency, there are two horizontal lines in which the phase of the color burst is shown by a solid line and one shown by a broken line. The phase of the color burst is opposite to the modulation phase of the BY signal, which is a color difference signal. Timing T0, which serves as a reference for the synchronization signal, is given at the timing when the falling edge waveform of the synchronization signal passes through a level that is 1/2 of the amplitude Vs of the synchronization signal. Furthermore, the interval between timing T0 and timing T1 at which the color burst starts is 19 cycles in the color subcarrier period, and at timing T0, the waveform (b
) The phase of the color subcarrier shown in ) is 0 degrees or 1 of the sine wave phase.
It will be 80 degrees. Therefore, the state shown in FIG. 2 is a case where SC-H is 0 degrees. The amount by which the phase of the color subcarrier at timing T0 deviates from the state in Figure 2 becomes the phase amount of SC-H, but if it deviates by 90 degrees, determine whether it is 0 degrees plus 90 degrees or 180 degrees minus 90 degrees. Can not. Therefore, SC-H only takes values from plus 90 degrees to minus 90 degrees. In addition, the phase of the color subcarrier in each horizontal line of each field is determined by the standard, so
A color frame can be determined by detecting whether the phase of the color subcarrier at timing T0 is 0 degrees or 180 degrees in one or more specific horizontal lines.

The operation when the above composite video signal is input to the timing detection circuit shown in FIG. 1 will be explained. In FIG. 1, the synchronization phase detection circuit (2) first detects the amplitude Vs of the synchronization signal and determines the level of Vs/2 in order to detect the reference timing T0 of the synchronization signal. Next, the point at which the falling edge of the synchronizing signal passes through the level of Vs/2 is determined by interpolating sample values, etc., and data indicating the phase of timing T0 with respect to the sampling phase is output. The color subcarrier phase detection circuit (3) determines the amplitude of the color burst at mutually orthogonal sampling phases from the color burst sample data sequence. Phase difference detection circuit (
4) compares the output of the synchronous phase detection circuit (2) and the output of the color subcarrier phase detection circuit (3) to detect the SC-H phase.

FIG. 3 shows an embodiment of the synchronous phase detection circuit (2). In FIG. 3, (45) is a level detection circuit that detects the reference level of the synchronization signal, including a pedestal level detection circuit (8) and a sync level detection circuit (1).
0), an adder circuit (12), and a divider circuit (13). The digital composite video signal input from the terminal (7) is first input to the pedestal level detection circuit (8) and the sync level detection circuit (10). The pedestal level detection circuit (8) holds the data of the pedestal portion in accordance with the pulse indicating the pedestal timing input from the terminal (9). On the other hand, the sync level detection circuit (10) holds the data of the sync bottom portion in accordance with the pulse indicating the timing of the bottom of the sync signal inputted from the terminal (11). The output data value V1 of the pedestal level detection circuit (8) and the sync level detection circuit (1)
After the output data value V2 of 0) is added by an adder circuit (12), the level is halved by a divider circuit (13). If the output data value of the division circuit (13) is Vc, then (V1+V
2) By calculating /2, a level Vc which is 1/2 of the amplitude of the synchronizing signal can be obtained. In the interpolation circuit (14), the terminal (
7), interpolate between sample values D1 and D2 before and after sandwiching the output data value Vc of the division circuit (13), and find out where the timing to apply Vc is between the sampling timings of D1 and D2. , terminal (15)
Output to.

A method for performing the above interpolation by linear approximation will be explained using a schematic waveform diagram shown in FIG. Vc
When sample values D1 and D2 close to each other are connected by a straight line, the timing at which data Vc is provided is defined as Tc. Also, consider normalizing the sampling period to 1. In this case, the relationship between Tc, D1, D2, and Vc is as follows:
It is expressed as a proportional relationship.

[0016]

[Math 1]

[0017] Therefore, Tc is determined by the following equation.

[0018]

[Math 2]

FIG. 5 shows an embodiment of the interpolation circuit 14 in which Tc is determined by interpolation using the above calculation. In FIG. 5, the digital composite video signal inputted from the terminal (7) is adjusted in timing with the output data of the division circuit (13) inputted from the terminal (20) by a timing adjustment circuit (17). By delaying the output of the timing adjustment circuit (17) by one sample in the delay circuit (18), when data D2 is output to the output of the timing adjustment circuit (17), data D1 is output to the output of the delay circuit (18). will be output. An adder circuit (19) subtracts data D2 from data D1 and outputs the result to a divider circuit (22). Further, the adder circuit (21) inputs the data D1 to the terminal (
20) and outputs it to the division circuit (22). The division circuit (22) is (D1-Vc)/(D1-
D2) is performed and the result is output to the terminal (15). In the above embodiment, a case has been described in which interpolation is performed by linear approximation, but other interpolation methods such as quadratic interpolation or interpolation using a digital filter may be used.

Next, an embodiment of the color subcarrier phase detection circuit (3) in FIG. 1 is shown in FIG. In FIG. 6, a digital composite video signal sampled at a frequency four times that of the color subcarrier is input from a terminal (23). Delay circuits (24), (25), and (26) delay data of the color burst portion of the digital composite video signal by one sample. As a result, four consecutive color burst data strings are obtained. Here, the output data value of the delay circuit (26) is A, the output data value of the delay circuit (25) is B, the output data value of the delay circuit (24) is C, and the output data value of the terminal (23) is D. do. The adder circuit (27) is a delay circuit (
The output data value of the delay circuit (24) is subtracted from the output data value of the delay circuit (26), that is, the calculation of A-C is performed, and the result Y is outputted to the terminal (29). The adder circuit (28) subtracts the output data value of the terminal (23) from the output data value of the delay circuit (25), that is, performs a calculation of B-D, and outputs the result X to the terminal (30). The output value Y of the adder circuit (27) and the output value X of the adder circuit (28) become mutually orthogonal sample phase components of the color burst. Here, the DC component at the pedestal level can be removed by taking the difference between the data values for every other sample.

The synchronous phase detection circuit (
2) Output data Tc and color subcarrier phase detection circuit (3)
An embodiment of the phase difference detection circuit (4) that detects the SC-H phase using the output data X and Y of is described. In FIG. 7, (a) is a waveform diagram when a color burst portion is sampled, and (b) is a vector representation of the relationship between the color burst and the sampling phase. Sample values A, B, C, and D correspond to the output data values of the delay circuit (26), delay circuit (25), delay circuit (24), and terminal (23), respectively. A-
The result of C, that is, the output value of the adder circuit (27), is expressed as Y, B-
Assuming that the result of D, that is, the output value of the adder circuit (28) is X, as is clear from the vector diagram (b), the color burst phase P with respect to the sampling phase can be obtained by calculating the trigonometric function shown in Equation 3.

[0022]

[Math 3]

[0023] The phase obtained by equation 3 is from -90 degrees to +
The range is up to 90 degrees. In order to find the relative phase between the synchronization signal phase Tc and the color burst phase P with respect to the sampling phase, in vector diagram (b), rotate the coordinate axes x and y by Tc around the origin, and then What is necessary is to find the amplitude components X' and Y'. This can be realized using the linear transformation formula of the matrix shown in Equation 4.

[0024]

[Math 4]

In Equation 4, the unit of phase is degree.
e) is used. In order to obtain the SC-H phase P' from X' and Y' obtained from Equation 4, the trigonometric function shown in Equation 5 may be calculated.

[0026]

[Math 5]

FIG. 8 shows a block diagram of an embodiment of the phase difference detection circuit 4 which obtains the SC-H phase by calculations of Equations 4 and 5. In FIG. 8, phase data Tc of a synchronizing signal inputted from a terminal (32) is inputted to an arithmetic circuit (34) and an arithmetic circuit (35). The arithmetic circuit (34) calculates SIN90Tc in Equation 4. Similarly, the calculation circuit (35) performs the calculation of COS90Tc in Equation 4. Output data X and Y of the color subcarrier phase detection circuit (3) are input to the terminal (31) and the terminal (33), respectively. Multipliers (36), (37), (38)
, (39) and adders (40), (41) perform matrix operations on data X, data Y, output data of the arithmetic circuit (34), and output data of the arithmetic circuit (35).
40) outputs data X', and the adder (41) outputs data Y'. The arithmetic circuit (42) receives data X',
Using Y' as input, perform the calculation shown in Equation 5 to obtain SC-H.
Output the phase data to the terminal (43). Arithmetic circuit (34
) and (35) can be easily realized by using a memory circuit that uses input data Tc as an address and stores the calculation result corresponding to Tc at that address. Similarly, the arithmetic circuit (42) can be easily realized by using a memory circuit whose address is a combination of data X' and Y'.

FIG. 9 shows a block diagram of another embodiment of the phase difference detection circuit (4) for determining the SC-H phase by calculations of Equations 4 and 5. In Figure 9, a memory with a large capacity (44
), the combination of data X, Y, and Tc is used as an address, and the calculation result P' obtained from the data X, Y, and Tc is stored in advance in that address. is obtained. The output data Tc of the synchronous phase detection circuit (2) and the color subcarrier phase detection circuit (
3) The means for detecting the SC-H phase using the output data Nothing has changed.

Furthermore, although the sampling frequency used in the embodiments described above is four times the color subcarrier frequency, it may be any frequency that allows the orthogonal phase components of the color burst to be obtained. Any frequency that is a multiple of 2 is sufficient. In the above embodiments, the operation of a timing detection circuit using an NTSC signal as an input signal has been described, but it can be applied in exactly the same way to other television signal systems such as a PAL signal, and the effects of the present invention will not change in any way. However, there is no such thing.

[0030]

[Effects of the Invention] According to the present invention, the SC is stable and has good linearity without being affected by temperature drift or accuracy of circuit components.
-H can be detected. Another advantage is that it is not affected by noise and has very good compatibility with devices that perform digital signal processing. Furthermore, since it is easy to integrate the circuit and eliminate adjustment, the device can be made smaller, more reliable, and lower in cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a timing detection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the relationship between a synchronization signal and a color subcarrier of a composite video signal.

FIG. 3 is a block diagram of a synchronous phase detection circuit according to an embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining an interpolation method of the synchronous phase detection circuit according to the present invention.

FIG. 5 is a block diagram of an interpolation circuit according to an embodiment of the invention.

FIG. 6 is a block diagram of a color subcarrier phase detection circuit according to an embodiment of the present invention.

FIG. 7 is a diagram for explaining the principle of color burst phase detection according to the present invention.

FIG. 8 is a block diagram of a phase difference detection circuit according to an embodiment of the present invention.

FIG. 9 is a block diagram of a phase difference detection circuit according to another embodiment of the present invention.

FIG. 10 is a block diagram of a conventional timing detection circuit.

FIG. 11 is a block diagram of a phase difference detection circuit in a conventional timing detection circuit.

FIG. 12 is an operation waveform diagram of a phase difference detection circuit in a conventional timing detection circuit.

[Explanation of symbols]

1...A/D conversion circuit, 2...Synchronized phase detection circuit, 3...color subcarrier phase detection circuit, 4...phase difference detection circuit, 14...Interpolation circuit, 45...Level detection circuit.

Claims (4)

[Claims] 1. A circuit that receives as input a composite video signal consisting of at least a synchronization signal and a color burst signal, and detects the phase relationship between the synchronization signal and the color burst signal, wherein the composite video signal is detected at a color subcarrier frequency. An encoding means (1) that samples and quantizes the sampled and quantized data at an even multiple of the frequency and outputs it as code data; and an encoder (1) that interpolates the output signal of the encoding means (1) to detect a phase that becomes a reference for a synchronization signal. a first phase detection means (2) for outputting information; and a second phase detection means (3) for detecting the phase of the color burst signal from the output signal of the encoding means (1) and outputting the phase information.
), and means for calculating the phase information of the first phase detection means (2) and the phase information of the second phase detection means (3) and outputting phase difference information between the synchronization signal and the color burst signal (
4) A timing detection circuit comprising: 2. The first phase detection means (2) includes means (45) for detecting a threshold value to be a phase reference of the synchronization signal, and a code at the same time as the synchronization signal passes the threshold value or before and after the synchronization signal passes the threshold value. 2. The timing detection circuit according to claim 1, further comprising means (14) for interpolating a waveform including the threshold value from the data and detecting the phase of the threshold value from the interpolated waveform. 3. The interpolation method is characterized in that the interpolation method is linear interpolation between code data at the same time or immediately before the synchronization signal passes the threshold value and code data at the same time or immediately after the synchronization signal passes the threshold value. The timing detection circuit according to claim 1 or claim 2. 4. The second phase detection means (3) comprises means for separating the code data string of the color burst signal into sets of mutually orthogonal sampling phases and obtaining amplitude data for each set. The timing detection circuit according to claim 1.