JPH0658923B2 - Mounting method of semiconductor chip - Google Patents

Mounting method of semiconductor chip

Info

Publication number
JPH0658923B2
JPH0658923B2 JP62027908A JP2790887A JPH0658923B2 JP H0658923 B2 JPH0658923 B2 JP H0658923B2 JP 62027908 A JP62027908 A JP 62027908A JP 2790887 A JP2790887 A JP 2790887A JP H0658923 B2 JPH0658923 B2 JP H0658923B2
Authority
JP
Japan
Prior art keywords
chip
substrate
solder
conductor
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62027908A
Other languages
Japanese (ja)
Other versions
JPS63194342A (en
Inventor
実 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62027908A priority Critical patent/JPH0658923B2/en
Publication of JPS63194342A publication Critical patent/JPS63194342A/en
Publication of JPH0658923B2 publication Critical patent/JPH0658923B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、はんだバンプを有する半導体チップをセラミ
ックなどの絶縁基板の両面に取り付け、バンプを基板上
の導体部と接続するフリップチップ方式の半導体チップ
の実装方法に関する。
The present invention relates to a flip-chip type semiconductor in which semiconductor chips having solder bumps are mounted on both sides of an insulating substrate such as ceramic and the bumps are connected to conductor portions on the substrate. Regarding a chip mounting method.

〔従来の技術〕[Conventional technology]

半導体チップのはんだバンプを絶縁基板上の少なくとも
表面がはんだよりなる導体部に位置合わせし、はんだを
リフローさせて融着するフリップチップ方式はよく知ら
れている。第2図はそのような実装方法の一例を示し、
セラミック基板1上にはんだペーストを印刷して導体部
2を形成し、この上にチップ3をはんだバンプ4のある
面を下向きにして載せ、バンプ4が導体部2に接するよ
うにしたのち、加熱炉に入れてはんだをリフローさせて
融着する。この場合、導体部2とバンプ4の位置が多少
ずれていても、はんだの表面張力によって接続が行われ
るセルフアライン機能がある。
A flip chip method in which a solder bump of a semiconductor chip is aligned with a conductor portion of which at least a surface on an insulating substrate is made of solder, and the solder is reflowed and fused is well known. FIG. 2 shows an example of such a mounting method,
Solder paste is printed on the ceramic substrate 1 to form the conductor portion 2, and the chip 3 is placed on the ceramic substrate 1 with the surface having the solder bumps 4 facing downward so that the bumps 4 are in contact with the conductor portion 2 and then heated. Place in furnace to reflow solder and fuse. In this case, even if the positions of the conductor portion 2 and the bump 4 are slightly deviated from each other, there is a self-aligning function in which the connection is performed by the surface tension of the solder.

高密度実装のために基板の両面にチップを実装する場合
には、絶縁基板両面に融点の異なるはんだを用いて導体
部を形成する。すなわち、先ず高融点のはんだのペース
トを用いて基板の一面に導体部を形成したのちチップを
載せ、リフロー炉においてチップのバンプと導体部を融
着させる。次に基板の他面に低融点のはんだのペースト
を用いて導体部を形成し、その面を上にしてその上にチ
ップを載せ、最初に用いたリフロー炉より温度の低いリ
フロー炉において他面側の導体部とチップのバンプとを
融着させる。
When chips are mounted on both sides of the substrate for high-density mounting, conductors are formed on both sides of the insulating substrate by using solders having different melting points. That is, first, a conductor portion is formed on one surface of a substrate by using a high melting point solder paste, and then a chip is mounted, and a bump of the chip and the conductor portion are fused in a reflow furnace. Next, a conductor part is formed on the other surface of the board using a low melting point solder paste, and the chip is placed on that surface with the surface facing up, and the other surface is used in the reflow furnace whose temperature is lower than that of the first reflow furnace. The conductor portion on the side and the bump of the chip are fused.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

このような両面実装方法には次の問題がある。 Such a double-sided mounting method has the following problems.

(1)2種類のはんだペーストおよびリフロー炉が必要で
ある。
(1) Two kinds of solder paste and reflow oven are required.

(2)工程時間が長い。(2) The process time is long.

(3)高融点のはんだが使用される側の基板面には、耐熱
性の低い他の電子部品、例えばコンデンサ,抵抗などを
実装することができない。
(3) Other electronic parts having low heat resistance, such as capacitors and resistors, cannot be mounted on the surface of the substrate where the high melting point solder is used.

本発明の目的は、上述の問題を解決し、低融点のはんだ
のみを使用して1回のリフロー工程で同時に基板の両面
にチップを実装することのできる半導体チップの実装方
法を提供することにある。
An object of the present invention is to solve the above problems and provide a semiconductor chip mounting method capable of mounting chips on both surfaces of a substrate at the same time in a single reflow process using only low melting point solder. is there.

〔問題点を解決するための手段〕[Means for solving problems]

上記の目的を達成するために、本発明の方法は、絶縁基
板の両面にそれぞれ少なくとも表面層が同一材料のはん
だよりなる導体部を形成し、チップ支持治具の位置決め
用の凹部内に基板の面に実装されるチップを1個ずつ収
容してチップ下面中央を支持し、チップ支持治具上に前
記基板を載せてその一面の導体部を支持治具内の各チッ
プのバンプに近接ないし接触させ、次いで基板の他面上
に他のチップを載せて他面の導体部に各チップのバンプ
を近接ないし接触させ、しかるのちリフロー炉中におい
て導体部とバンプとを融着させるものとする。
In order to achieve the above-mentioned object, the method of the present invention comprises forming conductor portions on both surfaces of an insulating substrate, at least surface layers of which are made of solder of the same material, and the substrate is provided in a positioning recess of a chip supporting jig. Each chip mounted on the surface is housed one by one to support the center of the lower surface of the chip, the substrate is placed on the chip supporting jig, and the conductor portion on the one surface is close to or in contact with the bump of each chip in the supporting jig. Then, another chip is placed on the other surface of the substrate, the bumps of each chip are brought into close proximity to or in contact with the conductor portion on the other surface, and then the conductor portion and the bump are fused in a reflow furnace.

〔作用〕[Action]

絶縁基板の両面に形成された少なくとも表面が同一材料
のはんだよりなる導体部には、下面では治具の位置決め
用凹部内に収容されたチップ、上面には上に載せられた
チップのはんだバンプがそれぞれ接触ないし近接してい
るので、はんだのリフローによって一回の加熱で両面に
おいてチップのバンプと導体部とを融着させることがで
き、高温のはんだおよび高温のリフロー炉を用いる必要
がない。
The conductor part formed on both sides of the insulating substrate, at least the surface of which is made of solder of the same material, has the chip accommodated in the positioning recess of the jig on the lower surface and the solder bump of the chip placed on the upper surface. Since they are in contact with each other or close to each other, the bumps of the chip and the conductor portion can be fused on both surfaces by one heating by reflowing the solder, and it is not necessary to use high temperature solder and high temperature reflow furnace.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示し、第2図と共通の部分
には同一の符号が付されている。チップ支持治具5は凹
部6を有し、この凹部6は、その中に収容された半導体
チップ3は凹部底面中央の支持体7に支えられ、上面の
はんだバンプ4が絶縁基板1の下面にはんだペーストの
印刷により形成された導体部2に接触するような位置に
設けられている。基板1の上面には、下面と同時にはん
だペーストの印刷により形成された導体部2の上に、バ
ンプ4が接触するようにチップ3が載せられている。こ
のように配置された基板1およびチップ3をチップ支持
治具5と共にリフロー炉に入れて加熱することにより、
各チップのバンプ4と上下両面の導体部2が融着する。
支持治具5には基板1の周辺の下側に段部8が形成さ
れ、リフローの際基板1が低下し過ぎて融着部がつぶさ
れるのを防ぐ。リフロー前にすべてのバンプ4と導体部
2が接触していなくても、リフロー時のはんだの変形に
よって接触し、セルフアライン機能を伴って正常な位置
での各バンプ4と導体部2の接続が行われる。下面側の
チップ3はそれぞれ支持体7により中央部の1点のみで
支えられているので、セルフアライン機能の働く際のチ
ップの変位が妨げられることがない。但し、凹部6の幅
はチップ3の寸法より100μm大きい程度にとどめる。
FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. The chip supporting jig 5 has a concave portion 6, the semiconductor chip 3 housed therein is supported by a support 7 at the center of the concave bottom surface, and the solder bumps 4 on the upper surface are on the lower surface of the insulating substrate 1. It is provided at a position where it comes into contact with the conductor portion 2 formed by printing the solder paste. The chip 3 is placed on the upper surface of the substrate 1 and on the conductor portion 2 formed by printing the solder paste at the same time as the lower surface so that the bumps 4 come into contact with each other. By placing the substrate 1 and the chips 3 thus arranged together with the chip supporting jig 5 in a reflow furnace and heating,
The bumps 4 of each chip and the conductor portions 2 on both upper and lower surfaces are fused.
A step 8 is formed on the support jig 5 below the periphery of the substrate 1 to prevent the substrate 1 from being lowered too much and being crushed at the fused portion during reflow. Even if all the bumps 4 and the conductors 2 are not in contact with each other before the reflow, they are contacted by the deformation of the solder at the time of the reflow, and the bumps 4 and the conductors 2 are connected at a normal position with the self-alignment function. Done. Since each of the chips 3 on the lower surface side is supported by the support 7 only at one point in the central portion, the displacement of the chips when the self-alignment function works is not hindered. However, the width of the recess 6 is limited to about 100 μm larger than the size of the chip 3.

第3図は別の実施例を示し、第1図の実施例と異なる点
は、支持治具5の凹部内でチップ3はピン9によって支
えられていることである。支持ピン9はばね10により各
チップ3を一定の圧力で上方へ押し上げる構造となって
いる。こうすることによって、チップ3の厚さのばらつ
きを吸収できる利点が得られる。
FIG. 3 shows another embodiment, which is different from the embodiment shown in FIG. 1 in that the chip 3 is supported by the pin 9 in the recess of the supporting jig 5. The support pin 9 has a structure in which each chip 3 is pushed upward by a spring 10 with a constant pressure. By doing so, there is an advantage that variations in the thickness of the chip 3 can be absorbed.

なお、絶縁基板1上の導体部は、上の実施例のようには
んだのみよりなるものでなく、他の材料よりなる導体上
に予備はんだを施したものであってもよい。
The conductor portion on the insulating substrate 1 is not limited to the solder only as in the above embodiment, but may be a conductor made of another material and preliminarily soldered.

〔発明の効果〕〔The invention's effect〕

本発明によれば、絶縁基板の下面に実装する半導体チッ
プを支持治具の凹部によって位置決めすることにより、
上面上に載せられたチップと共に1回のリフロー工程で
各チップのはんだバンプと基板両面の導体部との融着,
接続を行なうことができる。従って、はんだの融点は任
意に選定できるので、リフロー温度を高温にする必要が
なく、他の電子部品を損なうおそれなしに半導体チップ
のフリップチップ方式による両面実装が可能となる。
According to the present invention, by positioning the semiconductor chip mounted on the lower surface of the insulating substrate by the recess of the supporting jig,
Fusing the solder bumps of each chip with the conductors on both sides of the board in a single reflow process together with the chip placed on the upper surface,
The connection can be made. Therefore, since the melting point of the solder can be arbitrarily selected, it is not necessary to increase the reflow temperature, and it is possible to mount the semiconductor chip on both sides by the flip chip method without damaging other electronic components.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例において治具にセットされた
状態での断面図、第2図はフリップチップ方式の実装を
示す斜視図、第3図は本発明の別の実施例において治具
にセットされた状態での断面図である。 1:絶縁基板、2:導体部、3:半導体チップ、4:は
んだバンプ、5:支持治具、6:凹部、7:支持体、
9:ピン。
FIG. 1 is a cross-sectional view of a jig set in one embodiment of the present invention, FIG. 2 is a perspective view showing flip-chip mounting, and FIG. 3 is a sectional view of another embodiment of the present invention. It is sectional drawing in the state set in the tool. 1: Insulating substrate, 2: Conductor part, 3: Semiconductor chip, 4: Solder bump, 5: Support jig, 6: Recess, 7: Support,
9: Pin.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】はんだバンプを有する半導体チップを絶縁
基板の両面に取り付け、バンプを基板上の導体部と接続
する方法であって、絶縁基板の両面に少なくとも表面層
が同一材料のはんだよりなる導体部を形成し、チップ支
持治具の位置決め用凹部内に基板の一面に実装されるチ
ップを1個ずつ収容してチップ下面中央を支持し、該チ
ップ支持治具上に前記基板を載せて該基板の一面の導体
部を支持治具内の各チップのバンプに近接ないし接触さ
せ、次いで前記基板の他面上に他のチップを載せて基板
の他面の導体部に各チップのバンプを近接ないし接触さ
せ、しかるのちリフロー炉中において各導体部と各バン
プとを融着させることを特徴とする半導体チップの実装
方法。
1. A method of mounting semiconductor chips having solder bumps on both sides of an insulating substrate and connecting the bumps to conductor portions on the substrate, the conductor comprising at least surface layers made of solder of the same material on both sides of the insulating substrate. Part is formed, and each of the chips mounted on one surface of the substrate is housed in the positioning recess of the chip supporting jig to support the center of the lower surface of the chip, and the substrate is placed on the chip supporting jig. Bring the conductor on one side of the substrate close to or in contact with the bump of each chip in the support jig, then place another chip on the other side of the substrate and place the bump of each chip near the conductor on the other side of the substrate. A method for mounting a semiconductor chip, characterized in that each conductor portion and each bump are fused together in a reflow furnace.
JP62027908A 1987-02-09 1987-02-09 Mounting method of semiconductor chip Expired - Lifetime JPH0658923B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62027908A JPH0658923B2 (en) 1987-02-09 1987-02-09 Mounting method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62027908A JPH0658923B2 (en) 1987-02-09 1987-02-09 Mounting method of semiconductor chip

Publications (2)

Publication Number Publication Date
JPS63194342A JPS63194342A (en) 1988-08-11
JPH0658923B2 true JPH0658923B2 (en) 1994-08-03

Family

ID=12233982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62027908A Expired - Lifetime JPH0658923B2 (en) 1987-02-09 1987-02-09 Mounting method of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH0658923B2 (en)

Also Published As

Publication number Publication date
JPS63194342A (en) 1988-08-11

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