JPH065868A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH065868A JPH065868A JP4160890A JP16089092A JPH065868A JP H065868 A JPH065868 A JP H065868A JP 4160890 A JP4160890 A JP 4160890A JP 16089092 A JP16089092 A JP 16089092A JP H065868 A JPH065868 A JP H065868A
- Authority
- JP
- Japan
- Prior art keywords
- base layer
- layer
- type
- source
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 230000001939 inductive effect Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 65
- 230000001965 increasing effect Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
縦型二重拡散ＭＯＳＦＥＴを有する半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a vertical double diffusion MOSFET.
【０００２】[0002]
【従来の技術】従来の縦型二重拡散ＭＯＳＦＥＴは、図
３に示すように、Ｎ+ 型のドレイン層４とこの上にエピ
タキシャル成長法によって形成されたＮ- 型のドレイン
層５とからなる半導体基板に、ゲート・チャネル領域と
なるＰ- 型の第１のベース層６を設け、この第１のベー
ス層６の表面にＮ型のソース層７と誘導性負荷特有の逆
起電力サージによる破壊を防止するためにＰ+ 型の第２
のベース層９をソース層７とほぼ同じ拡散層深さで形成
し、更にその上にゲート酸化膜１０及び多結晶シリコン
を用いたゲート電極３を形成し、このゲート酸化膜１０
及びゲート電極３をソース層７の一部と第２のベース層
９の部分で開孔し、ゲート電極３上に層間絶縁膜１１を
設け、この部分でソース層７の一部と第２のベース層９
が接触するようにソース電極２を形成し、ソース電極２
上に表面保護膜１２を形成し、また下面にドレイン電極
１を形成した構造となっている。2. Description of the Related Art As shown in FIG. 3, a conventional vertical double diffusion MOSFET is a semiconductor including an N + type drain layer 4 and an N − type drain layer 5 formed thereon by an epitaxial growth method. The substrate is provided with a P − -type first base layer 6 serving as a gate / channel region, and the surface of the first base layer 6 is destroyed by an N-type source layer 7 and a counter electromotive force surge peculiar to an inductive load. P + type second to prevent
Of the source layer 7 is formed to a depth almost equal to that of the source layer 7, and a gate oxide film 10 and a gate electrode 3 made of polycrystalline silicon are further formed thereon.
And the gate electrode 3 is opened in a part of the source layer 7 and the second base layer 9, and an interlayer insulating film 11 is provided on the gate electrode 3, and in this part, a part of the source layer 7 and the second base layer 9 are formed. Base layer 9
Source electrode 2 is formed so that
The surface protection film 12 is formed on the upper surface, and the drain electrode 1 is formed on the lower surface.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の半導体
装置は、第２のベース層９がソース層７とほぼ同じ深さ
の拡散層であるため、ドレイン層５と第１のベース層６
及び第２のベース層９とソース層７とで寄生ＮＰＮトラ
ンジスタが形成される。この寄生ＮＰＮトランジスタに
おいては、第１のベース層の不純物濃度が低いためｈFE
が高まって導通しやすくなり、誘導性負荷に対する破壊
耐量が十分に得られなかった。In the conventional semiconductor device described above, since the second base layer 9 is a diffusion layer having substantially the same depth as the source layer 7, the drain layer 5 and the first base layer 6 are formed.
A parasitic NPN transistor is formed by the second base layer 9 and the source layer 7. In this parasitic NPN transistor, since the impurity concentration of the first base layer is low, h FE
Was increased to facilitate conduction, and a sufficient breakdown resistance against an inductive load could not be obtained.
【０００４】また、この誘導性負荷に対する破壊耐量を
向上させるために、前記寄生ＮＰＮトランジスタのｈFE
を低減させて導通しにくくするように第１のベース層６
の不純物濃度を高くした場合、ゲート・チャネル領域と
なる基板表面付近の不純物濃度、すなわちチャネル濃度
も同様に高くなり、ＭＯＳＦＥＴを導通状態にするため
にゲート・ソース間に印加するしきい値電圧ＶGS(Off)
が大きくなるという問題点があった。[0004] In order to improve the breakdown voltage for the inductive load, h FE of the parasitic NPN transistor
The first base layer 6 so as to reduce
When the impurity concentration of is increased, the impurity concentration in the vicinity of the surface of the substrate that becomes the gate / channel region, that is, the channel concentration is also increased, and the threshold voltage V applied between the gate and the source to bring the MOSFET into a conductive state is increased. GS (Off)
However, there was a problem that
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
ドレイン層となる第１導電型の半導体基板と、この半導
体基板内に設けられゲート・チャネル領域となる不純物
濃度の低い第２導電型の第１のベース層と、この第１の
ベース層表面の中央部に設けられ不純物濃度の高い第２
導電型の第２のベース層と、前記第１のベース層表面の
前記第２のベース層の周囲に設けられ第２のベース層と
ほぼ同じ厚さに形成された第１導電型のソース層と、前
記第１のベース層内に設けられ前記第２のベース層の下
部に接続し前記ソース層の下部に延在して形成された不
純物濃度の高い第２導電型の第３のベース層とを含むも
のである。The semiconductor device of the present invention comprises:
A first conductivity type semiconductor substrate which becomes a drain layer, a second conductivity type first base layer which is provided in the semiconductor substrate and has a low impurity concentration which becomes a gate / channel region, and a surface of the first base layer. 2nd with high impurity concentration
A conductive type second base layer, and a first conductive type source layer provided on the surface of the first base layer around the second base layer and formed to have substantially the same thickness as the second base layer. And a third base layer of a second conductivity type having a high impurity concentration, which is provided in the first base layer, is connected to a lower portion of the second base layer, and is extended to a lower portion of the source layer. It includes and.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のＮチャネル型ＭＯＳＦＥ
Ｔを示す断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an N-channel type MOSFE according to an embodiment of the present invention.
It is sectional drawing which shows T.
【０００７】図１に示すように、Ｎ+ 型のドレイン層４
と、この上にエピタキシャル成長法によって形成された
Ｎ- 型のドレイン層５とからなる半導体基板に、ゲート
酸化膜１０と多結晶シリコンを用いたゲート電極３を形
成したのち開孔し、この開孔部を用いてゲート・チャネ
ル領域となるＰ- 型の第１のベース層６を形成する。次
に、誘導性負荷に対する破壊耐量を向上させるためのＰ
型の第３のベース層８を形成し、続いてＮ型のソース層
７とその中央部にＰ+ 型の第２のベース層９を形成す
る。As shown in FIG. 1, the N + type drain layer 4 is formed.
Then, a gate oxide film 10 and a gate electrode 3 made of polycrystalline silicon are formed on a semiconductor substrate composed of an N − -type drain layer 5 formed thereon by an epitaxial growth method, and then a hole is formed. The P − -type first base layer 6 to be the gate channel region is formed by using the portion. Next, P for improving the fracture resistance against inductive loads
The third type base layer 8 is formed, and then the N type source layer 7 and the P + type second base layer 9 are formed in the central portion thereof.
【０００８】この場合、第３のベース層８は第２のベー
ス層９の下部で第２のベース層に接続し、しかもソース
層７の下部に延在するように構成する。次に、ゲート電
極３上に層間絶縁膜１１を形成し、ソース層７の一部及
び第２のベース層９上で層間絶縁膜１１を開孔し、ソー
ス電極２を形成する。次に、表面保護膜１２を形成し、
最後に基板裏面にドレイン電極１を形成する。In this case, the third base layer 8 is constructed so as to be connected to the second base layer below the second base layer 9 and extend below the source layer 7. Next, the interlayer insulating film 11 is formed on the gate electrode 3, and the interlayer insulating film 11 is opened on a part of the source layer 7 and the second base layer 9 to form the source electrode 2. Next, the surface protective film 12 is formed,
Finally, the drain electrode 1 is formed on the back surface of the substrate.
【０００９】このように構成された本実施例によれば、
第３のベース層８がソース層７及び第２のベース層９よ
りも拡散層の深さが深いため、ドレイン層５と第１，第
２，第３のベース層６，９，８とソース層７で形成され
る寄生ＮＰＮトランジスタにおいて、ベース層部分の不
純物濃度が高いため、ｈFEが低減して導通しにくくな
り、誘導性負荷に対する破壊耐量が向上する。According to the present embodiment thus constructed,
Since the third base layer 8 has a deeper diffusion layer than the source layer 7 and the second base layer 9, the drain layer 5 and the first, second, third base layers 6, 9, 8 and the source In the parasitic NPN transistor formed by the layer 7, since the impurity concentration of the base layer portion is high, h FE is reduced and it becomes difficult to conduct electricity, and the breakdown resistance against an inductive load is improved.
【００１０】また、本実施例によれば、ゲート・チャネ
ル領域となる基板表面付近の不純物濃度、すなわちチャ
ネル濃度は、第１のベース層６により維持されたままで
あり、ＭＯＳＦＥＴを導通状態にするためにゲート・ソ
ース間に印加するしきい値電圧ＶGS(Off) を大きくする
ことなく、誘導性負荷に対する破壊耐量を向上させるこ
とができる。Further, according to this embodiment, the impurity concentration in the vicinity of the surface of the substrate which becomes the gate / channel region, that is, the channel concentration is maintained by the first base layer 6 to keep the MOSFET in the conductive state. It is possible to improve the breakdown resistance against an inductive load without increasing the threshold voltage V GS (Off) applied between the gate and the source.
【００１１】図２は、誘導性負荷耐量と定格電流Ｉ
D(DC) の関係を表しており、縦軸に誘導性負荷耐量、横
軸に定格電流を示している。この図２において、黒点が
本実施例による場合、白点が従来の構造による場合であ
る。図２から明らかなように、従来の半導体装置に比べ
本実施例では誘導性負荷耐量が５０％向上していること
がわかる。FIG. 2 shows inductive load capacity and rated current I.
It shows the relationship of D (DC) , in which the vertical axis shows the inductive load capacity and the horizontal axis shows the rated current. In FIG. 2, the black dots represent the case of this embodiment and the white dots represent the case of the conventional structure. As is apparent from FIG. 2, the inductive load withstand amount is improved by 50% in this embodiment as compared with the conventional semiconductor device.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、縦型二重
拡散ＭＯＳＦＥＴにおいて、第１のベース層表面に形成
された第２のベース層の下に、ソース層及び第２のベー
ス層よりも深い第３のベース層を形成することにより、
誘導性負荷に対する破壊耐量を向上させることができる
という効果を有する。さらに、本発明によれば、しきい
値電圧ＶGS(Off) を大きくすることなく誘導性負荷に対
する破壊耐量を向上させることができる。As described above, according to the present invention, in a vertical double diffusion MOSFET, a source layer and a second base layer are provided below a second base layer formed on the surface of the first base layer. By forming a deeper third base layer,
It has an effect that it is possible to improve the breakdown resistance against an inductive load. Furthermore, according to the present invention, it is possible to improve the breakdown withstanding load against an inductive load without increasing the threshold voltage V GS (Off) .
【図１】本発明の一実施例を示す半導体チップの断面
図。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.
【図２】本実施例と従来例の誘導性負荷耐量と定格電流
の関係を示す図。FIG. 2 is a diagram showing a relationship between an inductive load withstanding capacity and a rated current in this example and a conventional example.
【図３】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ ドレイン電極 ２ ソース電極 ３ ゲート電極 ４ ドレイン層 ５ ドレイン層 ６ 第１のベース層 ７ ソース層 ８ 第３のベース層 ９ 第２のベース層 １０ ゲート酸化膜 １１ 層間絶縁膜 １２ 表面保護膜 1 Drain Electrode 2 Source Electrode 3 Gate Electrode 4 Drain Layer 5 Drain Layer 6 First Base Layer 7 Source Layer 8 Third Base Layer 9 Second Base Layer 10 Gate Oxide Film 11 Interlayer Insulating Film 12 Surface Protective Film
Claims (1)
板と、この半導体基板内に設けられゲート・チャネル領
域となる不純物濃度の低い第２導電型の第１のベース層
と、この第１のベース層表面の中央部に設けられ不純物
濃度の高い第２導電型の第２のベース層と、前記第１の
ベース層表面の前記第２のベース層の周囲に設けられ第
２のベース層とほぼ同じ厚さに形成された第１導電型の
ソース層と、前記第１のベース層内に設けられ前記第２
のベース層の下部に接続し前記ソース層の下部に延在し
て形成された不純物濃度の高い第２導電型の第３のベー
ス層とを含むことを特徴とする半導体装置。1. A first-conductivity-type semiconductor substrate serving as a drain layer, a second-conductivity-type first base layer having a low impurity concentration, which is provided in the semiconductor substrate and serves as a gate channel region, and the first-conductivity-type first base layer. Second conductive type second base layer provided in the central portion of the base layer surface and having a high impurity concentration, and a second base layer provided around the second base layer on the first base layer surface. A source layer of the first conductivity type formed to have substantially the same thickness as that of the second conductive layer, and the second layer provided in the first base layer.
A second conductive type third base layer having a high impurity concentration, which is formed so as to be connected to the lower part of the base layer and extend to the lower part of the source layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4160890A JPH065868A (en) | 1992-06-19 | 1992-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4160890A JPH065868A (en) | 1992-06-19 | 1992-06-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065868A true JPH065868A (en) | 1994-01-14 |
Family
ID=15724583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4160890A Withdrawn JPH065868A (en) | 1992-06-19 | 1992-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065868A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
-
1992
- 1992-06-19 JP JP4160890A patent/JPH065868A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |