JPH065680B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH065680B2 JPH065680B2 JP59182749A JP18274984A JPH065680B2 JP H065680 B2 JPH065680 B2 JP H065680B2 JP 59182749 A JP59182749 A JP 59182749A JP 18274984 A JP18274984 A JP 18274984A JP H065680 B2 JPH065680 B2 JP H065680B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- conductive
- forming
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- -1 Arsenic ions Chemical class 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】 技術分野 本発明は半導体装置の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device.
従来技術 ソースおよびドレーンの各接点窓のアルミニウム電極
は、絶縁膜の段差において断線がおきやすい。これを防
止するために、PSG絶縁膜を融解させて接点窓の段差を
緩やかにする方法、あるいは接点窓にシリコンをエピタ
キシャル成長させて接点窓を持ち上げてアルミニウム配
線する方法がある。2. Description of the Related Art The aluminum electrodes of the contact windows of the source and drain are easily broken at the step of the insulating film. To prevent this, there is a method of melting the PSG insulating film to make the step of the contact window gentle, or a method of epitaxially growing silicon on the contact window and lifting the contact window to perform aluminum wiring.
解決しようとする問題点 たとえば三次元素子のこの技術を応用すると、1000
℃以上の高温度が必要であり、再結晶シリコンのなかの
粒子間の不純物の異常拡散がおこりやすく、実施できな
い。また、PSGの融解は段差を解消するものではなく、
また接点窓のエピタキシャル成長は窓の側面に巣ができ
る欠点も有する。Problems to be solved For example, if this technology of three-dimensional element is applied,
Since a high temperature of ℃ or more is required and abnormal diffusion of impurities between particles in recrystallized silicon is likely to occur, it cannot be performed. Also, melting PSG does not eliminate the step,
Epitaxial growth of the contact window also has the drawback that cavities form on the sides of the window.
解決するための手段 上記問題点は、 1)シリコン基板にフィールド酸化膜およびゲート酸化
膜を形成した後、ゲート電極をマスクとしてソース領域
およびドレーン領域の酸化膜を除去する工程と、 2)全面に導電膜を形成する工程と、 3)ソース領域およびドレーン領域の各接点窓に相当す
る領域に位置する導電膜をホトレジストマスクで被覆す
る工程と、 4)基板のシリコン面まで導電膜をエッチングして、ソ
ースおよびドレーンの導電柱を形成し、かつホトレジス
トマスクを除去する工程と、 5)イオン注入して、ソースおよびドレーンを形成する
工程と、 6)全面に導電柱の頂面と同じ高さの酸化膜を形成する
工程と、 7)導電柱上の酸化膜をバイアススパッタリングして除
去するとともに、酸化膜のゲート上に突出する部分を除
去して平坦化する工程と、 8)イオン拡散し、かつ導電柱上に電極を形成する工程
とを含むことを特徴とする半導体装置の製法によって解
決することができる。Means for Solving the Problems The above problems are as follows: 1) a step of forming a field oxide film and a gate oxide film on a silicon substrate, and then removing the oxide film of a source region and a drain region using a gate electrode as a mask; A step of forming a conductive film, 3) a step of covering the conductive film located in regions corresponding to the contact windows of the source region and the drain region with a photoresist mask, and 4) etching the conductive film up to the silicon surface of the substrate. , Forming the source and drain conductive pillars and removing the photoresist mask, 5) forming a source and drain by ion implantation, and 6) forming a conductive pillar on the entire surface at the same height as the top surface of the conductive pillar. And the step of forming an oxide film, and 7) removing the oxide film on the conductive pillar by bias sputtering and removing the portion of the oxide film protruding above the gate. Planarizing by removed by, 8) and ion diffusion, and in that it comprises a step of forming an electrode on the conductive posts can be solved by method of a semiconductor device according to claim.
実施例 第1図を参照して、本発明の半導体装置の製法の1つの
実施態様を説明する。1)シリコン基板1を熱酸化して
フィールド酸化膜2およびゲート酸化膜3を形成し、こ
の上にポリシリコン膜をCVDによって形成し、これをエ
ッチングしてゲート4を形成した。なお、好ましい態様
として、ゲート4にレーザービームを照射して、表面の
ポリシリコンを融解して再結晶化した。これは後のエッ
チング工程において、全面ポリシリコンとゲートポリシ
リコンのエッチング比を上げてゲートを保護するためで
ある。2)次にゲートのシリコンをマスクとしてソース
領域およびドレーン領域の酸化膜を除去した。3)導電
膜として厚み5000〜8000Åのポリシリコン膜5
をCVDによって形成して全面を被覆した。なお導電膜と
して、ポリシリコンの代りにモリブデン、またはタング
ステンを使用することもできるが、このときはさきのゲ
ートシリコン再結晶化は不要である。4)ホトレジスト
マスク6を、ソース領域およびドレーン領域の各接点窓
に相当する領域のポリシリコン膜5の上に設けた。5)
ポリシリコン膜5をリアクディブイオンエッチングし
て、丁度基板1の面まで達したときにエッチングを終了
した。ゲート4は表面4′が再結晶化されているのでエ
ッチングされずに残り、ホトレジストマスク6の下には
ソース7およびドレーン8のための高さ5000〜80
00Åの導電柱5′が残った。ホトレジストマスク6は
剥離して、除去した。6)ひ素イオンを注入してソース
およびドレーンを形成した。このとき導電柱5′にも注
入された。もし、常法のように、工程1)においてイオ
ン注入を行なう場合は、基板シリコン1を損傷してエッ
チングレートが上がり、ポリシリコン膜5とのエッチン
グレートの差が少なくなるので、丁度基板面においてエ
ッチングを終了することが困難になる。7)導電柱5′
およびゲート4を載せたシリコン基板1の上に、CVDに
よって導電柱5′の頂面の高さと同じ高さの酸化膜9を
形成した。このとき導電柱5′の上にも球状の酸化膜
9′が沈着した。8)バイアススパッタリングによって
導電柱5′上の酸化膜9′を除去し、同時にゲート上に
突出する酸化膜も平坦化された。9)アニールによりソ
ース7およびドレーン8をそれぞれ導電柱5′の下で一
体化した。なおアルミニウム電極配線10を形成した。
導電柱5′と酸化膜9とが同一の高さであるので、断線
の恐れは全くない。EXAMPLE One embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. 1) The silicon substrate 1 was thermally oxidized to form a field oxide film 2 and a gate oxide film 3, a polysilicon film was formed on this by CVD, and this was etched to form a gate 4. As a preferred embodiment, the gate 4 was irradiated with a laser beam to melt and recrystallize the polysilicon on the surface. This is to protect the gate by increasing the etching ratio of the entire surface polysilicon and the gate polysilicon in the subsequent etching process. 2) Next, using the silicon of the gate as a mask, the oxide film in the source region and the drain region was removed. 3) Polysilicon film 5 having a thickness of 5000 to 8000Å as a conductive film
Was formed by CVD to cover the entire surface. As the conductive film, molybdenum or tungsten can be used instead of polysilicon, but in this case, recrystallization of the gate silicon is not necessary. 4) A photoresist mask 6 was provided on the polysilicon film 5 in the regions corresponding to the contact windows in the source region and the drain region. 5)
The polysilicon film 5 was subjected to reactive ion etching, and the etching was completed when the surface of the substrate 1 was reached. The gate 4 remains unetched because the surface 4'is recrystallized, and below the photoresist mask 6 the heights 5000 to 80 for the source 7 and the drain 8 are left.
The conductive column 5'of 00Å remained. The photoresist mask 6 was peeled off and removed. 6) Arsenic ions were implanted to form a source and a drain. At this time, the conductive columns 5'are also injected. If the ion implantation is performed in the step 1) as in the conventional method, the substrate silicon 1 is damaged and the etching rate is increased, and the difference in etching rate from the polysilicon film 5 is reduced. It becomes difficult to finish the etching. 7) Conductive pillar 5 '
Then, an oxide film 9 having the same height as the top surface of the conductive pillar 5'is formed by CVD on the silicon substrate 1 on which the gate 4 is mounted. At this time, a spherical oxide film 9'is also deposited on the conductive pillar 5 '. 8) The oxide film 9'on the conductive pillar 5'was removed by bias sputtering, and at the same time, the oxide film protruding above the gate was also flattened. 9) The source 7 and the drain 8 are integrated under the conductive pillar 5'by annealing. The aluminum electrode wiring 10 was formed.
Since the conductive pillars 5'and the oxide film 9 have the same height, there is no fear of disconnection.
この実施例では、ポリシリコンをCVDでつけたが、モリ
ブデンまたはタングステンを使用するときは、スパッタ
リングでつけることもできる。In this example, polysilicon was deposited by CVD, but if molybdenum or tungsten is used, it can be deposited by sputtering.
本発明の製法は、表面が平坦化されるので半導体素子の
三次元化が信頼性よく実現できる。According to the manufacturing method of the present invention, since the surface is flattened, three-dimensionalization of a semiconductor device can be realized with high reliability.
発明の効果 本発明によれば、電極配線の断線を防止することがで
き、また三次元構造の直接層間配線に利用できることも
有利である。なお、低温度の反応によって半導体装置を
製造することもできる。EFFECTS OF THE INVENTION According to the present invention, it is advantageous that the disconnection of the electrode wiring can be prevented and that the electrode wiring can be directly used for the interlayer wiring. Note that a semiconductor device can also be manufactured by a low temperature reaction.
第1図1)〜9)は本発明の半導体装置の製法を示す工
程図である。 1…シリコン基板、2…フィールド酸化膜、3…ゲート
酸化膜、4…ゲートポリシリコン、5…導電膜、5′…
導電柱、6…ホトレジストマスク、7…ドレーン、8…
ソース、9…酸化膜、9′…球状の酸化膜、10…電
極。1) to 9) are process drawings showing a method for manufacturing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Field oxide film, 3 ... Gate oxide film, 4 ... Gate polysilicon, 5 ... Conductive film, 5 '...
Conductive pillar, 6 ... Photoresist mask, 7 ... Drain, 8 ...
Source, 9 ... Oxide film, 9 '... Spherical oxide film, 10 ... Electrode.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 河村 誠一郎 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 森 治久 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 向井 良一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 伊沢 哲夫 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 昭60−53019(JP,A) 特開 昭57−141968(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Seiichiro Kawamura, 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Haruhisa Mori, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Ryoichi Mukai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Tetsuo Izawa, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP 60 -53019 (JP, A) JP-A-57-141968 (JP, A)
Claims (1)
びゲート酸化膜を形成した後、ゲート電極をマスクとし
てソース領域およびドレーン領域の酸化膜を除去する工
程と、 2)全面に導電膜を形成する工程と、 3)ソース領域およびドレーン領域の各接点窓に相当す
る領域に位置する導電膜をホトレジストマスクで被覆す
る工程と、 4)基板のシリコン面まで導電膜をエッチングしてソー
スおよびドレーンの導電柱を形成し、かつホトレジスト
マスクを除去する工程と、 5)イオン注入して、ソースおよびドレーンを形成する
工程と、 6)全面に導電柱の頂面と同じ高さの酸化膜を形成する
工程と、 7)導電柱上の酸化膜をバイアススパッタリングして除
去するとともに、酸化膜のゲート上に突出する部分を除
去して平坦化する工程と、 8)イオン拡散し、かつ導電柱上に電極を形成する工程
とを含むことを特徴とする半導体装置の製法。1. A step of 1) forming a field oxide film and a gate oxide film on a silicon substrate, and then removing the oxide film of a source region and a drain region using a gate electrode as a mask, and 2) forming a conductive film on the entire surface. And 3) a step of covering the conductive film located in the regions corresponding to the contact windows of the source region and the drain region with a photoresist mask, and 4) etching the conductive film up to the silicon surface of the substrate to conduct the source and drain. Steps of forming pillars and removing the photoresist mask, 5) Steps of ion-implanting to form sources and drains, and 6) Steps of forming an oxide film at the same height as the top surfaces of the conductive pillars on the entire surface. And 7) a step of removing the oxide film on the conductive pillar by bias sputtering and removing a portion of the oxide film protruding above the gate to flatten the surface. Preparation of a semiconductor device which comprises the steps of: 8) and ion diffusion, and forming an electrode on the conductive pillars.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59182749A JPH065680B2 (en) | 1984-09-03 | 1984-09-03 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59182749A JPH065680B2 (en) | 1984-09-03 | 1984-09-03 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6161466A JPS6161466A (en) | 1986-03-29 |
JPH065680B2 true JPH065680B2 (en) | 1994-01-19 |
Family
ID=16123761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59182749A Expired - Lifetime JPH065680B2 (en) | 1984-09-03 | 1984-09-03 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH065680B2 (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57176742A (en) * | 1981-04-21 | 1982-10-30 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
JPS57204145A (en) * | 1981-06-10 | 1982-12-14 | Toshiba Corp | Manufacture of semiconductor device |
JPS57141968A (en) * | 1981-07-01 | 1982-09-02 | Nec Corp | Insulated gate type field effect transistor |
-
1984
- 1984-09-03 JP JP59182749A patent/JPH065680B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6161466A (en) | 1986-03-29 |
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