JPH065563A - Ashing method of resist - Google Patents

Ashing method of resist

Info

Publication number
JPH065563A
JPH065563A JP18600892A JP18600892A JPH065563A JP H065563 A JPH065563 A JP H065563A JP 18600892 A JP18600892 A JP 18600892A JP 18600892 A JP18600892 A JP 18600892A JP H065563 A JPH065563 A JP H065563A
Authority
JP
Japan
Prior art keywords
resist
gas
plasma
ashing
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18600892A
Other languages
Japanese (ja)
Inventor
Toshiyuki Orita
敏幸 折田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP18600892A priority Critical patent/JPH065563A/en
Publication of JPH065563A publication Critical patent/JPH065563A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To peel off and remove resist without damaging a foundation layer by using chlorine gas or bromine gas together with oxygen gas as reactive gas for removing a resist on a substrate by ashing. CONSTITUTION:An Si substrate 11 is coated with a positive resist 13 using SiO2 12 as a foundation, a wafer A wherein ion implantation of phosphorus 14 is performed as impurities is set in a treatment chamber 3 and an inside of the treatment chamber 3 is decompressed. Chlorine gas or bromine gas is introduced at a low pressure to a plasma generation chamber 1 together with oxygen gas. The reactive gas is made into plasma by applying high frequency to the plasma generation chamber 1 and introduced to the treatment chamber 3 wherein the wafer A is set. The resist 13 applied to a surface of the wafer A is removed by ashing by plasma inside the treatment chamber 3. The resist can be completely peeled off and removed without affecting a foundation and without making residue remain.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体製造工程における
レジストの除去方法に関し、特にアッシングによりレジ
ストを除去する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of removing a resist in a semiconductor manufacturing process, and more particularly to a method of removing a resist by ashing.

【0002】[0002]

【従来の技術】半導体製造工程においては、半導体基板
上へのパターン形成及び不純物拡散等、レジストをマス
クとして用いる様々な工程がある。また、それぞれの工
程が終了した後に、レジストの剥離除去工程が設けられ
るが、この工程においては、下地となるSi基板及Si
2 膜等にダメージを与えず、レジストを完全に剥離除
去することが要求される。従来、上記のレジスト剥離除
去工程には、レジストを酸素プラズマにさらすことによ
って、低温で酸化除去する、いわゆるプラズマアッシン
グ法が広く用いられている。さらに残渣を残さずに完全
な剥離除去を行うために、上記酸素プラズマと共にフッ
素プラズマ、水素プラズマ等を用いる方法、及び酸素に
よるRIE(Reactive Ion Etching)等のアッシング方
法が用いられている。
2. Description of the Related Art In a semiconductor manufacturing process, there are various processes using a resist as a mask such as pattern formation on a semiconductor substrate and impurity diffusion. Further, after each step is completed, a resist peeling removal step is provided. In this step, the Si substrate and Si
It is required to completely remove the resist without damaging the 0 2 film or the like. Conventionally, a so-called plasma ashing method has been widely used in the above resist stripping and removing step, in which a resist is exposed to oxygen plasma to be oxidized and removed at a low temperature. Further, in order to completely remove the residue without leaving a residue, a method using fluorine plasma, hydrogen plasma or the like together with the oxygen plasma, and an ashing method such as RIE (Reactive Ion Etching) with oxygen are used.

【0003】[0003]

【発明が解決しようとする課題】しかし、各工程におけ
る様々な処理、例えば半導体基板にイオン注入を行うこ
とによってレジストは様々に変質し、上記のアッシング
工程を経ても完全に剥離除去されずに残渣を残したり、
あるいは以下の様な問題が見られた。先ず、酸素プラズ
マと共にフッ素プラズマを用いる方法においては、残渣
の低減が図られるものの、下地のSi基板及びSiO2
膜等もエッチングされてしまう。次に、酸素プラズマと
共に水素プラズマを用いる方法では、原子半径の小さい
水素が半導体基板に注入され、デバイス特性が劣化して
しまう。そして酸素によるRIEでは、酸素イオンのエ
ネルギーが高いため下地層に結晶欠陥等のダメージが加
わり、やはりデバイス特性が劣化してしまう。この発明
は、以上の問題点を解決し、レジスト除去工程において
Si基板及びSi02 膜等の下地層にダメージを与え
ず、レジストを完全に剥離除去するアッシング方法を提
供することを目的とする。
However, the resist is altered in various ways by various treatments in each step, for example, by ion implantation into the semiconductor substrate, and the resist is not completely stripped and removed even after the above ashing step. Or leave
Or the following problems were seen. First, in the method of using fluorine plasma together with oxygen plasma, although the residue can be reduced, the underlying Si substrate and SiO 2
The film etc. will also be etched. Next, in the method of using hydrogen plasma together with oxygen plasma, hydrogen having a small atomic radius is injected into the semiconductor substrate, resulting in deterioration of device characteristics. In RIE using oxygen, since the energy of oxygen ions is high, damage such as crystal defects is added to the underlying layer, and the device characteristics also deteriorate. An object of the present invention is to solve the above problems and to provide an ashing method for completely peeling and removing the resist without damaging the Si substrate and the underlying layer such as the SiO 2 film in the resist removing step.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明はプラズマ化した反応性ガスにより、半導体
基板上のレジストをアッシング除去する方法において、
前記反応性ガスとして、酸素ガスと共に塩素系ガスおよ
び/または臭素系ガスを用いることを特徴とする。
In order to achieve the above object, the present invention provides a method for ashing and removing a resist on a semiconductor substrate by using a reactive gas that has been turned into plasma.
As the reactive gas, chlorine-based gas and / or bromine-based gas is used together with oxygen gas.

【0005】[0005]

【作用】本発明のレジストのアッシング方法によれば、
反応性ガスとして酸素と共に塩素系ガスまたは臭素系ガ
スを用いるため、アッシングによる下地層のエッチング
及び結晶欠陥が抑えられ、さらに残渣を残さずにレジス
トの剥離を、行うことができる。
According to the resist ashing method of the present invention,
Since chlorine-based gas or bromine-based gas is used together with oxygen as the reactive gas, etching of the underlayer and crystal defects due to ashing can be suppressed, and the resist can be stripped without leaving a residue.

【0006】[0006]

【実施例】以下、本発明の実施例を詳細に説明する。図
1は本発明のレジストのアッシング方法を適応するダウ
ンフロー型のプラズマアッシング装置の構成図である。
この装置は、高周波電磁界によって反応性ガスをプラズ
マ化するプラズマ発生室1と、真空状態でレジストのア
ッシング処理を行う処理室3とで構成されている。プラ
ズマ発生室1と、処理室3は接続管2を介して連通し、
該接続管2は処理室3の上方に設置されている。そして
処理室3の底部には排気管4が設けられ真空ポンプで処
理室3の室内を真空状態に保っているため、室内の気流
は常に底部に向かって流れている。アッシング処理を行
うウェハAは処理室3にセットされる。
EXAMPLES Examples of the present invention will be described in detail below. FIG. 1 is a block diagram of a down-flow type plasma ashing apparatus to which the resist ashing method of the present invention is applied.
This apparatus is composed of a plasma generation chamber 1 in which a reactive gas is turned into plasma by a high frequency electromagnetic field, and a processing chamber 3 in which a resist ashing process is performed in a vacuum state. The plasma generation chamber 1 and the processing chamber 3 communicate with each other via a connecting pipe 2,
The connecting pipe 2 is installed above the processing chamber 3. Further, since the exhaust pipe 4 is provided at the bottom of the processing chamber 3 and the inside of the processing chamber 3 is kept in a vacuum state by the vacuum pump, the airflow in the chamber always flows toward the bottom. The wafer A to be ashed is set in the processing chamber 3.

【0007】上記構成のダウンフロー型のプラズマアッ
シング装置によるアッシングは、先ずプラズマ発生室1
に導入された反応性ガスが、室内に発生させた高周波電
磁界によってプラズマ化される。プラズマ化された反応
性ガスは、接続管2から真空状態となっている処理室3
に導入される。処理室3にセットされたウェハAの表面
のレジストが、該プラズマによってアッシング除去され
る。処理室3の内部の残留ガスが、底部の排気管4から
排気される。ダウンフロー型の装置を用いる理由として
は、生成したプラズマ中にイオンが殆ど存在しないこと
から、イオンによる高エネルギーが下地に与えるダメー
ジを少なくできるためである。
In the ashing by the down-flow type plasma ashing device having the above-mentioned structure, first, the plasma generating chamber 1
The reactive gas introduced into the chamber is turned into plasma by the high-frequency electromagnetic field generated in the room. The reactive gas that has been turned into plasma is processed from the connecting pipe 2 to the processing chamber 3 in a vacuum state.
Will be introduced to. The resist on the surface of the wafer A set in the processing chamber 3 is removed by ashing by the plasma. The residual gas inside the processing chamber 3 is exhausted from the exhaust pipe 4 at the bottom. The reason why the down-flow type device is used is that since ions are hardly present in the generated plasma, damage to the base due to high energy due to the ions can be reduced.

【0008】次に、上記の装置を用いた、本発明のレジ
ストのアッシング方法の一例について述べる。処理を行
うウェハAとして、図2(1)に示したようにSi基板
11上のSiO2 12を下地としてポジ型レジスト13
を1μmコーティングし、不純物としてリン14を加速
電圧100keV でドーズ量1×1016cm-2をイオン注入
したものを用いた。
Next, an example of the resist ashing method of the present invention using the above apparatus will be described. As the wafer A to be processed, as shown in FIG. 2A, the positive resist 13 is formed by using the SiO 2 12 on the Si substrate 11 as a base.
Was used as the impurity, and phosphorus 14 was ion-implanted as an impurity at an acceleration voltage of 100 keV and a dose of 1 × 10 16 cm -2 .

【0009】先ず、上記のウェハAを処理室3にセット
し処理室3の内部を減圧する。次に反応性ガス、例えば
酸素ガス2000sccm(Standard cm3/m ) に塩素ガス1
00sccmを添加したものを、プラズマ発生室1に1Torr
の低圧で導入する。プラズマ発生室1に1kWの高周波を
印加して上記の反応性ガスをプラズマ化し、上記ウェハ
Aがセットされた処理室3に導入する。処理室3の内部
で、ウェハAの表面にコーティングしたレジスト13を
該プラズマによってアッシング除去する。処理室3の内
部の残留ガスを、排気管4から排気する。
First, the wafer A is set in the processing chamber 3 and the inside of the processing chamber 3 is decompressed. Next, a reactive gas, for example, oxygen gas 2000 sccm (Standard cm 3 / m 2) and chlorine gas 1
What added 00 sccm was added to the plasma generating chamber 1 at 1 Torr.
Introduced at low pressure. A high frequency of 1 kW is applied to the plasma generation chamber 1 to turn the reactive gas into plasma, and the plasma is introduced into the processing chamber 3 in which the wafer A is set. Inside the processing chamber 3, the resist 13 coated on the surface of the wafer A is removed by ashing by the plasma. The residual gas inside the processing chamber 3 is exhausted from the exhaust pipe 4.

【0010】上記アッシング処理の結果は良好であっ
た。まず、酸素プラズマのみを用いたアッシングでは残
渣が確認されていたが、上記のアッシング処理では、図
2(2)に示したように上記のウェハAにコーティング
されたレジスト13は、完全に剥離除去された。これは
酸素と共に塩素を用いたためと考えられる。またアッシ
ングによる下地のSi基板11及びSiO2 膜12のエ
ッチングも見られなかった。これは、従来酸素と共に用
いていたフッ素と比較して、塩素のSi及びSiO2
対する反応性が弱いためと考えられる。デバイス特性に
ついても劣化は認められず、これは塩素の原子半径が大
きく基板に注入されにくいことと、ダウンフロー型のア
ッシング装置を用いてプラズマ中のイオンの発生を防い
だ効果と考えられる。
The results of the above ashing treatment were good. First, a residue was confirmed by ashing using only oxygen plasma, but in the above ashing treatment, the resist 13 coated on the wafer A was completely stripped and removed as shown in FIG. 2B. Was done. This is probably because chlorine was used together with oxygen. Further, neither etching of the underlying Si substrate 11 nor the SiO 2 film 12 due to ashing was observed. It is considered that this is because the reactivity of chlorine with respect to Si and SiO 2 is weaker than that of fluorine which has been conventionally used together with oxygen. Regarding device characteristics, no deterioration was observed, which is considered to be due to the fact that chlorine has a large atomic radius and is difficult to be injected into the substrate, and the effect of preventing the generation of ions in plasma by using a downflow type ashing device.

【0011】また、上述の条件で塩素ガスに代えて臭素
ガスを用いた場合、さらに酸素ガスに塩素ガス及び臭素
ガスを添加した場合にも、上記と同様に良好な結果が得
られた。
Similar results were obtained when bromine gas was used instead of chlorine gas under the above conditions, and when chlorine gas and bromine gas were added to oxygen gas.

【0012】[0012]

【発明の効果】以上実施例にて詳細に説明したように、
本発明のレジストのアッシング方法によれば、イオン注
入などの半導体製造工程の様々な処理によって変質した
レジストも、下地のSi基板及びSiO2 膜等へ影響を
及ぼすことなく、さらには残渣を残すことなく完全に剥
離除去される。
As described in detail in the above embodiments,
According to the resist ashing method of the present invention, even a resist that has been altered by various treatments in a semiconductor manufacturing process such as ion implantation does not affect the underlying Si substrate and SiO 2 film and leaves a residue. It is completely stripped and removed.

【図面の簡単な説明】[Brief description of drawings]

【図1】ダウンフロー型プラズマアッシング装置の構成
図である。
FIG. 1 is a configuration diagram of a downflow type plasma ashing apparatus.

【図2】アッシング処理に用いたウェハの一例を示す断
面図である。
FIG. 2 is a sectional view showing an example of a wafer used for an ashing process.

【符号の説明】[Explanation of symbols]

A ウェハ(半導体基板) 13 レジスト膜 A wafer (semiconductor substrate) 13 resist film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 プラズマ化した反応性ガスにより、半導
体基板上のレジストをアッシング除去する方法におい
て、 前記反応性ガスとして、酸素ガスと共に塩素系ガスおよ
び/または臭素系ガスを用いることを特徴とするレジス
トのアッシング方法。
1. A method for ashing and removing a resist on a semiconductor substrate with a reactive gas that has been turned into plasma, wherein a chlorine-based gas and / or a bromine-based gas are used together with oxygen gas as the reactive gas. Resist ashing method.
JP18600892A 1992-06-19 1992-06-19 Ashing method of resist Pending JPH065563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18600892A JPH065563A (en) 1992-06-19 1992-06-19 Ashing method of resist

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18600892A JPH065563A (en) 1992-06-19 1992-06-19 Ashing method of resist

Publications (1)

Publication Number Publication Date
JPH065563A true JPH065563A (en) 1994-01-14

Family

ID=16180762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18600892A Pending JPH065563A (en) 1992-06-19 1992-06-19 Ashing method of resist

Country Status (1)

Country Link
JP (1) JPH065563A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432211B2 (en) 2004-04-28 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432211B2 (en) 2004-04-28 2008-10-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

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