JPH0651349A - Liquid crystal display device and its manufacture - Google Patents
Liquid crystal display device and its manufactureInfo
- Publication number
- JPH0651349A JPH0651349A JP13371293A JP13371293A JPH0651349A JP H0651349 A JPH0651349 A JP H0651349A JP 13371293 A JP13371293 A JP 13371293A JP 13371293 A JP13371293 A JP 13371293A JP H0651349 A JPH0651349 A JP H0651349A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- wiring group
- electrode terminals
- partial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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- Liquid Crystal (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は液晶表示装置に関し、特
にマトリクス状に配置されたスイッチング素子およびこ
れらを結ぶ配線が形成されたアクティブマトリクスアレ
イ基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix array substrate having switching elements arranged in a matrix and wirings connecting them.
【０００２】[0002]
【従来の技術】近年、ガラス等の大型基板表面に形成し
たスイッチング素子アレイよりなるアクティブマトリク
ス液晶パネルが実用化され、ＣＲＴに代る薄型軽量表示
装置として脚光を浴びている。マトリクス状に配置され
るスイッチング用アクティブ素子ならびにそれらを結ぶ
配線の搭載されるアクティブマトリクスアレイ基板は、
半導体薄膜、絶縁性薄膜や導電性薄膜をガラス基板の片
側表面全体に堆積、パターン化することを順次繰返すこ
とで形成される。2. Description of the Related Art In recent years, an active matrix liquid crystal panel including a switching element array formed on the surface of a large substrate such as glass has been put into practical use and has been in the spotlight as a thin and lightweight display device replacing a CRT. The active matrix array substrate on which the switching active elements arranged in a matrix and the wiring connecting them are mounted is
It is formed by sequentially repeating the deposition and patterning of a semiconductor thin film, an insulating thin film and a conductive thin film on the entire one side surface of a glass substrate.
【０００３】スイッチング用アクティブ素子としては薄
膜トランジスタ（ＴＦＴ）が用いられている。ＴＦＴは
複数の行および列のマトリクス状に配置されている。同
一の行に配列されているＴＦＴはゲート同士がゲート配
線で共通されており、この配線はゲート駆動信号を受け
るためのゲート電極端子に導出接続されている。また、
同一の列の配列されているＴＦＴはドレイン同士がドレ
イン配線で共通されており、この配線はドレイン信号を
受けるためのドレイン電極端子に導出接続されている。
各ＴＦＴのソースは各画素のための一方の透明電極に接
続されている。A thin film transistor (TFT) is used as an active element for switching. The TFTs are arranged in a matrix of a plurality of rows and columns. In the TFTs arranged in the same row, the gates are commonly used for the gate wiring, and this wiring is led out and connected to the gate electrode terminal for receiving the gate drive signal. Also,
The drains of the TFTs arranged in the same column are shared by drain wirings, and these wirings are led out and connected to a drain electrode terminal for receiving a drain signal.
The source of each TFT is connected to one transparent electrode for each pixel.
【０００４】ゲート配線およびドレイン配線は、各画素
の大きさに応じてそれぞれ定められたピッチをもってそ
れぞれ行状および列状に配列されている。一方、ゲート
電極端子およびドレイン電極端子は、各端子に所定の信
号を印加するための駆動ＩＣとの接続の関係から、上記
ピッチよりもかなり小さいピッチをもって配列されてい
る。The gate wiring and the drain wiring are arranged in rows and columns with a pitch determined according to the size of each pixel. On the other hand, the gate electrode terminal and the drain electrode terminal are arranged at a pitch much smaller than the above pitch because of the connection with the drive IC for applying a predetermined signal to each terminal.
【０００５】[0005]
【発明が解決しようとする課題】ゲート配線，ドレイン
配線およびゲート，ドレイン電極端子はガラス基板とに
導電性薄膜を全面に形成し、そしてフォトレジスト工程
により選択的に除去されてパターン化されている。この
とき、フォトレジスト工程において塵埃が導入される
と、本来除去されるべき導電性薄膜部分が除去されずに
そのまま残存することになる。塵埃による薄膜残りは小
さいので、各ＴＦＴおよび画素の一方電極を含んだマト
リクスアレイ部におけるゲート配線，ドレイン配線間の
短絡はほとんど生じない。しかしながら、前述のとおり
ゲート電極端子同士およびドレイン電極端子同士のピッ
チは非常に小さく、その結果として電極端子間の短絡が
生じ得る。また、各電極端子と対応するゲート配線、ド
レイン配線とを結ぶ配線間の短絡も生じやすい。The gate wiring, the drain wiring and the gate and drain electrode terminals are patterned by forming a conductive thin film on the entire surface of a glass substrate and selectively removing them by a photoresist process. . At this time, if dust is introduced in the photoresist process, the conductive thin film portion which should be originally removed remains without being removed. Since the thin film remaining due to dust is small, there is almost no short circuit between the gate wiring and the drain wiring in the matrix array section including each TFT and one electrode of the pixel. However, as described above, the pitch between the gate electrode terminals and between the drain electrode terminals is very small, and as a result, a short circuit may occur between the electrode terminals. Further, a short circuit easily occurs between the wirings connecting the respective electrode terminals and the corresponding gate wirings and drain wirings.
【０００６】したがって、本発明の目的は配線間の短絡
を防止した液晶表示装置を提供することにある。Therefore, an object of the present invention is to provide a liquid crystal display device in which short circuits between wirings are prevented.
【０００７】本発明の他の目的は、マトリクスアレイ基
板の製造工程を増加することなく配線間の短絡を防止し
た液晶表示装置を提供することにある。Another object of the present invention is to provide a liquid crystal display device in which a short circuit between wirings is prevented without increasing the manufacturing process of the matrix array substrate.
【０００８】[0008]
【課題を解決するための手段】本発明による液晶表示装
置は、第１のピッチをもって複数行に配置形成された第
１の配線群と、第２のピッチをもって複数列に配置形成
された第２の配線群と、各第１および第２の配線の交差
部分に形成されたＴＦＴと、前記第１のピッチよりも小
さいピッチをもって配置形成された電極端子群と、各電
極端子を対応する第１の配線にそれぞれ接続する部分配
線群と、第１の配線群、電極端子群の一部および部分配
線群を覆う絶縁層とが絶縁基板上に形成されており、か
つ隣り合う電極端子間および部分配線間の上記絶縁層に
絶縁基板に達するスリットが設けられているアクティブ
マトリクスアレイ基板を備えている。A liquid crystal display device according to the present invention includes a first wiring group arranged in a plurality of rows with a first pitch and a second wiring group arranged in a plurality of columns with a second pitch. Wiring group, TFTs formed at the intersections of the first and second wirings, an electrode terminal group arranged and formed at a pitch smaller than the first pitch, and first electrode terminals corresponding to the electrode terminals. A partial wiring group connected to each wiring, a first wiring group, a part of the electrode terminal group and an insulating layer covering the partial wiring group are formed on an insulating substrate, and between adjacent electrode terminals and a part thereof. An active matrix array substrate having slits reaching the insulating substrate is provided in the insulating layer between the wirings.
【０００９】また、本発明では、絶縁基板上に上記第１
の配線群、電極端子および部分配線を形成した後に絶縁
膜を全面に形成し、上記電極端子の一部を露出するため
の絶縁膜に対する選択エッチングのときに隣り合う電極
端子間および部分配線間の絶縁層にスリットを設けてお
り、そして上記第２配線群の形成のための選択エッチン
グを上記スリットにより露出した部分に対しても実行し
ている。Further, according to the present invention, the first substrate is formed on the insulating substrate.
After forming the wiring group, the electrode terminals and the partial wiring, the insulating film is formed on the entire surface, and between the adjacent electrode terminals and the partial wiring during the selective etching for the insulating film for exposing a part of the electrode terminals. A slit is provided in the insulating layer, and selective etching for forming the second wiring group is also performed on the portion exposed by the slit.
【００１０】かくして、本発明によれば、隣り合う電極
端子同士、部分配線同士、さらには電極端子と部分配線
とを短絡する導電性層が残存していても、スリットによ
って当該短絡は切断されることになる。Thus, according to the present invention, even if the conductive layer that short-circuits the adjacent electrode terminals, the partial wirings, and further the electrode terminal and the partial wiring remains, the short-circuit is cut by the slit. It will be.
【００１１】[0011]
【実施例】以下、図面により本発明の実施例を詳細に説
明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１２】図１を参照すると、本発明一実施例による
液晶表示装置のアクティブマトリクスアレイ基板の平面
図が示されている。本基板は所謂配向膜を形成する直前
の状態を示している。Referring to FIG. 1, there is shown a plan view of an active matrix array substrate of a liquid crystal display device according to an embodiment of the present invention. This substrate shows a state immediately before forming a so-called alignment film.
【００１３】すなわち、ガラス基板１上にＴＦＴＱがｎ
行ｍ列のマトリクス状に配置形成されている。各ＴＦＴ
Ｑはゲート電極Ｇ、この電極上にゲート絶縁膜（図示せ
ず）を介して形成された半導体層ＳＳ、この半導体層の
両端部に形成されたドレイン電極Ｄおよびソース電極Ｓ
を有する。各ソース電極には画素を構成するための一方
の透明電極ＰＳが接続されている。That is, the TFT Q is n on the glass substrate 1.
They are arranged and formed in a matrix of rows and m columns. Each TFT
Q is a gate electrode G, a semiconductor layer SS formed on this electrode via a gate insulating film (not shown), a drain electrode D and a source electrode S formed at both ends of this semiconductor layer.
Have. One transparent electrode PS for forming a pixel is connected to each source electrode.
【００１４】同一の行をなすＴＦＴＱの各ゲート電極Ｇ
はゲート配線ＧＣにより共通接続されている。したがっ
て、ｎのゲート配線ＧＣ１乃至ＧＣｎが所定のピッチを
もってｎ行を構成するように形成されている。同一の列
をなすＴＦＴＱの各ドレイン電極Ｄはドレイン配線ＤＣ
により共通接続され、したがって、ｍのドレイン配線Ｄ
Ｃ１乃至ＤＣｍが所定のピッチをもってｍ列をなしてい
る。Each gate electrode G of the TFTs Q forming the same row
Are commonly connected by a gate line GC. Therefore, n gate wirings GC1 to GCn are formed so as to form n rows with a predetermined pitch. The drain electrodes D of the TFTs Q in the same column are drain wiring DC
Connected in common by the
C1 to DCm form m rows with a predetermined pitch.
【００１５】各ゲート配線ＧＣは対応するゲート電極端
子ＴＧに部分配線ＰＧを介して接続されている。図示す
るように、ゲート電極端子ＴＧ１〜ＴＧｎのピッチは非
常に小さい。これは、各ゲート電極端子ＴＧにゲート信
号を供給するＩＣがテープキャリアで形成されるためで
ある。同様に、各ドレイン配線ＤＣは、非常に小さいピ
ッチをもって形成されたドレイン電極端子ＴＤ１〜ＴＤ
ｍの対応する端子に部分配線ＰＤを介して形成されてい
る。本実施例では、後で詳述するが、ドレイン電極端子
ＴＤおよび部分配線ＰＤはドレイン配線ＤＣより前に形
成されるゲート電極端子ＴＧおよび部分配線ＰＧと同時
に形成されるので、各ドレイン配線ＤＣはコンタクトＣ
Ｃを介して対応する部分配線ＰＤに接続されている。Each gate wiring GC is connected to a corresponding gate electrode terminal TG via a partial wiring PG. As shown in the figure, the pitch of the gate electrode terminals TG1 to TGn is very small. This is because an IC that supplies a gate signal to each gate electrode terminal TG is formed of a tape carrier. Similarly, each drain wiring DC has drain electrode terminals TD1 to TD formed with a very small pitch.
It is formed on the corresponding terminal of m through the partial wiring PD. In this embodiment, as will be described later in detail, since the drain electrode terminal TD and the partial wiring PD are formed at the same time as the gate electrode terminal TG and the partial wiring PG formed before the drain wiring DC, each drain wiring DC is formed. Contact C
It is connected to the corresponding partial wiring PD via C.
【００１６】さらに、本基板には、本発明に従ってスリ
ットＳＧ，ＳＤが隣り合うゲート電極端子ＴＧ間および
これから延びる部分配線ＰＧ間に、また隣り合うドレイ
ン電極端子ＴＤ間およびこれらから延びる部分配線ＰＤ
間にそれぞれ設けられている。かかるスリットＳＧ，Ｓ
Ｄにより、ＧＳＤおよびＤＳＤとしてするゲート間短絡
導電膜およびドレイン間短絡導電膜が切断され、互なる
行のゲート間および互なる列のドレイン間の電気的絶縁
が保たれる。Further, on the present substrate, according to the present invention, the slits SG and SD are provided between the adjacent gate electrode terminals TG and between the partial wirings PG extending therefrom, and between the adjacent drain electrode terminals TD and the partial wiring PD extending therefrom.
It is provided between each. Such slits SG, S
D disconnects the inter-gate short-circuit conductive film and the inter-drain short-circuit conductive film used as GSD and DSD, and maintains the electrical insulation between the gates in the rows and the drains in the columns.
【００１７】すなわち、図２に図１の線Ａ−Ａ′に沿っ
た断面図を示すように、ガラス基板１上には部分配線Ｐ
Ｇが選択的に形成されている。この選択形成は、まずガ
ラス基板１の全面に導電性薄膜を形成しフォトレジスト
を用いたパターニングにより行なわれるものであるが、
フォトレジスト工程に混入したホコリにより部分配線Ｐ
Ｇ２およびＰＧ３を短絡する短絡導電膜ＧＳＤが残存し
ている。そこで、各電極端子ＴＧ，ＴＤ，部分配線Ｐ
Ｇ，ＰＤおよびゲート配線ＧＣを形成した後にゲート絶
縁膜１０を全面に形成し、電極端子ＴＧ，ＴＤの一部を
露出する穴を絶縁膜１０に形成するための選択エッチン
グ工程を利用してスリットＳＧを同時に形成している。
このスリットＳＧにより短絡導電膜ＧＳＤ，ＤＳＤの一
部が露出し、同膜がないところは基板１の一部が露出す
る。次いで、ドレイン配線ＤＣが形成されるわけである
が、このときの選択エッチングを利用して短絡導電膜Ｇ
ＳＤ，ＤＳＤもエッチングされ切断される。そして、全
面にパッシベーション膜としての絶縁膜２０が形成さ
れ、各スリットＳＧ，ＳＤが同膜２０でふさがれる。そ
の後、図示しない配向膜が形成されるのである。That is, as shown in FIG. 2 which is a sectional view taken along the line AA 'in FIG. 1, a partial wiring P is formed on the glass substrate 1.
G is selectively formed. This selective formation is performed by first forming a conductive thin film on the entire surface of the glass substrate 1 and then patterning with a photoresist.
Partial wiring P due to dust mixed in the photoresist process
The short-circuit conductive film GSD that short-circuits G2 and PG3 remains. Therefore, each electrode terminal TG, TD, partial wiring P
After forming the G and PD and the gate wiring GC, the gate insulating film 10 is formed on the entire surface, and a slit is formed by using a selective etching process for forming a hole in the insulating film 10 to expose a part of the electrode terminals TG and TD. SG is formed at the same time.
A part of the short-circuit conductive films GSD and DSD is exposed by the slit SG, and a part of the substrate 1 is exposed where there is no film. Next, the drain wiring DC is formed. The short-circuit conductive film G is formed by utilizing the selective etching at this time.
SD and DSD are also etched and cut. Then, the insulating film 20 as a passivation film is formed on the entire surface, and the respective slits SG and SD are closed by the same film 20. After that, an alignment film (not shown) is formed.
【００１８】かくして、ピッチが小さいがために選択エ
ッチングの際の欠陥にもとづく配線間の短絡が生じて
も、完成後は同短絡は切断されて配線間の絶縁が達成さ
れるのである。Thus, even if a short circuit occurs between wirings due to a defect in the selective etching due to the small pitch, the short circuit is cut off after completion and insulation between the wirings is achieved.
【００１９】次に、本アクティブマトリクスアレイ基板
を得るための製造方法につき説明する。なお、以下では
図１の基板の一部のみを示している。Next, a manufacturing method for obtaining the active matrix array substrate will be described. In the following, only a part of the substrate shown in FIG. 1 is shown.
【００２０】すなわち、図３に示すように、ガラス基板
１上にクロム（Ｃｒ）の導電性薄膜を全面に形成し、選
択エッチングによりパターニングしてゲート配線ＧＣ，
ゲート電極端子ＴＧ，部分配線ＰＧ，ドレイン電極端子
ＴＤ，部分配線ＰＤおよびコンタクト端子ＣＣを形成す
る。各ゲート配線ＧＣにはＴＦＴのゲートＧＳＣの突出
部分が設けられている。この選択エッチングにおけるパ
ターン欠陥により、部分配線ＰＧ２とＰＧ３とを短絡す
る短絡導体ＧＳＤが形成される。That is, as shown in FIG. 3, a conductive thin film of chromium (Cr) is formed on the entire surface of the glass substrate 1, patterned by selective etching, and gate wiring GC,
A gate electrode terminal TG, a partial wiring PG, a drain electrode terminal TD, a partial wiring PD and a contact terminal CC are formed. Each gate line GC is provided with a protruding portion of the gate GSC of the TFT. Due to the pattern defect in the selective etching, the short-circuit conductor GSD that short-circuits the partial wirings PG2 and PG3 is formed.
【００２１】次に、図４のように、全面にゲート絶縁膜
（図示せず）を全面に形成した後、非晶質シリコン（ａ
−Ｓｉ）膜をゲート絶縁膜上に全面に形成し、パターニ
ングすることにより、ＴＦＴのａ−Ｓｉ膜Ｓを選択的に
形成する。Next, as shown in FIG. 4, after a gate insulating film (not shown) is formed on the entire surface, amorphous silicon (a) is formed.
The -Si) film is formed on the entire surface of the gate insulating film and patterned to selectively form the a-Si film S of the TFT.
【００２２】この後、各ゲートおよびドレイン電極端子
ＴＧ，ＴＤのためのコンタクト穴ＴＧＣ，ＴＤＣおよび
コンタクト端子ＣＣのためのコンタクト穴ＣＣＣを形成
するためにゲート絶縁膜を選択的にエッチングするわけ
であるが、このエッチング工程によりスリットＳＧおよ
びＳＤも形成する（図５）。かくして、図６に図５の線
Ｂ−Ｂ′に沿った断面図からより明らかになるように、
スリットＳＧによりゲート絶縁膜１０の一部が除去され
て短絡導体ＧＳＤの一部が露出される。短絡導体がない
ところはガラス基板１の一部が露出する。Thereafter, the gate insulating film is selectively etched to form contact holes TGC, TDC for the gate and drain electrode terminals TG, TD and a contact hole CCC for the contact terminal CC. However, the slits SG and SD are also formed by this etching process (FIG. 5). Thus, in FIG. 6, as will be more apparent from the cross-sectional view along line BB ′ of FIG.
The slit SG removes a part of the gate insulating film 10 to expose a part of the short-circuit conductor GSD. A part of the glass substrate 1 is exposed where there is no short-circuit conductor.
【００２３】ゲート絶縁膜１０に対する選択エッチング
後、図７のように、Ｃｒの導電性薄膜を全面に形成し、
パターニングすることにより、ドレイン配線ＤＣおよび
コンタクト穴ＴＧＣ，ＴＤＣを埋める電極導体層１５，
１６を形成する。各ドレイン配線ＤＣはさらにコンタク
ト穴ＣＣＣを介して対応するコンタクト端子ＣＣに接続
され、また、ＴＦＴのドレインＤとしてａ−Ｓｉ膜Ｓの
一端部に接続する突出部分を有している。さらにまた、
ａ−Ｓｉ膜Ｓの他端部に接続されるＴＦＴのソース電極
Ｓが形成される。かかる選択エッチングにより、図８に
図７の線Ｃ−Ｃ′に沿った断面図に明示されるように、
スリットＳＧにより露出された短絡等本ＧＳＤはエッチ
ングされ切断される。かくして、短絡状態にあった部分
配線ＰＧ２およびＰＧ３、そしてＰＤ２およびＰＤ３
（図１）は絶縁分離されることにある。After selective etching of the gate insulating film 10, a conductive thin film of Cr is formed on the entire surface as shown in FIG.
By patterning, the electrode conductor layer 15 filling the drain wiring DC and the contact holes TGC, TDC,
16 is formed. Each drain wiring DC is further connected to a corresponding contact terminal CC via a contact hole CCC, and has a protruding portion connected to one end of the a-Si film S as a drain D of the TFT. Furthermore,
The source electrode S of the TFT connected to the other end of the a-Si film S is formed. By this selective etching, as clearly shown in FIG. 8 in a cross-sectional view taken along line CC ′ of FIG.
This GSD such as a short circuit exposed by the slit SG is etched and cut. Thus, the partial wirings PG2 and PG3 that were in the short-circuited state, and PD2 and PD3
(Fig. 1) is to be isolated.
【００２４】しかる後、図９のように透明電極薄膜を全
面に形成し、選択エッチングを行うことにより、ソース
Ｓに接続された各画素の一方の電極ＰＳを形成する。ま
た、このとき、電極導体層１５，１６を覆うように透明
電極導体膜１７，１８も残している。この後、パッシベ
ーション膜２０が全面に形成され、各電極端子のための
コンタクト穴が形成される（図９の線Ｄ−Ｄ′に沿った
断面図である図１０参照）。Thereafter, a transparent electrode thin film is formed on the entire surface as shown in FIG. 9 and selective etching is performed to form one electrode PS of each pixel connected to the source S. At this time, the transparent electrode conductor films 17 and 18 are also left so as to cover the electrode conductor layers 15 and 16. After that, the passivation film 20 is formed on the entire surface, and contact holes for each electrode terminal are formed (see FIG. 10, which is a cross-sectional view taken along the line DD ′ of FIG. 9).
【００２５】その後、配向膜がマトリクスアレイ部分に
のみスクリーン印刷され、所謂ラビング処理を施し、共
通電極が形成されたもう一方の基板と対向するように重
ねられ、液晶が封止されて液晶表示装置が完成する。After that, an alignment film is screen-printed only on the matrix array portion, subjected to a so-called rubbing treatment, and laminated so as to face the other substrate on which the common electrode is formed, the liquid crystal is sealed, and the liquid crystal display device is formed. Is completed.
【００２６】このように、本製造によればアクティブマ
トリクスアレイ基板を製造するに必要な工程を用いて短
絡導体を切断している。何ら工程の増加はない。As described above, according to the present manufacturing, the short-circuit conductor is cut by using the steps necessary for manufacturing the active matrix array substrate. There is no increase in the number of processes.
【００２７】上述したように、ＴＦＴのマトリクスアレ
イ部分は各配線のピッチが比較的大きいので、本発明に
よるスリットは設ける必要はないが、画素子数が増大す
るとそのピッチは小さくなってゆき、このため、マトリ
クスアレイ部においても短絡が生じることが考えられ
る。As described above, since the pitch of each wiring is relatively large in the matrix array portion of the TFT, it is not necessary to provide the slit according to the present invention, but the pitch becomes smaller as the number of picture elements increases. Therefore, it is conceivable that a short circuit may occur also in the matrix array section.
【００２８】そこで、図１０〜図１４のように、各ＴＦ
Ｔ（すなわち各画素）において、透明電極Ｓの一辺又は
複数辺に沿ってスリットＰＳＳを設けてもよい。本スリ
ットＰＳＳはスリットＳＧ，ＳＤと同一工程で形成され
る。Therefore, as shown in FIGS. 10 to 14, each TF is
In T (that is, each pixel), the slit PSS may be provided along one side or a plurality of sides of the transparent electrode S. This slit PSS is formed in the same process as the slits SG and SD.
【００２９】かかるスリットＰＳＳによってゲート配線
ＧＣ同士の短絡は切断できるが、ドレイン配線ＤＣ同士
の短絡は切断できない、そこで、図１５に示すように、
各ＴＦＴに対し、ドレイン配線短絡切断用スリットＰＤ
Ｓを設けている。The slit PSS can cut the short circuit between the gate wirings GC, but cannot cut the short circuit between the drain wirings DC. Therefore, as shown in FIG.
Drain wiring short circuit cutting slit PD for each TFT
S is provided.
【００３０】図１６に図１５のＥ−Ｅ′線に沿った断面
図を示すように、スリットＰＤＳは、パッシベーション
膜２０の選択エッチング工程（図１０）と同時に形成さ
れる。この後、工程は追加されるが、ホトレジスト３０
を全面に形成し、スリットＰＤＳに沿って開孔を設けて
Ｃｒに対するエッチャントを用いたエッチングを施すこ
とにより、ドレイン配線ＤＳ同士を短絡する導体が切断
される。図１１〜図１４と図１５とは各ＴＦＴに両方と
も適用することができる。As shown in FIG. 16 which is a sectional view taken along line EE ′ of FIG. 15, the slit PDS is formed simultaneously with the selective etching step (FIG. 10) of the passivation film 20. After this, steps are added, but the photoresist 30
Is formed on the entire surface, an opening is provided along the slit PDS, and etching is performed using an etchant for Cr, whereby the conductor that short-circuits the drain wirings DS is cut. Both FIGS. 11 to 14 and FIG. 15 can be applied to each TFT.
【００３１】[0031]
【発明の効果】以上のとおり、本発明によれば導電体の
パターニングの際にパターン欠陥で配線間に短絡導体層
が残っても、同層は切断されて、配線間の絶縁が行なわ
れたアクティブマトリクスアレイ基板が提供され、ま
た、同絶縁が製造工程の増加なしに実行し得る同基板の
製造方法が提供される。As described above, according to the present invention, even if a short-circuit conductor layer remains between wirings due to a pattern defect during patterning of the conductor, the short-circuiting conductor layer is cut and the wirings are insulated. An active matrix array substrate is provided, and a method for manufacturing the same is provided, in which the insulation can be performed without increasing the number of manufacturing steps.
【図１】本発明の一実施例を示すアクティブマトリクス
アレイ基板の平面図。FIG. 1 is a plan view of an active matrix array substrate showing an embodiment of the present invention.
【図２】図１のＡ−Ａ′線に沿った断面図。FIG. 2 is a sectional view taken along the line AA ′ of FIG.
【図３】本発明の一実施例による製造工程の１段階を示
す平面図。FIG. 3 is a plan view showing one stage of a manufacturing process according to an embodiment of the present invention.
【図４】本実施例による製造工程の他の段階を示す平面
図。FIG. 4 is a plan view showing another stage of the manufacturing process according to the present embodiment.
【図５】本実施例による製造工程のさらに他の段階を示
す平面図。FIG. 5 is a plan view showing still another stage of the manufacturing process according to the present embodiment.
【図６】図５のＢ−Ｂ′線に沿った断面図。6 is a cross-sectional view taken along the line BB ′ of FIG.
【図７】本実施例による製造工程のさらに他の段階を示
す平面図。FIG. 7 is a plan view showing still another stage of the manufacturing process according to the present embodiment.
【図８】図７のＣ−Ｃ′線に沿った断面図。8 is a cross-sectional view taken along the line CC 'of FIG.
【図９】本実施例による製造工程のさらに他の段階を示
す平面図。FIG. 9 is a plan view showing still another stage of the manufacturing process according to the present embodiment.
【図１０】図９のＤ−Ｄ′線に沿った断面図。10 is a cross-sectional view taken along the line DD ′ of FIG.
【図１１】本発明によるアクティブマトリクスアレイ基
板のＴＦＴ部の変形例を示す平面図。FIG. 11 is a plan view showing a modification of the TFT section of the active matrix array substrate according to the present invention.
【図１２】ＴＦＴ部の他の変形例を示す平面図。FIG. 12 is a plan view showing another modification of the TFT section.
【図１３】ＴＦＴ部のさらに他の変形例を示す平面図。FIG. 13 is a plan view showing still another modification of the TFT section.
【図１４】ＴＦＴ部のさらに他の変形例を示す平面図。FIG. 14 is a plan view showing still another modification of the TFT section.
【図１５】ＴＦＴ部のさらに他の変形例を示す平面図。FIG. 15 is a plan view showing still another modification of the TFT section.
【図１６】図１５のＥ−Ｅ′線に沿った断面図。16 is a sectional view taken along line EE ′ of FIG.
１ ガラス基板 Ｑ ＴＦＴ Ｇ ゲート電極 ＳＳ 半導体層 Ｄ ドレイン電極 Ｓ ソース電極 ＰＳ 透明電極 ＧＣ1 〜ＧＣｎ ゲート配線 ＤＣ1 〜ＤＣｍ ドレイン配線 ＴＧ ゲート電極端子 ＴＤ ドレイン電極端子 ＳＧ，ＳＤ スリット ＧＳＤ，ＤＳＤ 短絡導電膜 ＴＧＣ，ＴＤＣ，ＣＣＣ コンタクト穴 ＣＣ コンタクト端子1 glass substrate Q TFT G gate electrode SS semiconductor layer D drain electrode S source electrode PS transparent electrode GC 1 to GCn gate wiring DC 1 to DCm drain wiring TG gate electrode terminal TD drain electrode terminal SG, SD slit GSD, DSD short-circuit conductive film TGC, TDC, CCC contact hole CC contact terminal
Claims (12)
と、複数列に配置形成された第２の配線群と、各第１お
よび第２の配線の交差部分に形成された薄膜トランジス
タと、列方向に配置形成された複数の電極端子と、これ
ら電極端子を前記第１の配線群の対応する配線にそれぞ
れ接続する部分配線群と、前記第１の配線群、前記複数
の電極端子の夫々の一部および前記部分配線を覆う第１
の絶縁膜とが絶縁基板上に形成され、かつ隣り合う前記
電極端子間および部分配線間の前記絶縁膜に前記絶縁基
板に達するスリットが設けられていることを特徴とする
液晶表示装置。1. A first wiring group arranged and formed in a plurality of rows, a second wiring group arranged and formed in a plurality of columns, and a thin film transistor formed at an intersection of each of the first and second wirings. A plurality of electrode terminals arranged in the column direction, a partial wiring group connecting the electrode terminals to corresponding wirings of the first wiring group, a wiring group of the first wiring group, and a plurality of electrode terminals of the plurality of electrode terminals. First covering each part and the partial wiring
Is formed on an insulating substrate, and a slit reaching the insulating substrate is provided in the insulating film between the adjacent electrode terminals and between the partial wirings.
された透明導体層を有し、前記透明導体層の少なくとも
一つの辺に沿って前記絶縁基板に達するスリットが前記
第１の絶縁膜にさらに設けられていることを特徴とする
請求項１記載の液晶表示装置。2. The thin film transistor has a transparent conductor layer connected to its electrode, and a slit reaching the insulating substrate along at least one side of the transparent conductor layer is further provided in the first insulating film. The liquid crystal display device according to claim 1, wherein
された透明導体層を有し、前記第１の絶縁膜および前記
第２の配線群は第２の絶縁膜で覆われており、前記透明
導体層の少なくとも一つの辺に沿って前記第１の絶縁膜
に達するスリットが前記第２の絶縁膜にさらに設けられ
ていることを特徴とする請求項１記載の液晶表示装置。3. The thin film transistor has a transparent conductor layer connected to an electrode thereof, and the first insulating film and the second wiring group are covered with a second insulating film. 2. The liquid crystal display device according to claim 1, further comprising a slit reaching the first insulating film along at least one side of the second insulating film.
と、複数列に配置形成された第２の配線群と、これら第
１および第２の配線の各交差部分に形成された薄膜トラ
ンジスタと、列方向に配置形成された複数の第１の電極
端子と、これら第１の電極端子を前記第１の配線群の対
応する配線にそれぞれ接続する第１の部分配線群と、行
方向に配置形成された複数の第２の電極端子と、これら
第２の電極端子から延在形成された第２の部分配線群
と、前記第１の配線群、前記第１および第２の部分配線
群ならびに前記複数の第１および第２の電極端子の夫々
の一部を覆う第１の絶縁膜と、前記第２の配線群を覆っ
て前記第１の絶縁膜上に形成された第２の絶縁膜と、前
記第１の絶縁膜に選択的に形成された前記第２の部分配
線群を前記第２の配線にそれぞれ接続するための複数の
コンタクト穴とが絶縁基板上に形成され、さらに、隣り
合う前記第１の電極端子間および前記第１の部分配線間
の前記第１の絶縁膜ならびに隣り合う前記第２の電極端
子間および前記第２の部分配線間の前記第１の絶縁膜に
前記絶縁基板に達するスリットがそれぞれ設けられてい
ることを特徴とする液晶表示装置。4. A first wiring group arranged in a plurality of rows, a second wiring group arranged in a plurality of columns, and a thin film transistor formed at each intersection of the first and second wirings. A plurality of first electrode terminals arranged and formed in the column direction, a first partial wiring group connecting the first electrode terminals to corresponding wirings in the first wiring group, and a first partial wiring group in the row direction. A plurality of second electrode terminals arranged and formed, a second partial wiring group extending from the second electrode terminals, the first wiring group, and the first and second partial wiring groups And a first insulating film covering a part of each of the plurality of first and second electrode terminals, and a second insulating film formed on the first insulating film to cover the second wiring group. A film and the second partial wiring group selectively formed on the first insulating film as the second wiring. A plurality of contact holes for connecting to each other are formed on the insulating substrate, and further, the first insulating film between the first electrode terminals adjacent to each other and the first partial wiring and the second electrode adjacent to each other. 2. A liquid crystal display device, wherein slits reaching the insulating substrate are provided in the first insulating film between the electrode terminals and between the second partial wirings.
られていることを特徴とする請求項４記載の液晶表示装
置。5. The liquid crystal display device according to claim 4, wherein the slit is filled with the second insulating film.
導電層を選択的に除去することにより、複数行に配設さ
れた第１の配線群、これら配線群にそれぞれ対応する複
数の電極端子、および前記第１の配線群の夫々を対応す
る電極端子にそれぞれ接続する部分配線を形成する工程
と、前記第１の配線群、前記複数の電極端子および前記
部分配線を覆って前記絶縁基板上に絶縁膜を形成する工
程と、隣り合う前記電極端子間および前記部分配線間の
前記絶縁膜に前記絶縁膜を選択的に除去してスリットを
形成する工程と、第２の導電層を形成しこの導電層を選
択的に除去することにより、複数列に配置された第２の
配線群を形成するとともに、前記第２の導電層のエッチ
ング材に前記スリットの低面をさらす工程とを有するこ
とを特徴とする液晶表示装置の製造方法。6. A first conductive layer formed on a plurality of rows by forming a first conductive layer on an insulating substrate and selectively removing the conductive layer, and a plurality of wiring lines corresponding to the first wiring group. Forming an electrode terminal and a partial wiring connecting each of the first wiring group to a corresponding electrode terminal, and covering the first wiring group, the plurality of electrode terminals and the partial wiring, A step of forming an insulating film on the insulating substrate; a step of selectively removing the insulating film between the adjacent electrode terminals and between the partial wirings to form a slit, and a second conductive layer And selectively removing the conductive layer to form a second wiring group arranged in a plurality of rows and exposing the lower surface of the slit to the etching material of the second conductive layer. A liquid crystal characterized by having Manufacturing method of display device.
１の配線群の夫々の一部に前記絶縁層を介する重なる半
導体層を選択的に形成する工程をさらに有し、前記第２
の配線群の夫々は前記半導体層の一部に接続された部分
をそれぞれ有し、さらに、前記半導体層の他部に接続さ
れた電極層を前記第２の導電層の選択除去により形成す
ることを特徴とする請求項６の液晶表示装置の製造方
法。7. The method further comprises the step of selectively forming a semiconductor layer overlapping with the insulating layer on a part of each of the first wiring groups in a column in which the second conductive layer is formed, Two
Each of the wiring groups has a portion connected to a part of the semiconductor layer, and further, an electrode layer connected to another portion of the semiconductor layer is formed by selectively removing the second conductive layer. 7. The method for manufacturing a liquid crystal display device according to claim 6, wherein.
膜の選択エッチングにより複数のコンタクト穴を形成し
て前記電極端子の夫々一部を露出させ、さらに、前記第
２の導電層の選択エッチングにより前記コンタクト穴を
介して前記電極端子にそれぞれ接触する複数の電極導体
を形成することを特徴とする請求項７記載の液晶表示装
置の製造方法。8. A plurality of contact holes are formed by selective etching of the insulating film at the time of forming the slit to expose a part of each of the electrode terminals, and further by selective etching of the second conductive layer. The method for manufacturing a liquid crystal display device according to claim 7, wherein a plurality of electrode conductors are formed so as to be in contact with the electrode terminals through the contact holes.
導電層を選択的に除去することにより、複数行に配置さ
れた第１の配線群、これら配線にそれぞれ対応する複数
の第１の電極端子、前記第１の配線群の夫々を対応する
第１の電極端子にそれぞれ接続する第１の部分配線群、
複数の第２の電極端子、これら第２の電極端子からそれ
ぞれ延在する第２の部分配線群をそれぞれ形成する工程
と、前記第１の配線群、前記複数の第１および第２の電
極端子ならびに前記第１および第２の部分配線群を覆っ
て前記絶縁基板上に第１の絶縁膜を形成する工程と、前
記第１の絶縁膜を選択的に除去することにより、前記第
２の配線群の夫々の一部を露出される複数のコンタクト
穴ならびに隣り合う前記第１の電極端子間、第１の部分
配線間、前記第２の電極端子間および前記第２の部分配
線間にそれぞれ位置する複数のスリットを設ける工程
と、第２の導電層を形成しこの第２の導電層を選択的に
除去することにより、複数列に配置されかつ前記コンタ
クト穴を介して前記第２の配線群の対応する配線にそれ
ぞれ接続された第２の配線群を形成するととも、前記ス
リットの各々を埋める前記第２の導電層を除去する工程
と、前記第２の配線群を覆うとともに前記スリットの各
々を埋める第２の絶縁膜を形成する工程とを有すること
を特徴とする液晶表示装置の製造方法。9. A first conductive layer formed in a plurality of rows by forming a first conductive layer on an insulating substrate and selectively removing the conductive layer, and a plurality of first wiring groups respectively corresponding to these wirings. A first electrode terminal, a first partial wiring group for connecting each of the first wiring groups to a corresponding first electrode terminal,
Forming a plurality of second electrode terminals and a second partial wiring group respectively extending from the second electrode terminals; the first wiring group; and the plurality of first and second electrode terminals And a step of forming a first insulating film on the insulating substrate so as to cover the first and second partial wiring groups, and the second wiring by selectively removing the first insulating film. Positions of a plurality of contact holes exposing a part of each of the groups and between adjacent first electrode terminals, between first partial wirings, between second electrode terminals, and between second partial wirings. Forming a second conductive layer and selectively removing the second conductive layer, so that the second wiring group is arranged in a plurality of rows and through the contact holes. Second connected to the corresponding wiring of each Forming a wiring group, removing the second conductive layer that fills each of the slits, and forming a second insulating film that covers the second wiring group and fills each of the slits A method for manufacturing a liquid crystal display device, comprising:
の前に前記第１の配線群の夫々の一部と前記第１の絶縁
膜を介してそれぞれ重なる複数の半導体層を選択的に形
成する工程をさらに有し、前記第２の配線群の夫々は対
応する前記半導体層に接続された部分を有しており、さ
らに、前記第２の導電層の選択エッチングにより各半導
体層に接続され前記第２の配線群の前記部分では離間さ
れた電極層を形成し、さらにまた、前記第２の絶縁膜を
形成する前に前記電極層に接続された透明電極層を形成
する工程を有する請求項９記載の液晶表示装置の製造方
法。10. A plurality of semiconductor layers that selectively overlap with a part of each of the first wiring group and the first insulating film are selectively formed before the selective etching of the first insulating film. Further, each of the second wiring groups has a portion connected to the corresponding semiconductor layer, and further connected to each semiconductor layer by selective etching of the second conductive layer. Forming a separated electrode layer in the portion of the second wiring group, and further forming a transparent electrode layer connected to the electrode layer before forming the second insulating film. Item 10. A method for manufacturing a liquid crystal display device according to item 9.
により、前記透明電極層の少なくとも一辺に沿ってスリ
ットがさらに形成される請求項１０記載の液晶表示装置
の製造方法。11. The method of manufacturing a liquid crystal display device according to claim 10, wherein a slit is further formed along at least one side of the transparent electrode layer by selective etching of the first insulating film.
前記透明電極層の少なくとも一辺に沿って前記第１の絶
縁膜に達するスリットを形成する工程をさらに有する請
求項１０又は１１記載の液晶表示装置の製造方法。12. The method according to claim 10, further comprising a step of selectively removing the second insulating film to form a slit reaching at least the first insulating film along at least one side of the transparent electrode layer. Manufacturing method of the liquid crystal display device of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13371293A JP2806740B2 (en) | 1992-06-04 | 1993-06-04 | Liquid crystal display device and manufacturing method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4-143872 | 1992-06-04 | ||
| JP14387292 | 1992-06-04 | ||
| JP13371293A JP2806740B2 (en) | 1992-06-04 | 1993-06-04 | Liquid crystal display device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0651349A true JPH0651349A (en) | 1994-02-25 |
| JP2806740B2 JP2806740B2 (en) | 1998-09-30 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13371293A Expired - Lifetime JP2806740B2 (en) | 1992-06-04 | 1993-06-04 | Liquid crystal display device and manufacturing method thereof |
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| Country | Link |
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| JP (1) | JP2806740B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Production of active matrix substrate and its active matrix substrate |
| JP2000162647A (en) * | 1998-11-26 | 2000-06-16 | Samsung Electronics Co Ltd | Thin-film transistor substrate for liquid crystal display device and its production |
| WO2003029891A1 (en) * | 2001-09-28 | 2003-04-10 | Sanyo Electric Co., Ltd. | Liquid crystal display unit |
| US7136133B2 (en) | 2002-08-20 | 2006-11-14 | Sharp Kabushiki Kaisha | Active matrix substrate, liquid crystal display apparatus having the same, and method for manufacturing the same |
| US7164460B2 (en) | 2000-02-24 | 2007-01-16 | Seiko Epson Corporation | Mounting structure for semiconductor device, electro-optical device, and electronic apparatus |
| JP2008015372A (en) * | 2006-07-07 | 2008-01-24 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| WO2009078200A1 (en) * | 2007-12-19 | 2009-06-25 | Sharp Kabushiki Kaisha | Active matrix substrate, method for manufacturing active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit and television receiver |
| US7839460B2 (en) | 1998-11-26 | 2010-11-23 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for liquid crystal display and method of manufacturing the same |
| TWI396025B (en) * | 2009-06-30 | 2013-05-11 | Au Optronics Corp | Active device array substrate |
| KR20130091218A (en) * | 2012-02-07 | 2013-08-16 | 삼성디스플레이 주식회사 | Liquid crystal display |
| TWI414866B (en) * | 2009-11-27 | 2013-11-11 | Au Optronics Corp | Method of forming pixel structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424326U (en) * | 1987-07-31 | 1989-02-09 |
-
1993
- 1993-06-04 JP JP13371293A patent/JP2806740B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424326U (en) * | 1987-07-31 | 1989-02-09 |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1010583A (en) * | 1996-04-22 | 1998-01-16 | Sharp Corp | Production of active matrix substrate and its active matrix substrate |
| US7839460B2 (en) | 1998-11-26 | 2010-11-23 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for liquid crystal display and method of manufacturing the same |
| JP2000162647A (en) * | 1998-11-26 | 2000-06-16 | Samsung Electronics Co Ltd | Thin-film transistor substrate for liquid crystal display device and its production |
| US8294839B2 (en) | 1998-11-26 | 2012-10-23 | Samsung Display Co., Ltd. | Thin film transistor array panel for liquid crystal display and method of manufacturing the same |
| JP2011237807A (en) * | 1998-11-26 | 2011-11-24 | Samsung Electronics Co Ltd | Thin film transistor for liquid crystal display device and method for manufacturing the same |
| US7978276B2 (en) | 1998-11-26 | 2011-07-12 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for liquid crystal display and method of manufacturing the same |
| US7164460B2 (en) | 2000-02-24 | 2007-01-16 | Seiko Epson Corporation | Mounting structure for semiconductor device, electro-optical device, and electronic apparatus |
| WO2003029891A1 (en) * | 2001-09-28 | 2003-04-10 | Sanyo Electric Co., Ltd. | Liquid crystal display unit |
| US7136133B2 (en) | 2002-08-20 | 2006-11-14 | Sharp Kabushiki Kaisha | Active matrix substrate, liquid crystal display apparatus having the same, and method for manufacturing the same |
| JP2008015372A (en) * | 2006-07-07 | 2008-01-24 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| WO2009078200A1 (en) * | 2007-12-19 | 2009-06-25 | Sharp Kabushiki Kaisha | Active matrix substrate, method for manufacturing active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit and television receiver |
| US8450738B2 (en) | 2007-12-19 | 2013-05-28 | Sharp Kabushiki Kaisha | Active matrix substrate, production method of the same, liquid crystal panel, liquid crystal display device, liquid crystal display unit, and television receiver |
| JP5203391B2 (en) * | 2007-12-19 | 2013-06-05 | シャープ株式会社 | Active matrix substrate, manufacturing method of active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit, television receiver |
| TWI396025B (en) * | 2009-06-30 | 2013-05-11 | Au Optronics Corp | Active device array substrate |
| TWI414866B (en) * | 2009-11-27 | 2013-11-11 | Au Optronics Corp | Method of forming pixel structure |
| KR20130091218A (en) * | 2012-02-07 | 2013-08-16 | 삼성디스플레이 주식회사 | Liquid crystal display |
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