KR20010060586A - method for fabricating array substrate for liquid crystal display device - Google Patents

Abstract

PURPOSE: A method of fabricating an array substrate is to prevent short between a pixel electrode and a semiconductor layer, even though a portion protruded to a pixel region due to patterning defect is contacted with the pixel, thereby increasing yield. CONSTITUTION: A conductive metal is deposited on a substrate(111) and patterned with the first mask to form a gate wire(113) and a gate electrode protruded from the gate wire in one direction. The first insulating layer(114a), an intrinsic semiconductor layer, an impurity semiconductor layer(118a) and a conductive metal layer are formed on the substrate in order. The conductive metal layer is patterned with the second mask and then the impurity semiconductor layer and the conductive metal layer are etched to form a data wire(119a) orthogonal to the gate wire and a source/drain electrode protruded to an upper portion of the gate electrode. An insulating material is deposited on the substrate and then patterned with the third mask. The second insulating layer(121) formed on the drain electrode is etched to form a drain contact hole and, at the same time, the first insulating layer, the semiconductor layer and the second insulating layer on a pixel region are etched. The second insulating layer is patterned and then a side portion of the etched semiconductor layer is oxidized using oxygen.

Description

Method for fabricating array substrate for liquid crystal display device

The present invention relates to an array substrate of a thin film transistor type liquid crystal display device, and more particularly, to an array substrate of a thin film transistor type liquid crystal display device manufactured by simplifying a process.

In general, a liquid crystal display device is largely divided into a display part and a pad part.

The display unit is composed of two transparent substrates having a liquid crystal interposed therebetween. The liquid crystal display device includes a common electrode formed on one substrate, and a thin film for driving each pixel corresponding to a plurality of pixels on the other substrate. Gate and source wirings connected to the gate electrode and the source electrode of the transistor and the thin film transistor are arranged in an array.

The pad part includes a gate pad for applying a signal voltage to the gate wiring and a source pad for applying a data voltage to the source wiring.

The gate pad is configured to be in contact with one surface of the display unit, and the source pad is configured to be in contact with the other surface not facing the gate pad.

In order to form an array as described above, deposition, photolithography, etching, strip, and the like are repeated for each process, and as the number of these repeated processes increases, gate wiring or data wiring and The failure rate of the product due to the damage of other components can be increased, and the cost of the product due to the material cost is increased.

Therefore, in order to overcome the above-mentioned drawbacks, it has been directed to the simplicity of the process, it was possible to shorten the process from the existing 5 mask to 4 mask in general process pattern.

An existing four mask process will be described with reference to the accompanying drawings below.

FIG. 1 is a partial plan view of an array substrate having completed a second mask process among four mask processes.

As shown in the drawing, the gate electrode 13 is formed on the substrate 11 and the gate electrode 15 protruding in one direction on the gate wiring 13 by the first mask process.

Next, the data line 17 and the data line 17 protruding from the data line 17 to the upper portion of the gate electrode 15 are formed on the gate electrode 15 to intersect the gate line 13 by a second mask process. The formed source electrode 19 and the drain electrode 22 spaced apart from the source electrode 19 by a predetermined interval are formed.

In this case, the pixel region P is defined by the intersection of the gate wiring 13 and the data wiring 17.

A manufacturing process of the array substrate including such a configuration will be described below with reference to FIG. 2.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.

As illustrated, a plurality of gate wirings 13 formed in one direction on the substrate 11 are formed by depositing a conductive metal material on the substrate 11 to form a first metal layer and patterning the same using a first mask. And a plurality of gate electrodes 15 (FIG. 1) formed to protrude with a predetermined area in one direction from the gate wiring.

Next, an insulating material, a semiconductor material such as amorphous silicon, and a semiconductor material (n +) containing impurities are deposited on the entire surface of the substrate on which the gate wiring 13 is formed, and then a conductive metal material is continuously deposited to form a first insulating layer. 14, the semiconductor layer 16, the impurity semiconductor layer 18, and the second metal layer are formed.

Next, after patterning the second metal layer using a second mask, the second metal layer and the impurity semiconductor layer under the same are simultaneously etched to planarly overlap the impurity semiconductor layer 18. And a source electrode (19 in FIG. 1) which protrudes and has a predetermined area over the gate electrode (15 in FIG. 1) in the data line.

Next, a process of forming a second insulating layer by depositing an insulating material on the entire surface of the substrate on which the source electrode or the like is formed is performed.

3 is a partial plan view of the array substrate completed until the third mask process, which is the next process after the process shown in FIG.

As shown in FIG. 3, in the process of patterning the second insulating layer, a pattern such as a portion A protruding onto the pixel region P where the gate wiring 13 and the data wiring 17 cross each other. Defects may occur.

4 is a cross-sectional view taken along the line II-II of FIG. 3.

As shown in FIG. 2, after the second mask process of FIG. 2, an insulating material is deposited on the entire surface of the substrate on which the data line 17 is formed, a second insulating layer is formed, and then patterned by a third mask process. A portion of the second insulating layer 21 on the drain electrode 19 of FIG. 3 is etched to form a drain contact hole 23 of FIG. 3, and at the same time, the left side of the data line 17 and the gate line 13 are formed. At the same time, the second insulating layer 21, the semiconductor layer 16 and the first insulating layer 14 (see FIG. 1) below are simultaneously etched to expose the substrate 11 in the pixel region P. do.

At this time, as described in FIG. 1 during the lateral etching, protruding pattern defects A may occur on the pixel region due to dust particles or organic foreign matter.

FIG. 5 is a partial plan view of a pixel electrode in a pixel area of the array substrate of FIG. 3.

The pixel electrode 25 is formed on the pixel region P in which the second insulating layer, the semiconductor layer, and the first insulating layer are simultaneously etched. In this case, one side of the pixel electrode 25 overlaps with a predetermined area with the gate wiring 13 passing through the pixel region in one direction, and the other side of the pixel electrode 25 is drained through the drain contact hole 23. It is formed in contact with the electrode 22.

At this time, the protrusions wrongly patterned by the material and the portion B overlapping the pixel electrode 25 are generated.

6 is a cross-sectional view taken along the line VI-VI of FIG. 5.

As shown in the drawing, the semiconductor layer 16 exposed to the side and the pixel electrode 25 come into contact with each other at the portion B where the protruding portion and the pixel electrode overlap each other.

As a result, a short circuit occurs between the semiconductor layer 16 and the pixel electrode 25, which causes an electrical defect in the pixel electrode.

Accordingly, the present invention proposes a method for manufacturing an array substrate for a liquid crystal display device, in which a defect does not occur during the process of the array substrate.

1 is an enlarged plan view showing a part of a conventional array substrate for a display device;

2 is a cross-sectional view showing a cross section taken along II-II of FIG. 1;

3 is an enlarged plan view showing a part of a conventional array substrate for a liquid crystal display device;

4 is a cross-sectional view showing a cross section taken along the line IV-IV of FIG. 3;

5 is an enlarged plan view showing a part of an array substrate for a liquid crystal display device according to the present invention;

6 is a cross-sectional view illustrating a cross section taken along VI-VI of FIG. 5;

7A to 7B are cross-sectional views according to the present invention cut along the line IV-IV of FIG. 3, respectively.

8 is a completed cross-sectional view of the present invention taken along the line VI-VI of FIG. 5.

<Brief description of the main parts of the drawing>

111 substrate 113 gate wiring

114a: first insulating layer 116a: active layer

118a: impurity semiconductor layer 119a: data white line

121: second insulating layer

In order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes the steps of providing a substrate; Depositing a conductive metal on the substrate and patterning the conductive metal on the substrate to form a gate wiring and a gate electrode protruding in one direction from the gate wiring; Stacking a first insulating layer, an intrinsic semiconductor layer, an impurity semiconductor layer, and a conductive metal layer on an entire surface of the substrate on which the gate wiring and the gate electrode are formed; The conductive metal layer is patterned with a second mask to etch the impurity semiconductor layer and the conductive metal layer to form data wirings orthogonal to the gate wirings, and source / drain electrodes protruding from the data wirings over the gate electrodes. Making a step; An insulating material is deposited on the entire surface of the substrate on which the data line, the source electrode and the drain electrode are formed, and patterned with a third mask to etch the second insulating layer on the drain electrode to form a drain contact hole, and at the same time, the pixel region. Etching the first insulating layer, the semiconductor layer and the second insulating layer on the substrate; After patterning the second insulating layer, oxidizing and insulating side surfaces of the etched semiconductor layer using oxygen; Depositing a transparent conductive metal on the entire surface of the substrate on which the side of the semiconductor layer is oxidized; Patterning the transparent electrode with a fourth mask to form a pixel electrode in which one side contacts the drain electrode through the drain contact hole and the other side overlaps a part of the gate wiring.

The conductive metal constituting the gate wiring is one selected from the group of low resistance metals including aluminum or aluminum alloys, silver alloys, and copper.

The transparent conductive metal may be indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin oxide (ITZO).

In the process of oxidizing the etched semiconductor side is characterized in that the use of oxygen in the plasma state.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Before describing the drawings, the process of depositing and etching the second insulating layer in the prior art is the same in the present invention. Hereinafter, the process according to the present invention will be briefly described with reference to FIG. 7.

7A to 7B are cross-sectional views of the array substrate for a liquid crystal display device according to the present invention, taken along II-II of FIG. 3.

As shown in FIG. 7A, after the low-resistance metal material is deposited on the substrate 111, aluminum (Al), aluminum alloy, silver alloy, copper (Cu), and the like, the gate wiring 113 is formed by a first mask process. After forming the gate electrode 15 of FIG. 1, the first insulating layer 114, the semiconductor layer 116, and the impurity semiconductor layer 118 are formed on the entire surface of the substrate on which the gate wiring 113 and the like are formed. The conductive metal layer 119 is laminated successively.

Next, as shown in FIG. 7B, the conductive metal layer 119 is patterned by a second mask process, and the impurity semiconductor layer 118 and the conductive metal layer 119 are simultaneously etched to form the data line 119a and the source. An electrode (not shown) and a drain electrode (not shown) are formed. In this case, the data line 119a and the gate line 113 cross each other to define the pixel area P. FIG.

Next, a second insulating layer 121 is formed on the substrate 111 on which the data wiring 119a is formed, and the second insulating layer, the semiconductor layer 116 and the first insulating layer 114 below the second insulating layer 121 are formed. The substrate 111 is exposed in the pixel region P by simultaneously etching the same.

In this case, in the process of simultaneously etching the second insulating layer 121, the semiconductor layer 116, and the first insulating layer 114, when the plurality of layers are stacked, dust particles or organic foreign substances are caused by static electricity. It may be attached to the wiring side, and as a result, there may be a portion protruding and patterning toward the pixel region as described above in the next etching process.

Next, a process of oxidizing the array substrate 111 is performed. This method uses 0 ₂ plasma or maintains the atmosphere temperature of the chamber in which the substrate is located at 25 ° C. or higher to oxygen (O ₂ ). Choose how to expose.

Further, in order to further promote the reaction of the exposed silicon and oxygen, there is a method of oxidizing through a predetermined heat treatment, and a method of promoting oxidation of the exposed silicon by oxygen reaction using ultraviolet rays.

In this case, an etched side of the semiconductor layer formed of amorphous silicon reacts with oxygen to form an oxide insulating film of SiO _X on the side of the semiconductor layer.

FIG. 8 is a cross-sectional view taken along the line VI-VI of FIG. 5 in the following process of FIG. 7B.

As shown in the drawing, an oxide film is formed on the exposed side surface B of the semiconductor layer 116a, and then indium tin oxide (ITO) and indium zinc are formed on the second insulating layer 121. Depositing and patterning a transparent conductive metal such as -oxide (IZO) and indium-tin-zinc-oxide (ITZO), one side of which contacts the drain electrode (not shown) through the drain contact hole (not shown), The other side forms the pixel electrode 125 formed on the pixel region P while overlapping the gate wiring 113 by a predetermined interval.

In this case, the pixel electrode 125 overlaps the exposed side surface of the semiconductor layer among the patterns protruding into the pixel region P. FIG. Since the side surface of the semiconductor layer has already been insulated through an oxidation process in the previous step, an electrical short does not occur even when the transparent electrode 125 is in contact with the transparent electrode 125.

Therefore, the first insulating layer, the active layer and the second insulating layer are simultaneously etched during the manufacturing process of the thin film transistor array substrate according to the present invention manufactured using the four mask process, and then the side surfaces of the etched semiconductor layer are oxidized. The insulating layer is insulated from each other, so that a short circuit defect between the semiconductor layer and the pixel electrode does not occur even when a portion protruding into the pixel region due to a bad pattern is in contact with the pixel electrode, thereby improving the production yield of the product.

Claims (4)

Providing a substrate; Depositing a conductive metal on the substrate and patterning the conductive metal on the substrate to form a gate wiring and a gate electrode protruding in one direction from the gate wiring; Stacking a first insulating layer, an intrinsic semiconductor layer, an impurity semiconductor layer, and a conductive metal layer on an entire surface of the substrate on which the gate wiring and the gate electrode are formed; Patterning the conductive metal layer with a second mask to etch the impurity semiconductor layer and the conductive metal layer to form data wirings orthogonal to the gate wirings, and source / drain electrodes protruding from the data wirings over the gate electrode; Making a step; An insulating material is deposited on the entire surface of the substrate on which the data line, the source electrode and the drain electrode are formed, and patterned with a third mask to etch the second insulating layer on the drain electrode to form a drain contact hole, and at the same time, the pixel region. Etching the first insulating layer, the semiconductor layer and the second insulating layer on the substrate; After patterning the second insulating layer, oxidizing and insulating side surfaces of the etched semiconductor layer using oxygen; Depositing a transparent conductive metal on the entire surface of the substrate on which the side of the semiconductor layer is oxidized; Patterning the transparent electrode with a fourth mask to form a pixel electrode in which one side contacts the drain electrode through the drain contact hole and the other side overlaps with a portion of the gate wiring Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, The conductive metal constituting the gate wiring is one selected from the group of low resistance metals belonging to aluminum, aluminum alloy, silver alloy and copper. The method of claim 1, The transparent conductive metal is indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin oxide (ITZO). The method of claim 1, A method of manufacturing an array substrate for a liquid crystal display device using oxygen in a plasma state in a process of oxidizing the etched semiconductor side.