JPH0650811B2 - on. Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICABILITY The present invention can be used in cases such as when performing fail-safe information processing in the field of railway signals and the like. Regarding a delay circuit, a fail-safe oscillator configured by either PUT or UJT, and a fail-safe logic that stores an output pulse of the oscillator input to the other input terminal when one input terminal has an input voltage By turning on the gate voltage of PUT or the base voltage of UJT forming the oscillator in combination with the product circuit to one input terminal of the AND circuit, the circuit is turned on due to a circuit failure on the oscillator side. Delay. This is to prevent the time from being shortened and to improve fail-safety.

Conventional technology This kind of on. The basics of the delay circuit are based on Japanese Patent Application Laid-Open No. 57-157623 (Japanese Patent Application No. 56-42075) previously proposed by the applicant.
Issue). FIG. 4 shows the ON. Delay circuit, 1 is the power input terminal, 2
Is a constant voltage circuit, 3 is an oscillator, 4 is an amplifier, and 5 is an AND circuit.

The constant voltage circuit 2 is configured to include a transistor Q ₁ , a Zener diode Zd that serves as a reference voltage source, and a resistor R _1, and stabilizes the input voltage Vin supplied to the power supply input terminal 1 to generate an oscillator 3 and a logical product circuit. 4 is supplied with an input voltage Vs (Vs <Vin) serving as a power source.

The oscillator 3 is configured using PUT (programmable unijunction transistor) or UJT (unijunction transistor). here,
An example using a PUT is shown, and a series circuit of a resistor R ₂ and a capacitor C ₁ is provided between a hot side power supply line (a) and a cold side power supply line (b) led from the output end of the constant voltage circuit 2. And the anode A of the PUT is connected to the connection point between the resistor R ₂ and the capacitor C ₁ . Further, a series circuit of resistors R ₄ and R ₅ is connected between the power supply line (a) and the power supply line (b), and the gate G of the PUT is connected to the connection point of the resistors R ₄ and R ₅ . The cathode K of the PUT is connected to the power supply line (B) through the resistor R ₃ .

The amplifier 4 includes resistors R ₆ and R ₇ and a transistor Q ₂ , and amplifies the oscillation output of the oscillator 3 generated at both ends of the resistor R ₃ and then supplies the amplified output to the AND circuit 5 through the capacitor C ₂ .

The AND circuit 5 operates using the input voltage Vs stabilized by the constant voltage circuit 2 as a power source, and the input voltage Vin is supplied to the input terminal A of the two provided input terminals A and B. At this time, when the output pulse of the oscillator 3 is supplied to the input terminal B through the amplifier 4, the output pulse is stored and at the same time, the DC voltage V ₀ is output. Due to this storage operation, a feedback circuit is added from the output side of the AND circuit 5 to the input terminal B by the diode D ₂ . When the output pulse of the oscillator 3 is input to the input terminal B when the input voltage Vin is present at the input terminal A, the feedback circuit performs a self-holding operation, and the output pulse of the oscillator 3 is stored. A clamp diode D ₁ is connected between the input terminal B and the power supply line (a) to clamp the output pulse input to the input terminal B to the input voltage Vs.

The AND circuit 5 is configured as a fail-safe circuit in which two inputs oscillate when a predetermined value is input to generate an output, and the output voltage disappears due to a circuit failure. Such an AND circuit is disclosed in, for example, Japanese Patent Publication No. 45-29045 and Japanese Patent Publication No.
It is known from Japanese Patent Laid-Open No. 48-3077 and is configured by combining an AND operation oscillator and a rectifier circuit. OS of Fig. 4
C ₁ is an AND operation oscillator, and RC ₁ and RC ₂ are rectifier circuits.

On of the above. In delay circuit, as shown in FIG. 5 (a), when the input voltage Vin is supplied to the power supply input terminal 1 at t _0, stabilized input voltage Vs oscillator 3 and a logical product by the constant voltage circuit 2 Applied to the circuit 5, they start operating.

The oscillator 3 has an input voltage Vs as shown in FIG.
From t ₀ when the voltage is applied, the on-state depends on the time constant of the resistor R ₂ and the capacitor C ₁ . Delay. The output pulse P ₁ is generated at t _{1 which is} delayed by the time Td ₁ . The output pulse P ₁ is input to the input terminal B of the AND circuit 5 through the amplifier 4, but the input voltage Vin has already been supplied to the input terminal A of the AND circuit 5 at this point. The input condition in is satisfied, and the delay output V ₀ is generated in the AND circuit 5. A part of the delay output V ₀ is a diode D ₂
Since the input pulse is input to the input terminal B through the feedback circuit, the output pulse is stored by the self-holding operation, and the delayed output V ₀ is continuously obtained.

Problems to be Solved by the Invention By the way, turn on. In the delay circuit, when the circuit fails, the delay output V ₀ becomes zero and the delay circuit is turned on. Delay. Time T
The side where d ₁ is extended is the fail-safe side.

However, when the resistor R ₄ of the oscillator 3 is disconnected while the input voltage Vin is being input to the input terminal A of the AND circuit 5, the charge accumulated in the capacitor C _{1 of the} oscillator 3 is P
It is discharged from the anode A of the UT through the cathode K, and the output pulse Per (see FIG. 5 (b)) is generated across the resistor R ₃ .
(See) occurs. For this reason, the input conditions are satisfied at the input terminals A and B of the AND circuit 5, and the normal ON. Delay. On, shorter than time Td ₁ . Delay. There is a problem that the delay output V ₀ is generated at the time Td ₂ and the fail-safe property is deteriorated.

Means for Solving Problems In order to solve the above-mentioned conventional problems, the present invention provides a PU.
An oscillator that is configured by either T or UJT and that operates using an input voltage as a power source; and an oscillator that operates by using the voltage obtained by stepping down the input voltage as a power source, and input voltage to one of the two input terminals. ON, the output pulse of the oscillator input to the other input terminal is stored and an output voltage is generated at the same time, and the output voltage disappears due to a circuit failure. In the delay circuit, the gate voltage of the PUT or the base voltage of UJT is applied to the one input terminal of the AND circuit.

Action The above configuration is turned on. In the delay circuit, the gate voltage of PUT or the base voltage of UJT that configures the oscillator,
If it is applied to one input of the AND circuit, when the circuit is normal, the input voltage is applied and at the same time, the gate voltage of the PUT or UJ
The base voltage of T is input.

On the other hand, since the input voltage is also applied to the oscillator as a power source, the oscillator starts operating and generates an output pulse with a delay of a time depending on its own oscillation cycle. The output pulse is input to the other input of the AND circuit. As a result, the input condition in the AND circuit is adjusted to produce a delayed output, and the self-holding operation is performed to store the output pulse. Even if the output pulse disappears, the delayed output is continuously obtained.

Next, if the resistance that gives the gate voltage of the PUT or the base voltage of the UJT is disconnected while the input voltage is being applied, there is no input to one input terminal of the AND circuit. Therefore, even if an output pulse is generated in the oscillator due to disconnection, the delay output of the AND circuit is kept at zero and turned on. Delay. It becomes a failure mode on the side where the time is extended and becomes a fail safe.

Embodiment FIG. 1 shows the on. It is an electric circuit diagram of a delay circuit. In the figure, the same reference numerals as those in FIG. 4 denote the same components. In this embodiment, the oscillator 3
One end of the resistor R ₂ that constitute the, by connecting one end of the resistor R ₄ to be connected to the gate G of the PUT, while connected to the power supply input terminal 1, the resistor R which is connected to the gate G of the PUT
The connection point between the resistor ₄ and the resistor R ₅ is connected to the input terminal A of the AND circuit 5 via the diode D ₃ . A capacitor C ₃ is connected between the input terminal A and the ground. The capacitor C ₃ is provided for the purpose of preventing the potential of the input terminal A from decreasing due to the decrease in the gate voltage because the gate voltage of the capacitor C ₃ momentarily decreases when the PUT oscillates. The diode D ₃ is provided to prevent the electric charge of the capacitor C _{3 from} discharging through the resistor R ₅ .

On of the above embodiment. When the circuit is normal, the delay circuit operates in the same manner as described with reference to FIGS. 4 and 5. That is, as described in FIGS. 5A to 5C, t
_{When the} input voltage Vin is supplied to the power input terminal 1 at _0:00 ,
The oscillator 3 starts operation using the input voltage Vin as a power supply, and the logic circuit 5 starts operation using the voltage (stabilized voltage) obtained by stepping down the input voltage Vin as the power supply,
From t ₀ when in is applied, the resistor R ₂ and the capacitor C ₁
The output pulse P ₁ is generated at time t _{1 which is} delayed by the time Td ₁ depending on the time constant. The output pulse P ₁ is input to the input terminal B of the AND circuit 5 through the amplifier 4.

At time t ₁ when the output pulse P ₁ is supplied to the input terminal B,
Since the input voltage Vin has already been supplied to the input terminal A through the resistor R ₄ and the diode D ₃ , the input condition in the AND circuit 5 is satisfied, and the AND circuit 5 produces a delayed output. Since a part of the delayed output is input to the input terminal B through the feedback circuit, the self-holding operation is applied to store the output pulse, and the delayed output V ₀ is obtained.

Next, after the input voltage Vin is applied and before the output pulse P ₁ of the oscillator 3 is generated, the gate voltage of the PUT or UJ.
When the resistor R ₄ which gives the base voltage of T is disconnected, there is no input to the input terminal A of the AND circuit 5. Therefore, even if an output pulse is generated in the oscillator 3 due to the disconnection of the resistor R ₄ , the delay output V ₀ of the AND circuit 5 is kept at zero and turned on. Delay. The failure mode is on the side where the time Td ₁ is extended, and the fail-safe mode is achieved.

The AND circuit 5 is configured as a fail-safe circuit in which the output voltage disappears due to a circuit failure. An example of such an AND circuit 5 is the above-mentioned Japanese Patent Publication No. 45-29045.
The window disclosed in Japanese Utility Model Publication No. 57-4764, in addition to those disclosed in Japanese Patent Publication No. 48-3077. A comparator and an AND circuit proposed as Japanese Patent Application No. 59-81572 can be used. The window disclosed in Japanese Utility Model Laid-Open No. 57-4764 is a window having a window characteristic for at least one of inputs. The AND circuit proposed as Japanese Patent Application No. 59-81572 has a 2-input window. comparator. It is configured as an AND gate.

Fig. 2 is the window disclosed in Japanese Utility Model Laid-Open No. 57-4764. In the electrical circuit diagram of the comparator, the input voltages Va and Vb applied to the input terminals A and B are as follows: {R ₁₃ / (R ₈ + R ₁₂ + R ₁₃ )} Vb> Vs (1) Vf = {R ₁₁ / (R ₁₀ + R ₁₁ )} Va> Vs (provided that Vs <Va) (2) Within the range satisfying the condition, the transistor Q ₄ ,
Q ₅ ; off → transistor Q ₃ ; on → transistor Q
₃ ; ON → transistors Q ₄ and Q ₅ ; ON → transistor Q ₃ ; As a result, an oscillation output oscillating between the input voltage Va applied to the input terminal A and substantially zero volt is obtained at the output terminal V ₀₁ .

That is, this window. The comparator has an input terminal A,
Input voltages Va and Vb applied to B are (1) and (2)
The oscillation output is generated only when it is within the range that can satisfy the formula, and when the input voltage Vb drops below the range that satisfies the formula (1), or when the input voltage Va is above the range that satisfies the formula (2). When the voltage rises or is equal to or lower than the power source Vs, the circuit oscillation is stopped, and the lower and upper limits are generated in the input voltages Vb and Va that can continue the oscillation operation.

This window. In order to configure the AND circuit 5 using the comparator, the gate voltage of the PUT constituting the oscillator 3 is connected to the input terminal A via the diode D ₃ so that the gate voltage is used as the window input. , Oscillator 3
The output pulse of is applied to the input terminal B. Also,
The rectifier circuits RC ₁ and RC ₂ are connected to the output terminal V _01, and the feedback circuit including the diode D ₂ is connected from the rectifier circuit RC ₂ to the input terminal B.

Next, the fail-safe property will be described.

(1) The AND circuit 5 is a circuit whose output disappears when a circuit failure occurs, and is turned on in response to the circuit failure. Delay. This is the direction in which the time Td ₁ extends and is fail-safe.

(2) Disconnection of the resistor R _{1 Since} the power supply to the AND circuit 5 is cut off, the AND circuit 5
The output of is zero, which is fail safe.

(3) Failure of transistor Q ₁ Collector. Since there is no power input to the AND circuit 5 when there is an open-circuit failure between the emitters, it is fail-safe. At the time of a short circuit failure, the voltage of the input terminal A becomes lower than the power supply voltage Vs, so that the output of the AND circuit 5 is zero, which is fail-safe.

(4) Failure of Zener Diode Zd In the case of open circuit failure, it is the same as in the case of short circuit failure of the transistor Q ₁ and it is fail safe. In the case of a short-circuit failure, the power supply voltage of the AND circuit 5 becomes zero, which is fail safe.

(5) Disconnection of resistors R _{2 to} R ₅ PUT cannot oscillate, and thus it is fail safe. When the resistor R ₄ is disconnected when there is an input, it is fail safe as described above.

(6) Failure of Capacitor C ₁ PUT cannot oscillate in both cases of opening and short-circuiting, which is fail-safe.

(7) Disconnection of resistors R ₆ and R _{7 Since} the output pulse of the oscillator 3 does not enter the input terminal B of the AND circuit 5, it is a fail safe.

(8) Transistor Q ₂ collector. In either case of opening or shorting of the emitter, the output pulse of the oscillator 3 does not enter the input terminal B of the AND circuit 5, which is fail-safe. When the transistor Q ₂ is short-circuited while the input voltage Vin is being applied, the input terminal B becomes a negative input. No signal is generated when the transistor Q ₂ is opened.

(9) Failure of PUT Anode. It is fail-safe because it cannot oscillate when the cathode is open. anode. At the time of short circuit between the cathodes, the anode. Since the gates are also short-circuited, there is no oscillation output.

(10) Failure of the capacitor C _{2 When} the capacitor C ₂ is opened, there is no input to the AND circuit 5. At the time of short circuit, the output of the transistor Q ₂ is short-circuited by the diode D ₁ , so that no pulse is input to the input terminal B.

(11) Failure of diode D _{1 When} the diode D ₁ is opened, the clamp action disappears, so that the input voltage to the input terminal B cannot be higher than the power supply voltage Vs. Therefore, the AND circuit 5 cannot oscillate, which is fail safe. At the time of short circuit, the input of input terminal B becomes zero,
The AND circuit 5 cannot oscillate.

(12) Failure of the diode D _{2 When} the diode D ₂ is opened, no feedback is provided, so self-holding is not possible, and delayed output cannot be obtained. At the time of short circuit, the input pulse is rectifier circuit R
Since it is absorbed by the smoothing capacitor of C _2, the AND circuit 5
Cannot oscillate.

(13) Failure of the diode D _{3 When} the diode D ₃ is opened, the input to the input terminal A of the AND circuit 5 becomes zero, so that the AND circuit 5 cannot oscillate. PU in case of short circuit
At the same time when the output pulse of T enters the AND circuit 5, PUT
Due to the decrease in the gate voltage during oscillation, the input to the input terminal A of the AND circuit 5 becomes negative, and the AND circuit 5 cannot oscillate.

(14) Failure of capacitor C ₃ The output pulse of the PUT is input to the input terminal B, and at the same time, the negative pulse from the gate G of the PUT is also input to the input terminal A, and the AND circuit 5 cannot oscillate. Be safe. When a short circuit occurs, the input to the input terminal A of the AND circuit 5 becomes zero, so that the AND circuit 5 cannot oscillate.

FIG. 3 shows ON. It is an electric circuit diagram in another example of a delay circuit. In this embodiment, the oscillator 3
UJT is shown as the base B _{1 of} UJT,
Of the B ₂ , the voltage of the base B ₁ is input to the input terminal A. Also in the case of this embodiment, the on-state is turned on by the similar circuit action. The delayed output of the delay can be obtained and the same fail-safe property can be secured.

EFFECTS OF THE INVENTION As described above, the present invention provides a fail-safe oscillator configured by either PUT or UJT, and an oscillator input to the other input terminal when one input terminal has an input voltage. In combination with a fail-safe AND circuit that stores output pulses, the gate voltage of PUT or the base voltage of UJT that forms the oscillator is applied to one input terminal of the AND circuit, thereby causing a circuit failure including the oscillator. Turned on. Delay. ON with a high degree of fail-safety that does not shorten the time. A delay circuit can be provided.

[Brief description of drawings]

FIG. 1 shows an ON switch according to the present invention. An electric circuit diagram of the delay circuit, FIG. 2 is an ON circuit according to the present invention. A window suitable for constructing a logical product circuit of delay circuits. An electric circuit diagram of the comparator, FIG. An electric circuit diagram of another embodiment of the delay circuit is shown in FIG. An electric circuit diagram of the delay circuit and FIG. 5 are also time charts for explaining the operation thereof. 3 ... Oscillator, 5 ... AND circuit PUT ... Programmable. Unijunction. Transistor UJT ... Unijunction. Transistors R _{1 to} R ₇ ... Resistors C _{1 to} C ₃ ... Capacitors D _{1 to} D ₃ ... Diodes Q ₁ , Q ₂ ... Transistors

Claims (2)

[Claims] 1. An oscillator composed of either PUT or UJT, which operates by using an input voltage as a power source, and an oscillator which operates by using a voltage obtained by stepping down the input voltage as a power source, and one of two input terminals. An AND circuit that stores an output pulse of the oscillator input to the other input terminal when the input voltage is present at the input terminal and simultaneously generates an output voltage, and the output voltage disappears due to a circuit failure.
In the delay circuit, the gate voltage of the PUT or the base voltage of UJT is applied to the one input terminal of the AND circuit. Delay circuit. 2. The AND circuit has a window characteristic in at least one of the two inputs, and the gate voltage or base voltage of the oscillator is used as an input in the window of the AND circuit to oscillate the oscillator. The ON-state according to claim 1, wherein the output is the other input of the AND circuit. Delay circuit.