JPS62104310A - On-delay circuit - Google Patents

On-delay circuit

Info

Publication number
JPS62104310A
JPS62104310A JP24444085A JP24444085A JPS62104310A JP S62104310 A JPS62104310 A JP S62104310A JP 24444085 A JP24444085 A JP 24444085A JP 24444085 A JP24444085 A JP 24444085A JP S62104310 A JPS62104310 A JP S62104310A
Authority
JP
Japan
Prior art keywords
circuit
input
voltage
impressed
fail
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24444085A
Other languages
Japanese (ja)
Other versions
JPH0650811B2 (en
Inventor
Koichi Yomogihara
Kazuo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP24444085A priority Critical patent/JPH0650811B2/en
Publication of JPS62104310A publication Critical patent/JPS62104310A/en
Publication of JPH0650811B2 publication Critical patent/JPH0650811B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To improve the fail-safe performance of an on-delay circuit which is equipped with an oscillator operating with an input voltage as a power source and an AND circuit by applying the gate voltage of PUT or the base voltage of UJT to one input terminal of the AND circuit.
CONSTITUTION: If a resistance R4 impressed with the gate voltage of PUT or the base voltage of UJT is broken before the output pulse P1 of an oscillator 3 is generated after the input voltage Vin is impressed, an input to an input terminal of the AND circuit 5 is ceased. Therefore, even if the oscillator generates the output pulse owing to the wiring breaking of the resistance R4, the delay output V0 of the resistance R4 is held at zero V and the fault mode of the side where an on-delay time Td1 is extended is entered, so that the fail- safe performance is obtained. Namely, a capacitor C3 is connected to the gate G of PUT through a diode D3, so no input is impressed to the input terminal A of the OR circuit 5. Therefore, the AND condition is not satisfied, so the output V0 of the AND circuit 5 is not generated, so fail-safe operation is carried out.
COPYRIGHT: (C)1987,JPO&Japio
JP24444085A 1985-10-31 1985-10-31 on. Delay circuit Expired - Fee Related JPH0650811B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24444085A JPH0650811B2 (en) 1985-10-31 1985-10-31 on. Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24444085A JPH0650811B2 (en) 1985-10-31 1985-10-31 on. Delay circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5311549A Division JP2683608B2 (en) 1993-12-13 1993-12-13 on. Delay circuit

Publications (2)

Publication Number Publication Date
JPS62104310A true JPS62104310A (en) 1987-05-14
JPH0650811B2 JPH0650811B2 (en) 1994-06-29

Family

ID=17118684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24444085A Expired - Fee Related JPH0650811B2 (en) 1985-10-31 1985-10-31 on. Delay circuit

Country Status (1)

Country Link
JP (1) JPH0650811B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722932A (en) * 1993-12-13 1995-01-24 Nippon Signal Co Ltd:The On-delay circuit
EP0644655A1 (en) * 1993-03-31 1995-03-22 The Nippon Signal Co. Ltd. On-delay circuit
WO1997021271A1 (en) * 1995-12-05 1997-06-12 The Nippon Signal Co., Ltd. Fail-safe timer circuit and on-delay circuit using the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644655A1 (en) * 1993-03-31 1995-03-22 The Nippon Signal Co. Ltd. On-delay circuit
EP0644655A4 (en) * 1993-03-31 1995-08-30 Nippon Signal Co Ltd On-delay circuit.
JPH0722932A (en) * 1993-12-13 1995-01-24 Nippon Signal Co Ltd:The On-delay circuit
WO1997021271A1 (en) * 1995-12-05 1997-06-12 The Nippon Signal Co., Ltd. Fail-safe timer circuit and on-delay circuit using the same
US6239956B1 (en) * 1995-12-05 2001-05-29 The Nippon Signal Co., Ltd. Fail-safe timing circuit and on-delay circuit using the same

Also Published As

Publication number Publication date
JPH0650811B2 (en) 1994-06-29

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees