JP2746271B2 - Inverter device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an inverter device for obtaining an AC power supply from a DC power supply, and more specifically, to driving two switching elements connected to a DC power supply. The present invention relates to improvement of characteristics at the time of starting in an inverter device which obtains a power supply voltage from a DC power supply.

[Prior Art] FIG. 13 is a circuit diagram of a conventional inverter device. A series circuit of a pair of switching elements Q ₁ and Q ₂ is connected to both ends of the DC power supply V. The switching elements Q ₁ and Q ₂ are composed of, for example, power MOS transistors. Each of the switching elements Q ₁ and Q ₂ is turned on / off by outputs V ₁ and V ₂ of the drive circuits 1 and ₂ , respectively. The one ends of the switching element Q _2, the load circuit Z is connected. The load circuit Z, for example, a discharge lamp lighting apparatus including an LC resonance circuit of the inductance element L ₀ and capacitor C ₀ is connected.

The series circuit of the resistor R ₁ and the capacitor C ₁ connected to both ends of the switching element Q ₁ is the power supply circuit of the upper circuit, and the series circuit of the resistor R ₂ and the capacitor C ₂ connected to both ends of the DC power supply V is the lower circuit. This is the power supply circuit of the side circuit. Each capacitor C ₁ , C ₂
, Zener diodes ZD ₁ and ZD ₂ for voltage regulation are respectively connected in parallel. The oscillation circuit 3 fed by the capacitor C ₂ has two signals alternating between a high level and a low level.
V _A and V _B are output. Signal V _B is input to the drive circuit 2, the signal V _A via a signal transfer circuit, the drive circuit 1
Is input to

Signal transmission circuit, the transistors Tr ₁ to Tr ₄ and the resistor R _3, R
_The signal transmission is performed without using an insulating element such as a transformer. Transistor Tr ₁ in the signal transmission circuit is connected to the resistor R ₃ in series, is connected across the capacitor C _1. Between the base and emitter of the transistor Tr _1, the transistor Tr ₂ are connected to form a current mirror circuit 4. The base of the transistor Tr ₂ is
It is connected to the collector of the transistor Tr _3. Transistor Tr ₄ is connected to the transistor Tr ₃ form a current mirror circuit 5. If transistors Tr ₁ and Tr ₂ and transistors Tr ₃ and Tr ₄ constituting the current mirror circuits 4 and 5 are usually transistors having the same characteristics and their current gains hfe are extremely high, the current mirror circuits are formed. It can be considered that the current flowing through one transistor becomes the same as the current flowing through the other transistor. That is, the output current I _A of the current mirror circuit 5
Is the same as the constant current I _A ′ that has been lowered in advance, and even if the voltage V _Q2 across the switching element Q ₂ changes greatly with time, a constant current can flow through the transistor Tr ₂ irrespective of that. it can. In this case, the same current as the current flowing through the transistor Tr ₂ is also flowing to the transistor Tr _1, the resistor R
₃ , a current I ₃ (≒ I _A ) flows, and a voltage V ₃ is generated in the resistor R ₃ .
A high-level signal is input to the drive circuit 1. Signal V _A
Is low, a low-level signal is input to the drive circuit 1.

FIG. 14 is an operation waveform diagram of the circuit in FIG. When the time t ₀ in the signal V _A (FIG. 14 (a)) is Korebe Le, current I _A 'flows through the transistor Tr ₄ of the current mirror circuit 5, which the same current I _A (Figure 14 ( c)) flows through the transistor Tr _3. The current I _A flows through the transistor Tr ₂ of the current mirror circuit 4, the same current as it flows through the transistor Tr _1. Thus, a voltage is applied to the resistor R _3, the voltage V ₃
(FIG. 14 (d)) becomes high level and the drive circuit 1
Output V ₁ (FIG. 14 (g)), the switching element Q ₁
Turns on. When the signal V _A becomes a low level at time t _1, current
I _A is stopped, since the output voltage V _3, V ₁ of the drive circuit 1 becomes the low level, the switching element Q ₁ is turned off.

Then, when the time t ₂ the signal V _B (FIG. 14 (b)) goes high, the output V ₂ (FIG. 14 (f)) of the drive circuit 2 becomes the high level, the switching element Q ₂ Turns on. At this time, since the signal _VA is at a low level, the transistors Tr ₃ ,
It does not flow current I _A to the current mirror circuit 5 made of tr _4. Therefore, the transistor Tr of the current mirror circuit 4
₁ is turned off, the voltage V ₃ becomes low level, the output V ₁ of the drive circuit 1 goes low, the switching element Q ₁ is turned off. When the signal V _B goes low at time t _3, the output V ₂ of the drive circuit 2 becomes low level, the switching element
Q ₂ turns off. Hereinafter, the same operation is repeated, and an alternating voltage is supplied to the load circuit Z.

In this conventional example, a current mirror circuit a constant current signal I _A
Since the drive signal is transmitted through 4 and 5, the drive signal is transmitted from the lower oscillation circuit 3 to the upper drive circuit 1 having a different potential without using a base drive transformer or an insulating element such as a photocoupler. It can be transmitted, and it can be said that it is a method suitable for IC.

[Problems to be Solved] In the conventional example described above, the capacitor C ₂ for the power supply of the lower circuit is powered from a DC power supply V through a resistor R _2, but always maintained substantially constant voltage by the Zener diode ZD ₂ ,
Capacitor C ₁ for power supply of the upper circuit are charged in the period t ₁ ~t ₃ the lower switching element Q ₂ is turned on. That is, the voltage V _C1 of the capacitor C ₁ is increased in the period of the switching element Q ₂ is turned on, it lowers the period when the switching element Q ₁ is turned on. When the inverter begins to operate, since the capacitor C ₂ is always current is supplied through the resistor R _2, although the voltage V _C2 is quickly increases, the capacitor C ₁ to the switching operation of the switching element Q ₂ Accordingly, the voltage V _C1 gradually increases. In this startup program, when the output V ₁ of the drive circuit 1 is high, the capacitor C ₁ is to supply energy to the switching element Q _1, as in FIG. 14 is the output V ₁ of the drive circuit 1 (g) Will go down. If the load circuit Z comprises a resonance circuit, the driving signal V _A, since to stabilize the setting to work higher than the natural vibration frequency of the load circuit Z of V _B, the switching element Q ₁ at time t ₁ is is tries to continue to flow a current load circuit Z was flowing when off, current flows voltage V _Q2 of the switching element Q ₂ is reversed in the opposite direction of the switching element Q _2. Therefore, time t ₁
The switching element Q ₂ is the voltage V _C1 of the capacitor C ₁ is increased until the time t ₃ when turned on, the switching element Q ₂ is turned off at time t ₃ from the switching element Q ₁ is a voltage V _Q2 inverts
Reverse current flows through the At this time, since the drive circuit 1 does not supply the driving voltage to the switching element Q _1, the energy consumption is almost no voltage V _C1 of the capacitor C ₁ is not lowered so much, the output V ₁ of the drive circuit 1 at time t ₄ is because a high level, to supply energy to the switching element Q _1,
Start to fall again.

Therefore, although stable voltage is supplied to the switching element Q _2, the switching element Q _1, a capacitor C ₁ of the voltage V _C1 is the switching element Q for the power supply
It means that intermittently increased with _second on-off operation, the voltage supply to the switching element Q ₁ is not stable. When the voltage V _C1 of the capacitor C ₁ increases stepwise, the output V ₁ of the drive circuit ₁ also increases stepwise as shown in FIG. 14 (g). Energy is supplied to the load circuit Z by the on / off operation of the switching elements Q ₁ and Q _2.
When both Q ₁ and Q ₂ are operating, a steady current tends to flow in the load circuit Z by the DC power supply V, and except for the loss at the time of switching, the stress of the switching elements Q ₁ and Q ₂ becomes Often caused by the ON voltage. The switching element Q _2, since from the beginning may be added a sufficient driving voltage, it is possible to suppress the on-voltage V _Q2 low, the switching element Q ₁ is not and stable low driving voltage, the ON voltage As shown in FIG. 7 (k), V _Q1 becomes high between times t _{0 and} t ₁ . Such an increase in the ON voltage V _Q1 of the switching element Q ₁
Cause temperature rise of the switching elements Q _1, particularly stress becomes large when it is desired to supply a large current to the load circuit Z, it has been a cause of the deterioration or destruction switching element Q _1.

The present invention has been made in view of such a point,
It is an object of the present invention to provide a highly reliable inverter device which supplies a stable drive signal to a switching element even at the time of starting and has little deterioration of the switching element.

[Means for Solving the Problems] In the present invention, in order to solve the above problems, as shown in FIG. 1, first and second switching elements
An inverter device in which a series circuit of Q ₁ and Q ₂ is connected to a DC power supply V so that a power supply voltage V _C1 for driving the first switching element Q ₁ is charged when the _second switching element Q ₂ is turned on. Until the power supply voltage V _C1 for driving the first switching element Q ₁ reaches a predetermined voltage, the first switching element Q ₁ is turned off, and the second switching element Q ₂ is turned on. When the power supply voltage reaches a predetermined voltage, the first on-state switching element Q _1, it is characterized in the provision of the control circuit for the second switching element Q ₂ and the off-state.

In the [Operation] The present invention, thus, up to a first driving power supply voltage V _C1 of the switching element Q ₁ is reached to a predetermined voltage, the first off-state switching element Q _1, a second the switching element Q ₂ and the oN state, the when the drive power supply voltage reaches a predetermined voltage, the first on-state switching element Q _1, a control circuit for the second switching element Q ₂ and the off-state is provided in Therefore, when starting the inverter device,
The drive power supply voltages of the first and second switching elements Q ₁ , Q ₂ can both be sufficiently high, and therefore, the on-voltage of each switching element Q ₁ , Q ₂ can be reduced,
The loss can be reduced.

Embodiment 1 FIG. 1 is a circuit diagram of a first embodiment of the present invention. Less than,
The circuit configuration will be described. The both ends of the capacitor C _2, the series circuit of the resistor R ₆ and the capacitor C ₃ is connected. Connection point between the resistor R ₆ and the capacitor C ₃ is connected to one input of the AND circuit G _1, and is connected to one input of NAND circuit G _2. The other input of the AND circuit G _1, the signal V _A of the oscillating circuit 3 are input, the output V of the AND circuit G _1
G1 is input to the transistor Tr _3, Tr ₄ current mirror circuit 5 via a resistor R _4. To the other input of the NAND circuit G ₂ is the signal V _B of the oscillation circuit 3 is input via the NOT circuit G _3, the drive circuit 2 outputs V _G2 of the NAND circuit G ₂ via a resistor R ₅ Has been entered. The other circuit configuration is the same as that of the conventional example, and the corresponding parts are denoted by the same reference numerals and overlapping description will be omitted.

FIG. 2 is an operation waveform diagram of the present embodiment. Hereinafter, the operation of the present embodiment will be described. Circuit of this embodiment, until the upper power supply voltage V _C1 reaches a sufficient voltage is to hold the switching element Q ₂ turned on, the switching element Q ₁ in the OFF state. The time required for the voltage V _C3 of the time constant circuit composed of the resistor R ₆ and the capacitor C ₃ to reach the threshold voltage Vth of the AND circuit G ₁ and the NAND circuit G ₂ is determined by the voltage V of the capacitor C ₁ .
_C1 is set to the degree or, or the same is set longer than the time a normal power supply voltage by turning on the switching element Q _2.

The output signal V _A of the oscillation circuit 3 at time t ₀ becomes a high level, when the voltage V _C3 of the capacitor C ₃ in constant circuit is a low level, the output V _G1 is low-level of the AND circuit G _1, NAND circuit
The output V _{G2 of} G ₂ becomes high level, and the output V
₁ becomes low level, the output V ₂ of the drive circuit 2 is a high level, the switching element Q ₁ is turned off, the switching element Q ₂ is turned on, continuing this state. Also at time t ₂ the signal V _B becomes high level continuing the same state.

Then, increasing the charging voltage V _C3 of the capacitor C ₃ at time t _3, one input of the AND circuit G ₁ and NAND circuit G ₂ becomes high level, the signal V _A is directly next to the output V _G1 of the AND circuit G ₁ ,
Signal V _B is changed to a state where it becomes the output V _G2 of the NAND circuit G _2. At this time, since the signal V _B is high, the switching element Q ₂ to time t ₄ will continue on. And time t ₄
In the switching element Q ₂ is turned off, the switching element Q ₁ is turned on at time t _5. At this time, the voltage V of the capacitor C _{1
Since C1} is sufficiently increased, the voltage across V _Q1 of the switching element Q ₁ is becomes low on-voltage, Therefore, the stress of the switching element Q ₁ is being reduced.

Embodiment 2 FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is an operation waveform diagram thereof. In this embodiment, the capacitor C ₁
Actually detect the increase of the voltage V _C1 of, if the lower detection voltage V _C1 is to maintain the switching element Q ₁ OFF state, the switching element Q ₂ in the ON state. For this, both ends of the capacitor C _1, the light emitting element of the photocoupler PC via a resistor R ₇ is connected. Photo coupler PC
The light receiving elements are connected to both ends of the capacitor C ₂ through the resistor R _6. Connection point between the light receiving element and the resistor R ₆ of the photocoupler PC is connected to the input of the NOT circuit G _4, the output V _G4 of the NOT circuit G ₄ is one input of the AND circuit G ₁ and NAND circuit G ₂ ing. Other configurations are the same as those of the first embodiment.

Hereinafter, the operation of the present embodiment will be described. As shown in FIG. 4, although the time t ₀ in the signal V _A is high, the voltage V _C1 of the capacitor C ₁ is low, the resistance R ₇ and photo-coupler PC
Current flowing through the photocoupler PC is low.
_VR6 is at a high level. Therefore, the output V of the NOT circuit G _4
G4 goes low, the output V _G1 of the AND circuit G ₁ is a low level,
The output V _G2 of the NAND circuit G ₂ is has a high level. This condition, photo voltage V _R6 coupler PC on the output side is intended to continue until the lower threshold voltage Vth of the NOT circuit G _4, at time t ₂ the signal V _B becomes high level, the state Continue.

Then, at time t ₃ the voltage V _R6 of the output side of the photocoupler PC is N
When lower than the threshold voltage Vth of the OT circuit G _4, N
Output V _G4 of OT circuit G ₄ is changed to a high level. From this time, the output V _G1 of the AND circuit G _1, NAND circuit G ₂ of the output V _G2 each signal V _A, becomes the same signal as the signal V _B, the signal from the switching element Q _1, Q ₂ the oscillation circuit 3 Driven by V _A and V _B. Because from time t ₃ signal V _B is high level, the switching element Q ₂ is turned on, the switching element Q ₁ is turned off. Signal V _B goes low at time t _4, the switching element Q ₂ is turned off, the voltage across V _Q2 of the switching element Q ₂ is a high level by the action of the load circuit Z. Signal at a time t ₅
V _A becomes high level, and the input / output voltages V ₃ , V
₁ is at a high level.At this time, since the voltage V _C1 of the capacitor C ₁ is sufficiently high, the voltage V _Q1 across the switching element Q ₁ can be a low on-voltage. is there.

Third Embodiment FIG. 5 is a circuit diagram of a third embodiment of the present invention, and FIG. 6 is an operation waveform diagram thereof. In this embodiment, as in the second embodiment, the voltage V _C1 of the capacitor C ₁ is actually detected, and the switching element Q ₁ is turned off until the voltage V _C1 of the capacitor C ₁ rises to a sufficient voltage. but in which the switching element Q ₂ and the oN state, and it is different from example 2,
Rather than the signal transmitting means of the insulating type transmission means of the detection signal by the photo coupler PC, resistors R ₆ to R ₈ and the transistor Tr
_{5 to} Tr _{7 is} a non-insulated signal transmission means.

Hereinafter, the operation of the present embodiment will be described. The signal V _A at time t ₀ becomes high level, the voltage V _C1 of the capacitor C ₁ is low, current I ₆ flowing through the current I ₇ and the transistor Tr ₆ flows through the transistor Tr ₇ becomes low. Therefore,
Since the voltage V ₈ of the resistor R ₈ has not reached a sufficient voltage to the transistor Tr ₅ is turned on, the transistor Tr ₅ is turned off, the collector potential of the transistor Tr ₅ is increased, NOT
Output V _G4 of circuit G ₄ are has a low level. Therefore, A
The output V _G1 of the ND circuit G ₁ becomes low level, the output V _G2 of the NAND circuit G ₂ becomes high level, and the input / output voltages V ₃ and V _{1 of the} drive circuit ₁
But low level, the output voltage V ₂ of the drive circuit 2 becomes the high level, the switching element Q ₁ is turned off, the switching element Q ₂ is turned on. Thus, the voltage V of the capacitor C _1
C1 rises quickly. The signal V _B becomes high level at time t _2, the the state does not change.

Then, the voltage V _C1 of the capacitor C ₁ is sufficiently increased at the time t _3, the current I _7, I ₆ flowing through the transistor Tr _7, Tr ₆ becomes large, the voltage V ₈ of the resistor R ₈ is a transistor Tr ₅ reached a sufficient voltage to turn on, the transistor Tr ₅ is turned on. For this reason, the lower the collector potential of the transistor Tr _5, NOT
The output V _G4 of circuit G ₄ becomes high level, the output V _G1, NAND circuit G ₂ of the output V _G2 each signal V _A of the AND circuit G _1, the same as V _B, the output of the AND circuit G ₁ V _G1 is low level, NAND circuit G ₂
Output V _G2 remains high. Signal V _B at time t ₄
If There goes low, the switching element Q ₂ is turned off, the load circuit Z voltage V across the action by the switching element Q ₂ of
_Q2 rises. When the signal V _A goes high at time t _5, AN
The output V _G1 of the D circuit G ₁ and the input / output voltages V ₃ and V _{1 of the} drive circuit ₁
There becomes a high level, the switching element Q ₁ is turned on. At this time, since the voltage V _C1 of the capacitor C ₁ is sufficiently high, the voltage V _Q1 across the switching element Q ₁
Becomes a sufficiently low on-state voltage.

Embodiment 4 FIG. 7 is a circuit diagram of a fourth embodiment of the present invention, and FIG. 8 is an operation waveform diagram thereof. In the present embodiment, in order to increase the voltage V _C1 of the capacitor C _1, without the charging of the capacitor C ₁ due to the turn-on of the switching element Q _2, it is performed by the other switching elements. For this,
At both ends of the switching element Q _2, connects the transistor Tr ₈ via a resistor R _9. The base of the transistor Tr _8, the voltage of the capacitor C ₃ in a time constant circuit consisting of resistor R ₆ and the capacitor C ₃ is detected by the voltage detection circuit G _6, NO
Voltage V _G7 inverted by T circuit G ₇ is applied through a resistor R _10. Output V _G6 of the voltage detection circuit G ₆ is connected to one input of the AND circuit G _1, G _5, to the other input of the AND circuit G _1, G _5, signal V _A of the oscillation circuit 3, V _B is input. Output V _G1, V _G5 of the AND circuit G _1, G ₅ are respectively a drive signal of the switching elements Q _1, Q _2.

Hereinafter, the operation of the present embodiment will be described. The signal V _A at time t ₀ becomes high level, when the voltage V _C3 of the capacitor C ₃ of the time constant circuit is low, the output V _G6 of the voltage detection circuit G ₆ becomes low level, the AND circuit G _1, G ₅ The outputs V _G1 and V _G5 are at a low level, and the switching elements Q ₁ and Q ₂ are both off. At this time, the output V _G7 of the NOT circuit G ₇ goes high, transistor Tr ₈ is turned on. Therefore, the resistance R ₁
The capacitor C ₁ is charged through R _9, the voltage V _C1 is gradually increased rapidly. The signal V _B becomes high level at time t _2, the the state does not change.

Then, the voltage V _C3 of the capacitor C ₃ at time t ₃ becomes higher than the threshold voltage Vth of the voltage detector circuit G _6, the output V ₆ of the voltage detection circuit G ₆ becomes high. As by this time the voltage V _C1 of the capacitor C ₁ can be increased sufficiently, previously selected time constant of the resistor R ₆ and a capacitor C ₃ to an appropriate value. When the output V _G6 of the voltage detection circuit G ₆ becomes high level, AND
The output V _G1 of the circuit G ₁ and the output V _G5 of the AND circuit G ₅ are each a signal V.
_A, becomes the same as V _B, become the switching elements Q _1, Q ₂ can operate, the switching element Q ₁ is turned off, the switching element Q ₂ is turned on. At the same time, the output V _G7 of the NOT circuit G ₇ is goes low, the transistor Tr ₈ is turned off. Until this time t _3, since the switching elements Q _1, Q ₂ is in the off state, the voltage across V _Q2 of the switching element Q _2, Q _2, V _Q1 the voltage V _C1 of the capacitor C ₁ from the DC power supply V the voltage obtained by subtracting, dividing voltage becomes in resistors R ₁ and R _9, 8
It changes as shown in FIGS. The switching element Q ₂ at time t ₄ is turned off, the voltage across V _Q2 goes high, the voltage across V _Q1 of the switching element Q ₁ is a low level. At this time, since the reverse current flowing through the switching element Q ₁ by the action of the load circuit Z, the voltage across V _Q1 of the switching element Q ₁ is a minus. Time t ₅ the signal V _A becomes high level, the output V _G1 of the AND circuit G _1, output voltage V _3, V ₁ of the drive circuit 1 becomes a high level, the switching element Q ₁ is turned on. At this time, since the voltage V _C1 of the capacitor C ₁ is sufficiently high, the voltage V _Q1 across the switching element Q ₁ is a sufficiently low on-voltage, and the power loss is reduced.

In addition, the capacitor C ₁ by the transistor Tr ₈ and the resistor R ₉
If a current mirror circuit 7 composed of transistors Tr ₈ and Tr ₉ is used as shown in FIG. 9 instead of the charging means, a constant current adjusted by the resistor R ₁₀ flows through the transistor Tr ₈ . it is possible, the role of the voltage distribution by resistors R ₉ can be borne to the transistor Tr _8. Further, the transistors Tr ₈ and Tr ₉ are not limited to bipolar transistors, but may be FETs or the like.

FIG. 10 shows a circuit example of the drive circuits 1 and 2. In the figure, between the power supply terminal Vcc and the ground terminal GND, and the capacitor C ₁ or
Supply voltage by C ₂ is supplied. In this drive circuit, a resistor R ₁₁ is connected between the power supply terminal Vcc and the ground terminal GND.
The series circuit of the transistor Q _3, the resistor R ₁₂ and transistor Q
_{4 and} a complementary operation type emitter follower circuit comprising transistors Q ₅ and Q ₆ are connected.
The collector output of the transistor Q ₃ which is connected to the base is connected to the base of the transistor Q _4, the transistor
Collector output Q ₄ are, by complementary operation type emitter follower consisting of transistors Q _5, Q ₆ is low impedance, and output to the output terminal B. When this drive circuit input terminal A is high, the transistor Q ₃ is turned on, the transistor Q ₄ is turned off, the transistor Q ₅ is turned on, the transistor Q ₆ is turned off, the output terminal B becomes high level When the input terminal A is at a low level, the output terminal B is at a low level.

FIG. 11 shows a circuit example of the oscillation circuit 3. This circuit comprises an astable multivibrator comprising a timer circuit 8 and a frequency dividing circuit comprising a T flip-flop FF. The timer circuit 8 is a general-purpose timer IC (NEC μPD1
5555). As is well known, this general-purpose timer IC is triggered when the trigger terminal (terminal 2) falls below (1/3) Vcc, the output terminal (terminal 3) becomes high level, and the discharge terminal (terminal 7) ) Has high impedance. Also, the threshold terminal (6th terminal) is (2/3) Vcc
, The output terminal (terminal No. 3) becomes low level, and the discharge terminal (terminal No. 7) also becomes low level. The power supply voltage Vcc is
Resistor R ₁₃ and a variable resistor VR and which is applied to the series circuit of the capacitor C _4, resistor R ₁₃ and a connection point of the variable resistor VR is connected to the discharge terminal (pin 7), the variable resistor VR and a capacitor C ₄
Is connected to the trigger terminal (terminal No. 2) and the threshold terminal (terminal No. 6). Thus, from the output terminal (pin 3), which oscillation output of the square wave is obtained, the oscillation frequency is resistor R ₁₃ and a variable resistor V
Determined by the time constant of the R and the capacitor C _4, the duty factor is determined by the ratio of resistors R ₁₃ and a variable resistor VR.
In the circuit of Figure 11, the resistance value of the variable resistor VR set considerably smaller than the resistance value of the resistor R _13, a period of high level is long, so that the oscillation output period of the low level is short is obtained .

The oscillation output of the astable multivibrator is frequency-divided by a frequency dividing circuit. The divider circuit is a T flip-flop
An FF is provided, and its output Q, is connected to one input of AND gates G ₁₁ , G ₁₂ , respectively. The oscillation output of the above-mentioned astable multivibrator is connected to the trigger input T. Each time the trigger input T rises from a low level to a high level, the output of the T flip-flop FF is inverted, and the output Q, from which the oscillation output of the astable multivibrator is divided by a factor of 50%, is 50%. Is obtained. On the other hand, the oscillation output of the astable multivibrator is connected to the other inputs of the AND gates G ₁₁ and G ₁₂ . The output of each AND gate G _11, G _12, respectively, the driving signal V _A of the switching element Q _1, Q _2, the V _B. Therefore, this drive signal is a signal that alternates between a first period in which one is at a high level and the other is at a low level and a second period in which one is at a low level and the other is at a high level. There is a third period between and the second period in which both outputs are both low. This third period is a dead-off time for preventing both the switching elements Q ₁ and Q _{2 from} being turned on, and may be a short time in consideration of the carrier accumulation time of the transistor in the on-state. Is determined by the period during which the oscillation output of the astable multivibrator is at a low level.

Further, as the switching elements Q ₁ and Q ₂ , for example, the first
2 A circuit in which a diode is connected in reverse parallel to a bipolar transistor as shown in FIG. 12A, a power MOSFET having a parasitic diode inside as shown in FIG. 12B, and the like can be used.

[Effects of the Invention] As described above in detail, in the present invention, a series circuit of the first and second switching elements is connected to a DC power supply,
In the inverter device in which the driving power supply voltage for the first switching element is charged when the second switching element is turned on, the first power supply voltage for the first switching element is maintained until the driving power supply voltage for the first switching element is sufficiently increased. Since the switching element is turned off and the second switching element is turned on, the driving power supply voltage of the first switching element quickly rises, and the switching operation of the first switching element is completely performed. In addition, there is an effect that a highly reliable inverter device with low power loss can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of the above embodiment, FIG. 3 is a circuit diagram of a second embodiment of the invention, FIG. FIG. 5 is a circuit diagram of a third embodiment of the present invention, FIG. 6 is an operation waveform diagram of the above embodiment, FIG. 7 is a circuit diagram of a fourth embodiment of the invention, FIG. FIG. 9 is a main part circuit diagram of a modification of the above embodiment, FIG. 10 is a specific circuit diagram of a drive circuit used in the first to fourth embodiments of the present invention,
FIG. 11 is a specific circuit diagram of an oscillation circuit used in the first to fourth embodiments of the present invention, and FIGS. 12A and 12B are specific circuit diagrams of the switching elements used in the first to fourth embodiments of the present invention. 13 is a circuit diagram of a conventional example, and FIG. 14 is an operation waveform diagram of the same. Q ₁ and Q ₂ are switching elements, V is a DC power supply, and C ₁ is a capacitor.

Claims (1)

(57) [Claims] An inverter device in which a series circuit of first and second switching elements is connected to a DC power supply, and a driving power supply voltage for the first switching element is charged when the second switching element is turned on. In the method, the first switching element is turned off and the second switching element is turned on until the driving power supply voltage of the first switching element reaches a predetermined voltage, and the driving power supply voltage is reduced to a predetermined voltage. An inverter device provided with a control circuit that, when reached, turns on a first switching element and turns off a second switching element.