JP2677368B2 - Inverter device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an inverter device in which a driving condition of a switching element is variable. (Background Art) FIG. 6 is a circuit diagram of a conventional inverter device. This circuit is a half-bridge type inverter circuit. The DC power supply E ₀ is composed of a DC voltage obtained by rectifying and smoothing a commercial AC power supply. A series circuit of switching elements Q ₁ and Q _{2 and} a series circuit of capacitors C ₃ and C ₄ are connected in parallel to this DC power source E ₀ . A load Z is connected between the connection point of the switching elements Q ₁ and Q _{2 and} the connection point of the capacitors C ₃ and C ₄ .
The switching elements Q ₁ and Q ₂ are on / off driven by drive circuits 1 and 2, respectively. The drive circuits 1 and 2 are supplied with power from drive power sources E ₁ and E ₂ , respectively. The capacitors C ₃ and C ₄ are charged by the DC power source E ₀ . Switching elements Q ₁ and Q ₂ are turned on alternately,
When Q ₁ is turned on, a current flows from the capacitor C ₃ to the load Z via the switching element Q _1, and when the switching element Q ₂ is turned on, from the capacitor C ₄ to the load Z via the switching element Q _2. Current flows in the opposite direction to the above. As a result, the load Z is AC-driven. By the way, in this circuit, in addition to the DC power supply E ₀ , a power supply E ₁ for supplying power to the drive circuit 1 and a power supply E ₂ for supplying power to the drive circuit 2 are required. In order to obtain the latter two power supplies E ₁ and E ₂ from the DC power supply E ₀ , a circuit as shown in FIG. 7 has been proposed. In the circuit of FIG. 7, in order to obtain the power supply E ₁ of the drive circuit 1, a series circuit of a resistor R ₁ and a capacitor C ₁ is connected to both ends of the switching element Q ₁ , and both ends of the capacitor C ₁ are connected. , Zener diode ZD ₁ for voltage regulation is connected in parallel. Moreover, in order to obtain the power supply E ₂ of the drive circuit 2,
A series circuit of a resistor R ₂ and a capacitor C ₂ is connected to both ends of a DC power source E ₀ , and a voltage regulating Zener diode ZD ₂ is connected in parallel to both ends of the capacitor C ₂ . First, in the power source E ₁ , the charging current flows to the capacitor C ₁ via the resistor R ₁ only when the switching element Q ₂ is turned on, and the charging current and the current consumed by the drive circuit 1, that is, the discharge amount The power supply voltage is determined. If this voltage is higher than the Zener voltage of the Zener diode ZD _1, the capacitor C through the Zener diode ZD _1
Since the electric charge of ₁ is discharged, the upper limit of the power supply voltage becomes equal to the Zener voltage of the Zener diode ZD ₁ . In the power source E ₂ , a charging current always flows through the capacitor C ₂ via the resistor R _2, and the power source voltage is determined by this charging current and the current consumed by the drive circuit 2, that is, the amount of discharge. If this voltage is higher than the Zener voltage of the Zener diode ZD ₂ is the charge of the capacitor C ₂ through the Zener diode ZD ₂ is discharged, the upper limit of the power supply voltage is equal to the Zener voltage of the Zener diode ZD ₂ Become. In the above-mentioned conventional example, when the drive frequency of the switching elements Q ₁ and Q ₂ is changed for the purpose of changing the state of the load Z, the current consumption of the drive circuits 1 and 2 changes. Therefore, under all conditions, in order to operate the drive circuits 1 and 2 normally, the power supplies E ₁ and E ₂ should be able to obtain sufficient voltage even when the current consumption of the drive circuits 1 and 2 is the largest. Need to be designed. Therefore, when the consumption current is not the maximum, the extra current is consumed by the Zener diodes ZD ₁ and ZD ₂ , and there is a problem that the power loss increases. In particular, when the frequency change is large, the loss due to the Zener diodes ZD ₁ and ZD ₂ becomes large. For example,
When the load Z is a discharge lamp load such as a fluorescent lamp and is an inductive load, the frequency is changed when the output of the inverter device is controlled to perform dimming. At this time, as shown in FIG. 8 (a), when the drive frequency of the switching element Q ₁ is low, the consumption current of the drive circuit 1, that is, the gate-source capacitance of the switching element Q ₁ composed of a MOSFET is reduced. The charging current is as shown in FIG. 8 (b). Further, as shown in FIG. 8 (c), when the driving frequency of the switching element Q ₁ is increased, the charging current becomes as shown in FIG. 8 (d). Figure 8 (a), as seen from (c), because the width of the on-off switching element Q ₁ is equal irrespective of the frequency, the charging current supplied to the capacitor C ₁ is equal regardless of the change in the frequency . Also, MOSF
Although the current consumption required to turn on the switching element Q ₁ made of ET is equal, the higher the frequency is, the more the number of times it is turned on increases, so the current consumption of the drive circuit 1 increases.
Therefore, the voltage of the power supply E ₁ becomes lower as the frequency becomes higher. If the voltage of the power supply E ₁ is set to be sufficiently high even in this high frequency state, in the low frequency state,
The voltage of the power supply E ₁ rises unnecessarily and the Zener diode ZD
The loss of ₁ becomes large. The power source E ₂ of the drive circuit 2 for the switching element Q ₂ has the same problem. (Object of the Invention) The present invention has been made in view of the above points, and an object thereof is to provide an inverter device capable of efficiently supplying a power source for driving a switching element. is there. DISCLOSURE OF THE INVENTION In the inverter device according to the present invention, in order to achieve the above object, as shown in FIG. 1 to FIG. 5, DC power supply E ₀ and DC power supply E ₀ a switching element Q ₁ for switching, the load Z is driven by the generated AC power by switching operation of the switching element Q ₁
A drive circuit 1 for driving the switching element Q ₁ on / off according to a control signal, and a drive power supply E for supplying power to the drive circuit 1 by the electric power supplied from the DC power supply E _0.
1 and a power feeding circuit that controls the power supplied from the DC power source E ₀ to the driving power source E ₁ according to the driving condition of the switching element Q ₁ . Therefore, in the present invention, the switching element Q ₁
ON / OFF frequency, ON / OFF duty, etc.
Even if the driving condition changes such that the load of the driving circuit 1 changes, the power supply to the driving power source E ₁ is controlled accordingly, so that the driving power source E ₁ may have insufficient power or excessive power. Therefore, it is possible to secure sufficient driving power without incurring power loss. Hereinafter, examples of the present invention will be described. Embodiment 1 FIG. 1 is a circuit diagram of a first embodiment of the present invention. The present embodiment is an example in which the present invention is applied to the power supply E ₁ of the switching element Q ₁ in the half-bridge type inverter circuit.
The configuration and operation of the main circuit of the inverter circuit are the same as those of the conventional example shown in FIG. 6, so redundant description will be omitted.
The configuration of the power supply unit will be described. The capacitor C ₁ is connected across the switching element Q ₁ via the collector and emitter of the transistor Q ₄ . Transistors Q _3, Q ₄ and transistors Q _5, Q ₆ are respectively connected to form a current mirror circuit. Each transistor Q ₃ ~
When the current amplification factor hfe of Q ₆ is made sufficiently high, substantially the same current as the current flowing through the transistor Q ₅ is a transistor Q ₆
, And this current also flows in the transistor Q ₃ , and almost the same current flows in the transistor Q ₄ . The diode D ₁ is provided to bypass the base-emitter reverse voltage of the transistor Q ₃ . FIG. 2 is an operation waveform diagram of the present embodiment. FIG.
(B) and (c) respectively show the control signal, the timer output, and the current consumption when the frequency of the control signal is low, and (d), (e) and (f) of the same figure show that the frequency of the control signal is high. The control signal, timer output, and current consumption in each case are shown. A control signal (not shown) is supplied with a rectangular-wave control signal as shown in FIG. 2A or 2D, and this control signal is input to the drive circuit 2 and the timer circuit 3 and , Is also input to the drive circuit 1 via the NOT circuit G ₁ . When the control signal is “High” level, the switching element Q ₂ is in the ON state and the switching element Q ₁ is in the OFF state. When the control signal is at the “Low” level, the switching element Q ₂ is in the OFF state and the switching element Q ₁ is It is on. The output of the timer circuit 3 is shown in FIG.
As shown in (e), the control signal goes to the "High" level for a certain period of time after it goes to the "High" level. When the output of the timer circuit 3 becomes "High" level, the transistor Q
_A current flows through the current mirror circuit composed of ₅ , Q ₆ , and the same current flows through the current mirror circuit composed of the transistors Q ₃ , Q ₄ to charge the capacitor C ₁ . The magnitude of this charging current can be set by the current flowing through the base of the transistor Q ₅ . The control signal is "H" during the time when the output of the timer circuit 3 is "High" level.
The charging operation is performed when the switching element Q ₁ is in the off state and the switching element Q ₂ is in the on state, which is shorter than the time at which the control signal is “high” level. At the "Low" level, the switching element Q ₁ is driven to the ON state by the driving circuit 1. If the switching element Q ₁ is composed of a power MOSFET, the current for charging the gate-source capacitance is flow, FIG. 2 (c) or current as shown in (f) is discharged from the capacitor C _1, is consumed. FIG. 2 (a) ~ (c) and FIG (d) ~ (f) As is clear from a comparison of, when the frequency of the control signal increases,
Although the current consumption of the drive circuit 1 increases, the power supplied to the drive circuit 1 also increases, so the drive power supply as a whole
The voltage of E ₁ hardly changes. Further, in the equilibrium state, the voltage of the driving power source E ₁ hardly changes even if the frequency changes, and therefore the Zener diode is not necessary. Embodiment 2 FIG. 3 is a circuit diagram of another embodiment of the present invention. The present embodiment is an example in which the present invention is applied to the driving power supplies E ₁ and E ₂ for the switching elements Q ₁ and Q ₂ in the serial inverter circuit. First, the main circuit of the inverter circuit will be described. The series circuit of switching elements Q ₁ and Q ₂ is connected to the DC power supply E ₀ , and a capacitor is connected across the switching element Q _2.
The load Z is connected via C ₀ . Switching element
Q _1, Q ₂ are alternately turned on by the drive circuit 1. The switching element Q ₁ is turned on, when the switching element Q ₂ is off, the switching element Q ₁ from the DC power source E _0, capacitor
A current flows through the load Z via C ₀ . At this time, the capacitor C ₀ is charged. Next, the switching element Q ₁ is turned off,
When the switching element Q ₂ is on, the capacitor C ₀ as the power source, current flows in the load Z through the switching element Q ₂ from the capacitor C _0. As a result, the load Z is AC-driven. Next, the configuration of the power supply unit will be described. Capacitor C ₁
Is connected to both ends of the switching element Q ₁ through the emitter and collector of the transistor Q ₈ . Transistor
Q ₇ is connected together with transistor Q ₈ to form a current mirror circuit. The series circuit of the capacitor C ₅ and the resistor R ₅ is connected to the switching element Q ₁ via the transistor Q _7.
Connected to both ends. The capacitor C ₂ is connected to both ends of the DC power source E ₀ via the collector and emitter of the transistor Q ₄ . Transistors Q _3, Q ₄ and transistors Q _5, Q ₆ are respectively connected to form a current mirror circuit. The diodes D ₁ and D ₂ are provided to bypass the base-emitter reverse voltage of the transistors Q ₃ and Q ₇ , respectively. The control signal is input to the drive circuit 1 and the timer circuit 3, and also to the drive circuit 2 via the NOT circuit G ₁ . The power supply E ₁ of the drive circuit 1 for the switching element Q ₁ is such that when the switching element Q ₂ is turned on, the capacitor C ₅ and the resistor R ₅
Charging current flows through transistor Q ₇ , and the same current flows through transistor Q ₈ to charge capacitor C ₁ . The discharge of the capacitor C ₅ is a switching element.
This is done through diode D ₂ when Q ₁ is turned on. Power E ₂ of the driving circuit 2 of the switching element Q ₂ is obtained by the operation similar to the operation shown in Example 1. in this way,
Drive circuit according to the drive frequency of switching elements Q ₁ and Q ₂
By changing the electric power supplied to the power sources E ₁ and E ₂ of the power sources ₁ and ₂ , it is possible to prevent the occurrence of power loss as in the conventional example. Embodiment 3 FIG. 4 is a circuit diagram of a third embodiment of the present invention. In the present embodiment, the present invention is applied to the power source E ₁ of the switching element Q ₁ in the one-stone separately excited inverter circuit. First, the main circuit of the inverter circuit will be described. The DC power source E ₀ is connected to the primary winding of the oscillation transformer OT via the switching element Q ₁ , and the resonance capacitor C ₀ is connected in parallel to the primary winding. A load Z is connected to the secondary winding of the oscillation transformer OT. When the switching element Q ₁ is driven on / off, the oscillation transformer OT
The current flowing in the primary winding of the oscillating transformer OT is intermittent, the oscillating current flows in the LC resonance circuit consisting of the inductance of the primary winding of the oscillation transformer OT and the capacitor C _0, and the sine wave AC voltage is generated. Load Z with this AC voltage
Is driven. Next, the configuration of the drive circuit 1 will be described. At both ends of the capacitor C ₁ for supplying power E ₁ of the drive circuit 1, the collectors of the NPN transistors Q ₉ and a PNP transistor Q ₁₀ is connected. The bases of the transistors Q ₉ and Q ₁₀ are connected to the oscillation output of the control circuit 4, and the emitters are connected to the gate of the switching element Q ₁ composed of a MOSFET via the resistor R ₄ . The control circuit 4 is supplied with power by the capacitor C ₁ and produces an oscillation output of a rectangular wave as shown in FIG. When the output of the control circuit 4 is in the "High" level, the transistor Q ₉ is turned on, the transistor Q ₁₀ is turned off, the gate-source capacitance of the switching element Q ₁ is, transistor Q ₉ from the capacitor C _1, resistors R ₄ Be charged through. When the control output of the circuit 4 is in the "Low" level, the transistor Q ₉ is turned off, a state of the transistor Q ₁₀ can be turned on. At this time, the charge of the gate-source capacitance of the switching element Q ₁ is discharged via the resistor R ₄ and the transistor Q ₁₀ . Next, the configuration of the power supply unit will be described. Capacitor C ₁
Is connected to the DC power supply E ₀ via the resistor R ₁ and the collector-emitter of the transistor Q ₄ . Transistors Q ₃ , Q ₄
And transistors Q _5, Q ₆ are connected to form a current mirror circuit. Each transistor Q ₃
When the current amplification factor hfe of the to Q ₆ is a sufficiently high, substantially the same current as the current flowing through the transistor Q ₅ is transistor
It flows into Q ₆ , this current also flows into transistor Q ₃ , and almost the same current flows into transistor Q ₄ . The oscillation output of the control circuit 4 is also input to the timer circuit 3. The oscillation output of the control circuit 4 input to the timer circuit 3 is applied to one end of the capacitor C ₆ via the buffer circuit G ₂ . The other end of the capacitor C ₆ is pulled up by the DC power supply E ₁ via the resistor R ₆ and the NOT circuit G ₃
Has been entered. The output of NOT circuit G ₃ is a transistor
It is input to the current mirror circuit consisting of Q ₅ and Q ₆ . When the output of the control circuit 4 becomes “High” level, one end of the capacitor C ₆ becomes “High” level via the buffer circuit G ₂ , and the other end pulled up by the resistor R ₆ becomes “High” level.
Level and the output of the NOT circuit G ₃ are the "Low" level. In this state, both ends of capacitor C ₆ are
gh "level, the charging voltage of the capacitor C ₆ becomes low. Next, when the output of the control circuit 4 becomes" Low "level, one end of the capacitor C ₆ becomes" Lo "via the buffer circuit G _2.
It becomes "level. At this time, since the charging voltage of the capacitor C ₆ lower, the other end of the capacitor C ₆ is also" w becomes Low "level,
The output of NOT circuit G ₃ is "Hig" as shown in Fig. 5 (b).
After that, the capacitor C ₆ is charged from the DC power source E ₁ through the resistor R ₆ , the potential at the other end of the capacitor C ₆ rises, and the output of the NOT circuit G ₃ becomes as shown in FIG. As shown in b), it returns to the “Low” level after the elapse of a certain time t _1. This constant time t ₁ is the time constant NOT of the resistor R ₆ and the capacitor C _6.
Determined by the threshold level of circuit G ₃ . As described above, in the present embodiment, after the switching element Q ₁ is turned off, the output of the timer circuit 3 becomes “High” level for a certain time t ₁ , and the current mirror circuit including the transistors Q ₅ and Q ₆ is provided. and current flows through the current mirror circuit consisting of transistors Q _3, Q _4, the capacitor C ₁ is charged. Therefore, even if the driving frequency of the switching element Q ₁ increases and the current consumption increases, the number of times of charging also increases, and the voltage of the power source E ₁ does not decrease. On the contrary, even if the driving frequency of the switching element Q ₁ is lowered and the current consumption is reduced, the number of times of charging is similarly reduced, so that the voltage E ₁ is not increased. Incidentally, in the above embodiments, the uses a current mirror circuit of the transistor Q ₃ to Q _6, since a high driving frequency of the switching element, the transistor Q ₃ to Q ₆ is operated in an unsaturated region, feeding This is to speed up the operation of the circuit. Instead of the transistor Q ₃ to Q _6, it may use other switching elements such as FET. (Advantages of the Invention) As described above, the present invention supplies the driving power of the switching element by the required amount according to the driving condition of the switching element. Therefore, the loss due to the change of the driving condition and the driving power are increased. The effect is that there will be no shortage of.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of the same, FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. Is a circuit diagram of a third embodiment of the present invention, FIG. 5 is an operation waveform diagram of the same as above, FIG. 6 is a circuit diagram of a conventional example, FIG. 7 is a circuit diagram of another conventional example, and FIG. It is an operation waveform diagram. 1, 2 are drive circuits, 3 are timer circuits, 4 are control circuits, and E ₀
Is a DC power supply, E ₁ and E ₂ are drive power supplies, Q ₁ and Q ₂ are switching elements, and Z is a load.

Claims (1)

(57) [Claims] A DC power supply, a switching element for switching the power of the DC power supply, a load driven by the AC power generated by the switching operation of the switching element, and a drive circuit for driving the switching element on / off according to a control signal. A driving power supply for supplying power to the driving circuit by the power supplied from the DC power supply, and a power supply circuit for controlling the power supplied from the DC power supply to the driving power supply according to the driving condition of the switching element. An inverter device characterized by comprising: