JP3226036B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an inverter device suitable as a power source for a dimmable discharge tube.

[0002]

2. Description of the Related Art For example, an inverter is used as a power supply for a cold cathode discharge tube (CFL). This type of inverter converts a DC voltage to an AC voltage of about 40 to 60 kHz to drive a discharge tube. The discharge tube is connected to a liquid crystal display (L
When used as a backlight of a CD), dimming is required. This dimming method is roughly classified into a method of adjusting the input voltage of the inverter and a method of adjusting the inverter by 200 to 300.
There is a method of intermittent driving at a repetition frequency of about HZ.

FIG. 1 shows a circuit for intermittently driving the latter inverter, and FIG. 2 shows a state of each part in FIG. The circuit in FIG. 1 is roughly divided into a rectifying and smoothing circuit 1 as a DC power supply, an inverter circuit 2, an inverter control circuit 3, a cold cathode discharge tube 4 as a load, a smoothing reactor 5, a current detecting circuit 6, Consisting of

The rectifying and smoothing circuit 1 has a pair of AC power supply terminals 7,
8 and converts the commercial AC voltage into a DC voltage, which is sent to a pair of DC power supply lines 9 and 10. In this embodiment, one DC power supply line 9 is a positive power supply line, and the other DC power supply line 10 is a negative or ground line.

The inverter circuit 2 is a self-excited push-pull type inverter, and includes first and second transistors Q1 and Q2 as a pair of conversion switches, and a transformer T.
And a resonance capacitor C1.

[0006] The transformer T has a primary winding N1, a secondary winding N2, and a tertiary winding N3 electromagnetically coupled to each other. The primary winding N1 has a center tap 11, and the first and second portions N
1a and N1b. The center tap 11 is connected to one DC power supply 9. One end of primary winding N1
The first transistor Q1 is connected between the (upper end) and the ground line 10, and the second transistor Q2 is connected between the other end (lower end) of the primary winding N1 and the ground line 10. In this embodiment, both the first and second transistors Q1 and Q2 are of the NPN type, and their respective emitters are connected to the ground line 10.

The tertiary winding N3 is for self-oscillation. One end (lower end) is connected to the base of the first transistor Q1, and the other end (upper end) is connected to the second transistor Q2. Connected to the base. The voltage of the tertiary winding N3 is used for base control of the first and second transistors Q1 and Q2. The downward voltage generated on the tertiary winding N3 forward biases the first transistor Q1, and the upward voltage generated on the tertiary winding N3 forward biases the second transistor Q2. The resonance capacitor C1 is connected in parallel with the primary winding N1. The resonance capacitor C1 forms a resonance circuit with the inductance of the primary winding N1 when the first and second transistors Q1 and Q2 are turned off, and allows an oscillating current to flow through the primary winding N1.

The switch control circuit 3 controls the driving period of the first and second transistors Q1 and Q2 of the inverter circuit 2, and includes the first and second control transistors Q11 and Q12, the starting resistor R1 and , Bias adjustment resistor R
2, R3 and a PWM control circuit 12.

The first control transistor Q11 is a PNP transistor, and its emitter has a current limiting resistor R
1 is connected to one of the DC power supply lines 9 and has a collector connected to a first transistor Q as a conversion switch.
1 is connected to a control terminal, i.e., the base and one end (lower end) of the tertiary winding N3.
And to the ground line 10 via the transistor Q12. A second control transistor Q12 comprising an NPN transistor is a control switch for turning on / off the first control transistor Q11, and has a collector connected to the base of the first control transistor Q11 via a resistor R3. The emitter is connected to the ground line 10, and the base (control terminal) is connected to the PWM control circuit 12.

The PWM control circuit 12 controls the first and second transistors Q1 and Q2 of the inverter circuit 2 at a low repetition frequency indicated by a driving period Ton and a non-driving period Toff in FIG. A PWM control signal Vpwm for intermittent control is generated and applied to the base of the second control transistor Q12. The PWM control circuit 12 includes a duty variable adjuster 13 for dimming the discharge tube 4. The variable adjuster 13 adjusts the ON period Ton of the PWM control signal Vpwm in a stepwise or continuous manner, and has a manual operation unit (not shown). The repetition frequency f2 of the PWM control signal Vpwm is about 200 to 300 Hz, and the output frequency f1 (40 to 6
0 kHz). Note that the PWM repetition frequency f2 is determined to be a value at which flicker does not cause a problem during the lighting period of the discharge tube 4.

The on-period Ton of the PWM control signal Vpwm
Is stably held, the output line of the current detection circuit 6 is connected to the PWM control circuit 12. The current detection circuit 6 includes a current detection resistor Ra, a rectifier diode Da, and a smoothing or integrating capacitor Ca. The discharge tube 4 is connected in parallel to a secondary winding N2 via a coupling capacitor C2. The current detection resistor Ra is connected in series to the discharge tube 4 as a load, and generates a voltage corresponding to the load current. PWM
The control circuit 12 controls the ON period Ton of the PWM control signal Vpwm so as to keep the current value detected by the current detection circuit 6 constant.

A reactor 5 connected in series to one DC power supply line 9 between the rectifying and smoothing circuit 1 and the inverter circuit 2 comprises a core and a coil.
Has the effect of reducing the ripple of the output and the effect of suppressing the noise generated by turning on and off the first and second transistors Q1 and Q2 from leaking to the power supply side.

In the apparatus shown in FIG. 1, when adjusting the brightness of the discharge tube 4, the duty variable adjuster 13 of the PWM control circuit 12 is operated. As a result, the PWM control signal Vpw
The ratio of the ON period Ton to the constant period T2 of m changes. The first and second control transistors Q11 and Q12 are P
It turns on in response to the on-period Ton of the WM control signal Vpwm. When the first control transistor Q11 is turned on, the base current of the first transistor Q1 flows through the path of one of the DC power supply line 9, the resistor R1, and the first control transistor Q11, and is turned on. First transistor Q1
Is turned on, one DC power supply line 9 and the primary winding N
A current flows through a circuit composed of the first part N1a, the first transistor Q1, and the other DC power supply line 10, and a voltage in the first direction is induced in the secondary winding N2 and the tertiary winding N3. The voltage of the tertiary winding N3 in the first direction is a downward voltage, and has a direction in which the first transistor Q1 is forward biased and the second transistor Q2 is reverse biased. And the off state of the second transistor Q2 is maintained. Transformer T
Since the primary winding N1 has an inductance, the collector current of the first transistor Q1 increases with time. If the collector current is increased by a value obtained by multiplying the base current Ib by the current amplification factor, the collector current cannot be increased any more, and the first transistor Q1 cannot be kept in the saturation ON state. The collector-emitter voltage of the first transistor Q1 increases, and conversely, the voltage applied to the primary winding N1 of the transformer T decreases. As a result, the base current supplied to the first transistor Q1 in the tertiary winding N3 decreases, and the first transistor Q1 is rapidly turned off. If the direction of the voltage applied to the primary winding N1 due to resonance after the first transistor Q1 is turned off is reversed, the first winding is applied to the tertiary winding N3.
A voltage in the second direction (upward) opposite to the above direction is generated, the second transistor Q2 is forward-biased, and the first transistor Q1 is reverse-biased. The base current of the second transistor Q2 is supplied to one of the DC power supply line 9 and the resistor R
1, a first control transistor Q11, a tertiary winding N3, a second transistor Q2, and the other DC power supply line 10. If the saturated on state of the second transistor Q2 cannot be maintained, it is turned off, and the first transistor Q1 is turned on instead. As a result, the first
The second transistor Q1 and the second transistor Q2 are alternately turned on and off at the cycle T1, and the AC voltage of the secondary winding N2 also changes at the cycle T1.

[0014]

By the way, a method of adjusting the input voltage of the inverter circuit at the time of dimming the discharge tube is adopted, and if the input voltage is lowered to lower the brightness, the lighting of the discharge tube becomes unstable. become. Further, in the method of intermittently controlling the inverter circuit 2 shown in FIG. 1 as shown in FIG.
As shown in FIG. 2, the drive period Ton from t1 to t2 to t2 to
At the time of switching to the non-driving period Toff at t4, a surge voltage is generated in the second control transistor Q12, the first and second transistors Q1, Q2 as shown in the section from t2 to t3, and these transistors Q12, The collector-emitter voltages Vq12, Vq1, Vq2 of Q1, Q2 are
The voltage is higher than the voltage between the 10 and the transistors Q1, Q2
, Q12 are required to have a high withstand voltage, which inevitably increases the cost. Also, electromagnetic wave noise is generated by the surge voltage, which adversely affects peripheral devices. For example, discharge tube 4
When is used as a backlight of a liquid crystal display device, it may cause flicker on the screen. The above problem also occurs when the inverter circuit 2 is configured as a circuit different from the circuit of FIG.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an inverter device which can achieve either one or both of lowering the breakdown voltage and reducing noise of the conversion switch of the inverter.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the above object, the present invention provides a DC power supply, a power supply connected to the DC power supply via a reactor, and turning on / off the voltage of the DC power supply. An inverter circuit having at least one conversion switch for converting the DC voltage of the DC power supply into an AC voltage, and intermittently connecting and disconnecting the inverter circuit having a repetition frequency lower than the AC output frequency of the inverter circuit. An inverter control circuit that controls a control terminal of the conversion switch so as to be driven in a controlled manner, and based on a release of the stored energy of the reactor in response to control by the inverter control circuit to switch the inverter circuit to a non-drive state. An inverter device including surge voltage suppression means connected in parallel to the reactor to suppress surge voltage; A is the reactor of the pair
Connected in series to one of the DC power supply lines,
The converter control circuit is connected to one end of the reactor and the conversion switch.
Control transistor connected between the
And the base of the control transistor and the other DC power supply
A control switch connected to the line and a switch
And a control circuit.
Connected to the one DC power supply line,
The collector of the transistor is the control terminal of the conversion switch.
And the switch control circuit is connected to the inverter
When the circuit is driven, the control switch is turned on.
When the inverter circuit is in the non-driving state,
The control switch is turned off.
The voltage suppressing means is provided between the base of the control transistor and the front of the control transistor.
The diode connected between the other end of the reactor
Those related to the inverter apparatus characterized by that. The surge voltage suppression means reduction or removal of the surge voltage.

[0017] Incidentally, as shown in claim 2, can be connected in parallel to control elements surge voltage suppression reactor as surge voltage suppressing means is controlled by a switching element for controlling the same. Also, the inverter circuit as shown in claim 3 and a self-excited inverter circuit, it is desirable to configure to be able to vary the ratio between the driving period and the non-driving period of the inverter circuit.

[0018]

According to the present invention, the energy remaining in the reactor is absorbed by the surge voltage suppressing means when the conversion switch of the inverter circuit is turned off.
A surge voltage generated based on the reactor can be reduced or eliminated, and no surge voltage is applied to the conversion switch when the conversion switch is turned off, so that a lower breakdown voltage and lower cost can be achieved. Claim 1
According to the invention, the portion between the emitter and the base of the control transistor is also used as a part of the surge voltage suppressing means, and the surge voltage based on the reactor can be easily and satisfactorily suppressed. According to the second aspect of the present invention, the switching of the inverter circuit from the driving state to the non-driving state based on the output of the switch control circuit and the formation of the reactor energy absorbing circuit by the surge voltage suppressing control element are simultaneously performed. Can be achieved. According to the third aspect of the present invention, adjustment of the output voltage or current of the inverter circuit can be easily achieved.

[0019]

[Embodiment and Examples] Next, with reference to Figures 3-7 illustrating the embodiments and examples of the present invention. However, FIG.
In FIG. 7 , portions common to FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

[0020]

First Embodiment An inverter device for a discharge tube 4 according to a first embodiment shown in FIG. 3 has a diode 20 as a surge voltage suppressing means added to the inverter device shown in FIG. It has the same configuration as the inverter device.

The diode 20 is connected between the base of the first control transistor Q11 and the other end (right end) of the reactor 5. Therefore, a surge voltage suppressing circuit, that is, a surge absorbing circuit comprising a series circuit of the resistor R1, the first control transistor Q11, and the diode 20 is connected in parallel with the reactor 5.

The basic operation of the inverter device shown in FIG.
Is the same as the inverter device. Therefore, the PWM control signal Vpwm of the circuit of FIG. 3, the collector-emitter voltage Vq11 of the first and second control transistors Q11 and Q12,
Vq12 and the collector-emitter voltages Vq1 and Vq2 of the first and second transistors Q1 and Q2 vary substantially as shown in FIG. 4 as shown in FIG. However, V in FIG.
As is clear from the comparison between q12, Vq1, Vq2 and Vq12, Vq1, Vq2 in FIG. 4, according to the first embodiment in FIG. 3, the surge voltage at the time of turning off the first transistor Q1 is largely suppressed. Then, at the turn-off time t2, the surge voltages of the voltages Vq12, Vq1, Vq2 of the transistors Q12, Q1, Q2 can be almost completely removed.

Next, the operation of suppressing the surge voltage will be described.
If the diode 20 of the present embodiment is not provided,
As described in FIG. 2, when the first transistor Q1 or the second transistor Q2 is turned off, the power supply line 9,
A surge voltage of about 30 to 40% of the DC power supply voltage between 10 is generated. On the other hand, in the circuit of this embodiment in FIG.
When the PWM control signal Vpwm changes from the drive period Ton to the non-drive period Toff, the second control transistor Q12 as a switch is turned off, the anode of the diode 20 is disconnected from the ground line 10, and this reverse bias state is released. Is done. For example, if the first transistor Q1 is in the ON state at the time t2 when the driving period Ton is switched to the non-driving period Toff, a current flows through the reactor 5 so that the first transistor Q1 is forcibly activated at the time t2. , The energy remains in the reactor 5. However, at time t2, since the diode 20 switches to the forward bias state, the reactor 5 and the resistor R
1. Between the emitter and base of the control transistor Q11,
A closed circuit composed of the diode 20 is formed, in which energy stored in the reactor 5 is released and absorbed there. During the energy release period of the reactor 5, the first
PN between the emitter and base of the control transistor Q11
The junction becomes forward-biased, through which the energy emission current flows. The forward voltage of the diode 20 is Vd,
The base-emitter voltage of the transistor Q11 is Vde
If the current flowing through the resistor R1 is Is, the voltage between both terminals of the reactor 5 is Vd + Vbe + IsR1, and the voltage between one end P1 of the reactor 5 and the ground line 10 is the voltage between the pair of DC power supply lines 9, 10. Assuming that Vin is Vin + Vd + Vbe + IsR1. The forward voltage Vd of the diode 20 is about 0.8
V, base-emitter voltage Vb of transistor Q11
Since e is about 0.6 V, and the value of the resistor R1 and the value of the current Is are not so large, the value of Vd + Vbe + IsR1 is not so large, and the release of the energy stored in the reactor 5 is completed within a very short time. Therefore, the surge voltage based on the reactor 5 is almost completely removed.

If the surge voltage based on the reactor 5 is suppressed, the voltages Vq1 and Vq2 of the first and second transistors Q1 and Q2 and the voltage Vq12 of the voltage Vq12 of the second control transistor Q12 do not become too large. This withstand voltage can be reduced, and the cost is reduced. Further, by suppressing the surge voltage, it is possible to reduce electromagnetic wave noise based on the surge voltage. In this embodiment, since the discharge tube 4 as a backlight of the liquid crystal display device is a load, flickering of the liquid crystal display screen due to noise based on the surge voltage can be prevented.

In the present embodiment, the surge voltage suppressing circuit is constituted by also using the first control transistor Q11 included in the control circuit 3 of the inverter circuit 2, so that the circuit structure can be simplified. Have been.

[0026]

Second Embodiment An inverter device according to a second embodiment shown in FIG. 5 is provided with an inverter circuit 2a which is a modification of the inverter circuit 2 shown in FIG. 3, and is otherwise substantially the same as FIG. It is. The inverter circuit 2a is for interrupting the DC voltage by one switching element, that is, the transistor Q1. The tertiary winding N3 is connected between the base and the emitter of the transistor Q1 via the control circuit 30. The control circuit 30 controls the base current of the transistor Q1 so that the output voltage (load voltage) detected by the voltage detection circuit 6a connected to the load circuit 4a becomes a predetermined value, and controls the drive period Ton and the non-drive state of the transistor Q1. Period T
off.

Since the circuit for suppressing a surge based on the reactor 5 of FIG. 5 is formed in the same manner as in FIG. 3, the same effect as that of the embodiment of FIG. 3 can be obtained by the embodiment of FIG.

[0028]

Third Embodiment An inverter device according to a third embodiment shown in FIG. 6 uses an NPN transistor 20 as a surge absorption control element instead of the diode 20 of the inverter device shown in FIG.
a, the collector of the transistor 20a is connected to one end of the reactor 5, the emitter is connected to the other end of the reactor 5, and the base is connected to the collector of the transistor Q3 via the resistor R3. Is connected to a resistor R4, and the other components are the same as those shown in FIG.

The transistor 20a in FIG. 6 has the functions of both the diode 20 and the transistor Q11 in FIG. That is, when the transistor Q12 is on, the base of the transistor 20a is connected to the ground line 10 via the transistor Q12,
Is kept off. When the transistor Q12 is turned off, the reverse bias between the base and the emitter of the transistor 20a is released, and the reactor 5, the resistor R4, and the transistor 20a are released based on the release of the stored energy of the reactor 5.
A current flows through a circuit consisting of a PN junction between the base and the emitter of the transistor, and a surge voltage is absorbed. Thus, the same effects as those of the first embodiment of FIG. 3 can be obtained by the third embodiment of FIG.

[0030]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) As a modification of the first and third embodiments, the first resistor R1 can be connected to the collector of the control transistor Q11 as shown in FIG. (2) As a modification of the first and third embodiments, it is possible to connect each of the collectors of the braking patronage transistor Q11 to the base of the first and second bets transistor Q1, Q2 via a resistor. (3) The inverter circuit 2 of Figure 3 can be modified in various inverter circuits other than FIG. (4) The transistors Q1, Q2 of the inverter circuits 2, 2a
A semiconductor switch such as an FET can be used instead of Q2. (5) A semiconductor switch such as an FET can be used instead of the transistor Q12 in FIG. 2 and the transistors Q11 and Q12 in FIG. (6) The rectifying and smoothing circuit 1 can be used as a battery power supply. (7) A diode can be connected in reverse parallel to the PN junction between the base and the emitter of the first and second transistors Q1 and Q2. (8) The transformer T is a saturable transformer, and the saturation allows the first and second transistors Q1 and Q2 to be switched on and off.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional discharge tube inverter device.

FIG. 2 is a waveform diagram showing a state of each unit in FIG.

FIG. 3 is a circuit diagram showing an inverter device for a discharge tube according to the first embodiment.

FIG. 4 is a waveform chart showing a state of each unit in FIG. 3;

FIG. 5 is a circuit diagram showing an inverter device according to a second embodiment.

FIG. 6 is a circuit diagram showing an inverter device according to a third embodiment.

FIG. 7 is a circuit diagram showing a part of an inverter device according to a modification.

[Explanation of symbols]

2 Inverter circuit 3 Inverter control circuit 4 Cold cathode discharge tube 5 Reactor Q1, Q2 Conversion transistor Q11, Q12 Control transistor 20 Surge voltage suppression diode

Claims (3)

(57) [Claims] 1. A DC power supply, comprising: a DC power supply; and at least one conversion switch connected to the DC power supply via a reactor for turning on and off a voltage of the DC power supply. An inverter circuit that converts the voltage into a voltage; and an inverter control circuit that controls a control terminal of the conversion switch so as to have a repetition frequency lower than an AC output frequency of the inverter circuit and drive the inverter circuit intermittently. A surge voltage suppressor connected in parallel with the reactor to suppress a surge voltage based on emission of stored energy of the reactor in response to control for converting the inverter circuit to a non-drive state by the inverter control circuit. An inverter device , wherein the reactor is connected in series to one of a pair of DC power supply lines.
Connected, the inverter control circuit is connected to one end of the reactor and the
A control switch connected to the control terminal of the conversion switch
A transistor, the base of the control transistor and the other
Control switch connected between the DC power line
And a switch control circuit, the emitter of the control transistor being connected to the one DC power supply.
Connected to the power supply line,
Is connected to the control terminal of the conversion switch, and the switch control circuit drives the inverter circuit.
The control switch is turned on when the
The control switch is used to set the barter circuit to the non-driving state.
Is turned off, and the surge voltage suppressing means is provided for the control transistor.
A die connected between the base and the other end of the reactor
An inverter device characterized by being an ode . 2. A DC power supply, wherein said DC power supply is connected via a reactor and said DC power supply
At least one of the following:
AC DC voltage of the DC power supply has a conversion switch
An inverter circuit for converting to a voltage, and a repetition rate lower than an AC output frequency of the inverter circuit.
Intermittently driving the inverter circuit with a frequency
Controlling the control terminal of the conversion switch as described above.
A data control circuit and the inverter circuit by the inverter control circuit.
Said reactor in response to control to convert to a non-driving state
Surge voltage based on the release of stored energy
Surge voltage suppression connected in parallel with the reactor
Means, wherein the reactor is connected in series to one of a pair of DC power supply lines.
Connected, the inverter control circuit is connected to one end of the reactor and the
The control switch connected between the conversion switch and the control terminal
And a switch control circuit, wherein the switch control circuit drives the inverter circuit.
The control switch is turned on when the
When the inverter circuit is set in the non-driving state, the control switch is used.
And the surge voltage suppressing means is connected in parallel with the reactor.
Connected by the switch control circuit.
The control switch is turned off during the on-control period, and the control switch is turned off.
An inverter device, which is a surge voltage suppression control element that is turned on or turned on during a switch off control period . 3. The inverter circuit according to claim 1, wherein the inverter circuit is a self-excited inverter.
A circuit, wherein the switch control circuit is configured to control an output current of the inverter circuit.
Or driving the inverter circuit to change the output voltage
Formed to change the ratio between the period and the non-driving period
3. The inverter device according to claim 1, wherein: