JPH0646726B2 - Timing extraction circuit - Google Patents

Description

The present invention relates to a timing extraction circuit for extracting timing from an equalized waveform in a communication line.

[Conventional technology]

The purpose of this type of timing extraction circuit is to provide a central point in the eye diagram for correct identification of equalized signal waveforms. Therefore, the timing component is extracted from the received code sequence itself. Especially when the code format is bipolar, full-wave rectification of the received signal results in a unipolar, resulting in bright line spectrum components. Therefore, as shown in FIG. 3, the conventional timing extraction circuit is composed of a full-wave rectification circuit for generating a timing clock and a clipper circuit for removing timing jitter. FIG. 4 shows the waveform of each part of the timing extraction circuit shown in FIG.

Referring to FIG. 3 and FIG. 4, the above-mentioned full-wave rectifier circuit is
Operational amplifiers 9 and 10, resistors 15, 16, 17, 1
8 and 19, and field effect transistors 12 and 13.

When the input signal e _i is positive, the diode-connected field effect transistor 12 is reverse biased and turned off (OF
F). When the field effect transistor 12 is turned off, the first operational amplifier 9, the input resistor 15 and the feedback resistor 1
6 forms an inverting feedback circuit. Resistance 1 in this case
If the value of 5 and the value of the resistor 16 are set equal, the gain is −
As a result, the output of the amplifier 9 becomes -e _i .

On the other hand, when the input signal e _i is positive, the diode-connected field effect transistor 13 is forward biased, and the second
The operational amplifier 10, the input resistance 17 and the feedback resistance 19 of
An inverting feedback circuit is configured, and the input signal of this inverting feedback circuit is –e _i . Here, when the value of the resistor 17 is set to 1/2 of the value of the resistor 19 and the value of the resistor 18 is set equal to the value of the resistor 19, the gains are added to be -1, and the output of the operational amplifier 10 is e _i . Become.

Next, when the input signal e _i is zero or negative, the field effect transistor 12 is forward biased and the operational amplifier 9
The input and output of are short-circuited and the output is always zero. On the other hand, since the field effect transistor 13 is reverse biased and turned off, the gain of the operational amplifier 10 is determined by the values of the resistors 18 and 19. As mentioned above, resistor 1
Since the values of 8 and the resistance 19 are set equal, the gain of the operational amplifier 10 becomes -1, and the inverted waveform e _i is output. Therefore, as shown in FIG. 4, when the input signal e _i is positive, e _i is output to the output E3 of the second operational amplifier 10. Similarly, when e _i is negative, the output E3 is also output. Since e _i is output, it becomes a full-wave rectified waveform.

Next, the clipper circuit has a resistor 20 and a reference voltage +
It is composed of a diode-connected transistor 14 supplied with V _ref and a buffer 11. Output E of the second operational amplifier 10
Since the case 3 of the voltage is equal to or higher than the reference voltage + V _ref is diode-connected transistor 14 is off (OFF), the output e _o of the voltage of the output E3 of the second operational amplifier 10 is a buffer 11
Appears in.

On the other hand, when the voltage of the output E3 of the second operational amplifier 10 is equal to or lower than the reference voltage + V _ref , the diode-connected transistor 1
4 is turned on (ON), and as a result, the input voltage of the buffer 11 becomes + V _ref , and this + V _ref is the output e _{o of the} buffer 11.
Appears in. In this way, the clipper outputs only the waveform of the reference voltage V _ref or higher.

Thus, the conventional timing extraction circuit shown in FIG. 3 generates the full-wave rectified waveform E3 of the input signal e _i as shown in FIG. 4, and then clips it at + V _ref to output the output e _o . It has gained.

[Problems to be solved by the invention]

However, since the conventional timing extraction circuit described above has a lot of resistance, there is a problem that the occupied area becomes large when implemented on a MOS LSI.

The threshold voltage of the field effect transistor depends on the manufacturing process such as the impurity implantation density. Therefore, the threshold voltage varies depending on the LSI sample, and the reference voltage V
_{Even if the ref} is constant, there is a problem in that the clip level differs for each LSI.

[Means for solving problems]

The present invention relates to an operational amplifier, one end of which is connected to a first input of the operational amplifier and the other end of which is connected to a first capacitance, and one end of which is connected to a second input of the operational amplifier, A second capacitor having the other end to which the input signal is input, a third capacitor having one end connected to the output of the operational amplifier and the other end connected to the first input of the operational amplifier, and the input A first comparator for comparing the signal with a first reference voltage; a second comparator for comparing the input signal with a second reference voltage;
The output of the first comparator is used as a control signal, one end of which is grounded and the other end of which is connected to the second input of the operational amplifier, and the output of the second comparator is controlled. A timing extraction circuit comprising an output and a second Aronag switch arranged in parallel with the third capacitor, wherein a tank circuit drive signal is obtained from the output of the operational amplifier.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of a timing extraction circuit according to the present invention. FIG. 2 is a diagram showing the waveforms of the input signal e _i , the switch control signals E1, and E2, and the output signal e _o .

Referring to FIGS. 1 and 2, 1 is an operational amplifier, 2 and 3 are comparators, 4 and 5 are analog switches, 6, 7 and 8 are capacitors, E1 and E2 are switch control signals, and + V.
_ref is a positive reference voltage, -V _ref is a negative reference voltage, e _i is an input signal, and e _o is an output signal.

The output state of the above timing extraction circuit is divided into the following three states depending on the level of the input signal e _i . (1) Input signal e
_i is less than positive reference voltage + V _ref and negative reference voltage −V
_In case of _ref or more, (2) In case of higher than positive reference voltage + V _ref ,
(3) This is the case where it is lower than the negative reference voltage −V _ref .

First, in the case of (1) −V _ref ≦ e _i ≦ + V _ref , the switch control signal E1 from the comparator 2 turns on the analog switch 5. Therefore, the non-inverting input of the operational amplifier 1 is grounded. On the other hand, the switch control signal E2 from the comparator 3
Turns the analog switch 4 on. Therefore, the operational amplifier 1 becomes full feedback. As a result, the output signal e _o of the operational amplifier 1 is always zero.

Next, in the case of (2) e _i > + V _ref , the comparator 2 determines that e _i > + V _ref
Then, the switch control signal E1 from the comparator 2 turns off the analog switch 5. On the other hand, the comparator 3 determines that e _i > −V _ref, and the switch control signal E2 from the comparator 3 turns on the analog switch 4. At this time, the input signal e _i has a positive reference voltage + V
_The charge is stored in a state equal to _ref . Therefore, the output signal e _o of the operational amplifier 1 which is a non-inverting circuit with a gain of 1 is e _i
-(+ V _ref ) value.

Finally, when (3) e _i <−V _ref , the switch control signal E1 from the comparator 2 turns on the analog switch 5 and the non-inverting input of the operational amplifier 1 is grounded. On the other hand, the switch control signal E2 of the comparator 3 turns off the analog switch 4, and as a result, the operational amplifier 1 has a configuration of an inverting feedback circuit. The phase of the output from the operational amplifier 1 is inverted and has a gain determined by the ratio of the capacitance 6 and the capacitance 8. At this time, charges are accumulated in the capacitor 6 in a state where the input signal e _i is equal to the negative reference voltage −V _ref . Therefore, the operational amplifier 1
The value of | e _i − (− V _ref ) | is added to the inverting input of. At this time, if the values of capacitance 6 and capacitance 8 are set equal,
The gain of the operational amplifier 1 becomes -1, and the absolute value of the voltage obtained by subtracting the negative reference voltage -V _ref from the input signal e _i appears in the output signal e _o .

Therefore, as shown in FIG. 2, when the input signal e _i is equal to or more than the positive reference voltage + V _ref , it is clipped by + V _ref and the output signal e _o is equal to or more than the positive reference voltage + V _ref of the input signal e _i . When a signal is obtained and the input signal e _i is less than or equal to the negative reference voltage −V _ref , it is clipped by | −V _ref |, and the output signal e _o includes the negative reference voltage −V _{ref of the} input signal e _i. The following signals will appear inverted.

〔The invention's effect〕

As described above, since the timing extraction circuit according to the present invention uses the capacitance, the analog switch, and the comparator, it is not directly affected by the threshold value of the field effect transistor as in the conventional case. Therefore, it has a higher accuracy than the conventional timing extraction circuit. Further, since the resistor is not used, there is an effect that the occupied area can be reduced as compared with the conventional timing extraction circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a timing extraction circuit according to the present invention, FIG. 2 is a diagram showing waveforms of respective parts of FIG. 1, FIG. 3 is a circuit diagram showing a conventional timing extraction circuit, and FIG. The figure is a diagram showing the waveform of each part in FIG. 1 ... Operational amplifier, 2, 3 ... Comparator, 4, 5 ... Analog switch, 6-8 ... Capacitance, 9, 10 ... Operational amplifier, 11 ...
Buffer amplifier, 12 to 14 ... Field effect transistor,
16 to 20 ... Resistors.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-38945 (JP, A) JP-A-59-181744 (JP, A) Practical use Sho-59-41635 (JP, U)

Claims (1)

[Claims] 1. An operational amplifier, one end of which is the first of the operational amplifiers.
A first capacitor connected to the input of the operational amplifier and inputting the input signal to the other end, and a second capacitor having one end connected to the second input of the operational amplifier and the other end receiving the input signal. A first comparison for comparing the input signal and a first reference voltage with a third capacitor having one end connected to the output of the operational amplifier and the other end connected to the first input of the operational amplifier Bowl,
A second comparator for comparing the input signal with a second reference voltage and the output of the first comparator are used as control signals, one end of which is grounded and the other end of which is the second input of the operational amplifier. A first analog switch connected to the second comparator, and a second analog switch connected in parallel to the third capacitor using the output of the second comparator as a control signal. A timing extraction circuit characterized in that a circuit drive signal is obtained.