JPH0645872A - High frequency circuit and high frequency semiconductor device - Google Patents

Abstract

PURPOSE:To provide a variable impedance element of less linearity degradation without requiring a DC current for the impedance change by short-circuiting sources of FETs whose drains and gates coupling capacitors are arranged between and controlling the impedance between drains by gate voltages of these FETs. CONSTITUTION:A coupling capacitor C1 is connected between a drain D1 and a gate G1 of a first FET1, and a coupling capacitor C2 is connected between a drain D2 and a gate G2 of a second FET2, and a source S1 of the FET1 and a source S2 of the FET2 are connected. A resistor R1 is connected between the gate G1 and an impedance connection terminal, and a resistor R2 is connected between the gate G2 and an impedance control terminal, and the impedance between drains D1 and D2 is changed by the DC voltage of the impedance control terminal in the condition of no DC potential difference between drains D1 and D2. Consequently, the DC current is unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable attenuator, an automatic gain controller, etc. used at high frequencies.

[0002]

2. Description of the Related Art Conventionally, there is a PIN diode as a variable impedance element used at a high frequency, but it has been necessary to change a DC current to change the impedance of the PIN diode. Further, as an element for changing impedance without requiring a DC current, there is an element for changing the impedance of the channel portion by the gate voltage of FET as used in Japanese Patent Application No. 3-206889 shown in FIG. It was

[0003]

However, there is a problem that power consumption increases in an element such as a PIN diode which requires a DC current to change impedance. On the other hand, in the element that changes the impedance of the channel portion by the gate voltage of the FET, the linearity is significantly deteriorated when the gate voltage is near the pinch-off voltage, and the intermodulation characteristics and the input / output characteristics are significantly deteriorated. there were.

The cause will be described from the DC characteristics with reference to FIG. 2 in the case of inputting a signal to the drain, grounding the source, and changing the channel impedance according to the gate voltage in the case of an N-channel depletion GaAs MESFET.

FIG. 2 shows a threshold value of −0.4 V and Wg of 200 μ.
3 is a DC characteristic diagram of the drain current Id when the source of the GaAs MESFET of m is grounded and the drain voltage Vd is changed with the gate voltage Vg as a parameter. In addition,
A gate resistor R3 of 2 kΩ was inserted in the gate so that a large current would not flow from the gate to the channel. From Figure 2, V
It can be seen that the linearity of the Vd-Id characteristics deteriorates near g = -0.4V and Vd = 0V. This is Vd> 0V
Shows that the channel is in the pinch-off state or a state close to the pinch-off, whereas when Vd <0V, the channel is opened, and this is the result of a large change in Id. The output characteristics deteriorate.

In view of the above problems, the present invention has an operating point (Vd
The Vd-Id characteristic in the vicinity of = 0 V) is improved, a DC current is not required for impedance change, and a variable impedance element with little deterioration in linearity is provided.

[0007]

As a means for improving the linearity of the Vd-Id characteristics near the operating point (Vd = 0V), there is a means using a complementary FET, for example, GaAsME.
When it is difficult to form a complementary FET such as an SFET in the same process, it is difficult to use this means.

If a complementary FET other than the variable impedance element is unnecessary, it is possible to reduce the number of process steps if it can be formed with a unipolar FET. Furthermore, by forming adjacent FETs having the same mask pattern, it is possible to form FETs having extremely similar characteristics to those of complementary FETs.

Therefore, V near the operating point (Vd = 0V)
As a means for improving the linearity of the d-Id characteristic, two FETs having the same polarity are provided, and the drain and the gate of the first FET are short-circuited at high frequency and opened in DC, and the second FET is formed.
The drain and the gate of the FET are short-circuited at high frequency and opened in DC, the source of the first FET and the source of the second FET are short-circuited at high frequency, and the gate of the first FET and the second FET are
Open the gate of the FET at high frequency, and apply the control voltage to the gate of the first FET and the gate of the second FET at the same time under the condition that no DC potential difference is generated between the drain of the first FET and the drain of the second FET. We propose a high-frequency circuit characterized by changing the impedance between the drain of the first FET and the drain of the second FET, and when the gate voltage of the junction FET or MESFET becomes higher than the potential barrier, the gate changes from the channel to the channel. As a specific example of a device through which a large current flows, two FETs of the same polarity, two coupling capacitors, and two resistors are provided, and the drain ( A first coupling capacitor (hereinafter, C1) is connected between the gate (hereinafter, G1) and a second FET (hereinafter, F).
ET2) drain (hereafter D2) and gate (hereafter G2)
Connect a second coupling capacitor (hereinafter C2) between
Source of T1 (hereinafter S1) and source of FET2 (hereinafter S)
2) is connected, and the first is connected between G1 and the impedance control terminal.
Resistor (hereinafter R1) is connected, a second resistor (hereinafter R2) is connected between G2 and the impedance control terminal, and D1 and D
A high-frequency semiconductor device shown in FIG. 1 is proposed, which is characterized in that the impedance between D1 and D2 is changed by the DC voltage of the impedance control terminal under the condition that no DC potential difference is generated in 2.

When D2 is grounded at a high frequency and used, C2 can be omitted because the isolation between S2 and G2 is usually large. Also MOSFET
In the element whose gate and channel are insulated as described above, either R1 or R2 can be omitted. Further, when a large current does not flow from the gate, it is possible to replace R1 and R2 with an inductor.

[0011]

In the case of the N-channel depletion FET, the operation of the present invention is performed by inputting a high frequency signal into D1, grounding D2, and connecting the DC voltage (hereinafter VAG) of the impedance control terminal.
The case where the impedance of the channel is changed by C) will be described from the DC characteristics.

C1 and C2 are respectively D1 and G1 and D
2 and G2 are selected to be short-circuited in terms of high frequency, and R
For 1, R2, select a size that opens G1 and G2 in terms of high frequency.

When a high frequency signal is applied to D1, G1
The potential of moves according to the potential of D1. On the other hand, G2 is grounded in terms of high frequency and its potential does not move like D2.

Therefore, when the voltage applied to D1 is positive, FET1 is biased so as to exhibit a diode characteristic,
FET2 is biased to exhibit a constant resistance characteristic. However, since FET1 and FET2 are connected in series, the potential of S1 is determined so that the currents flowing through the channels of FET1 and FET2 become equal. On the other hand, when the voltage applied to D1 is negative, FET1 is biased to exhibit a constant resistance characteristic, and FET2 is biased to exhibit a diode characteristic. However, since FET1 and FET2 are connected in series, the potential of S1 is determined so that the currents flowing through the channels of FET1 and FET2 become equal.

Therefore, the linearity of the current is not significantly deteriorated by the positive / negative of the signal voltage, which is generated in the element that changes the impedance of the channel portion by the gate voltage of the conventional FET.

FIG. 3 is a DC representation of this. FIG. 3 shows the voltage V of D1 when VAGC is used as a parameter.
It is a DC characteristic of the channel current ID when IN is changed, and V1 is set so that the voltage of G1 becomes VAGC + VIN.
A voltage source E1 generating a voltage equal to IN was inserted between G1 and R1 and D2 was grounded. FET1 and FET2 are GaAs-MESF with a threshold value of −0.4 V and Wg = 400 μm.
ET, and R1 and R2 are 2 kΩ. C1 is omitted by replacing its effect with E1, and C2 is omitted under the condition that D2 is grounded.

It can be seen from FIG. 3 that the linearity in the vicinity of the operating point of the channel current is greatly improved as compared with FIG.

[0018]

EXAMPLE An example of the present invention will be described with reference to FIGS. 4 to 7 in comparison with the characteristics of an element in which the impedance of a channel portion is changed by the gate voltage of a conventional FET. It should be noted that this embodiment is performed by a simulation by SPICE.

FIG. 4 is a circuit diagram of an automatic gain control device using the elements of this embodiment and the conventional example. FET1 and FET2 have N-channel Ga with a threshold value of −0.4 V and Wg = 400 μm.
AsMES-FET and FET3 have threshold values of -0.4V and Wg.
= 200 μm N-channel GaAs MES-FET,
C1 and C2 are 5 pF, R1, R2 and R3 are 2 kΩ, FE
TA is a threshold value of −0.4 V, Wg = 400 μm N-channel GaAs MES-FET, CPASS is 100 pF,
RB1 and RB2 are 2kΩ, RG is 2kΩ, and CIN is 10
0 pF, L is 1 μH, CGND is 100 pF, RIN is the characteristic impedance of the signal source VIN, 50Ω, and the power supply voltage is 5V. Here, in addition to the function described in (Operation), R1 and R2 also have a function of suppressing the inflow / outflow of the DC current in the gain control power supply and suppressing the DC bias fluctuation of the variable impedance element, similarly to R3. ing.

FIG. 5 is a gain control characteristic diagram showing an open circuit voltage gain at the monitor terminal with respect to VAGC at a signal frequency of 1400 MHz and an input power of -20 dBm. The solid line shows the present embodiment and the broken line shows the conventional example. From FIG. 5, in this embodiment, when VAGC is larger than the DC bias voltage by the threshold voltage, that is, when the gain is 2.1V, the maximum gain is obtained, and there is almost no change, whereas in the conventional example, the gain is gradually increased to 2.1V or less. You can see that the gain is increasing. This is because in the conventional example, even if VAGC becomes 2.1 V or less, the channel opens due to the instantaneous voltage of the monitor terminal, and pinch-off does not occur unless a lower VAGC voltage is applied, but in the present example, this phenomenon occurs. Drastically improved to 2.1
It indicates that pinch-off is performed at V or less.

FIG. 6 shows a signal frequency of 1350 MHz and 1
It is a 3rd-order intermodulation distortion suppression characteristic figure showing the 3rd-order intermodulation distortion suppression amount with respect to VAGC in 400 MHz and input power -20 dBm. Here, 1400 MH can be placed on the monitor terminal
The ratio of the output voltage of 1450 MHz to the output power of z is shown. The solid line shows the present embodiment and the broken line shows the conventional example. It can be seen from FIG. 6 that the linearity of the variable impedance element is improved and the third-order intermodulation distortion suppression characteristic is improved.

FIG. 7 shows a signal frequency of 1400 MHz, VA
FIG. 4 is an input / output characteristic diagram showing input power vs. output power at GC = 2.1 V, where the solid line is the present embodiment and the broken line is the conventional example. It can be seen from FIG. 7 that the linearity of the variable impedance element is improved and the dynamic range of the automatic gain control device is expanded.

Although the above description does not describe the parasitic capacitance and the like that pose a problem in high frequency characteristics, the gist of the present invention is to improve the linearity at the operating point, and the influence of the parasitic capacitance and the like is This is different from the gist of the present invention. Although the terms FET, drain, source, and gate are used for convenience of description, a channel and an element having a structure for controlling it are consistent with the gist of the present invention. It is not excluded from the scope of the invention. Further, FETs having threshold values, gate widths, and gate lengths other than those of the present embodiment, or a combination thereof are not excluded from the scope of the present invention.

Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 10 in comparison with the characteristics of an element in which the impedance of a channel portion is changed by the gate voltage of a conventional FET. In the second example, a circuit was formed by combining discrete components, and measurement and evaluation were performed.

FIG. 8A is a circuit diagram of the attenuator of the second embodiment in which the variable impedance element of the present invention and the conventional variable impedance element are arranged in a π type. The variable impedance element of the present invention is a through element. Used as. FE
T11 and FET12 have a threshold value of −1.0 V, Wg = 800 μ
m N-channel GaAs MES-FET, FET1
3, the FET 14 is an N-channel GaAs MES-FET with a threshold value of -1.0 V and Wg = 400 μm, C11 and C12.
Is 100 pF and R11, R12, R13 and R14 are 3.
It is 3 kΩ. FIG. 8B is a circuit diagram of a conventional attenuator in which only conventional variable impedance elements are arranged in a π type, and FET15, FET16, and FET17 are threshold values −1.
0V, Wg = 400μm N-channel GaAs MES
-FET, R15, R16, and R17 are 3.3 kΩ. A signal is input from each of the input terminals (IN1, IN2) and a signal is output from each of the output terminals (OUT1, OUT2), but the impedance control terminal voltage (V
1, V3) and the impedance control terminal voltage (V2, V4) of the shunt element are combined and changed,
Impedance matching can be achieved.

FIG. 9 shows the attenuation amount and VSWR (voltage standing wave ratio) in the attenuator of the second embodiment shown in FIG. 8A and the attenuator of the conventional example shown in FIG. 8B. ) Is shown. The solid line is the second embodiment and the broken line is the conventional example. The characteristic impedance of the measurement system is 50Ω and the measurement frequency is 1900 MHz.
Is. It can be seen from FIG. 9 that good impedance matching of VSWR2 or less can be obtained over a range of attenuation of 15 dB or more.

FIG. 10 shows the attenuation amount and the third-order intermodulation distortion output in the attenuator of the second embodiment and the attenuator of the conventional example. The solid line is the second embodiment and the broken line is the conventional example. Input power is -15 dBm, frequency is 1900 MHz and 190
It was performed with a 2-wave input of 0.3 MHz. From this figure, it is understood that the third-order intermodulation distortion characteristic is improved over the entire attenuation range by using the variable impedance element of this embodiment.

Although the variable impedance element of the present invention is used only for the through element in the second embodiment, the linearity is improved even if it is used for both the through element and the shunt element, or only for the shunt element. What is done is obvious.

[0029]

As described in detail above, according to the present invention, it is possible to realize a variable impedance element that does not require a DC current for impedance change and has a small deterioration of linearity, and to obtain the intermodulation characteristics of a gain control device. It has the effect of improving the dynamic range. Further, since it can be manufactured by a unipolar process, the number of process steps can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a variable impedance element used in an example.

FIG. 2 is a DC measurement circuit diagram of a conventional example and a Vd-Id characteristic diagram.

FIG. 3 is a measurement circuit diagram for showing the DC characteristic of the variable impedance element used in the embodiment, and a VIN-Id characteristic diagram.

FIG. 4 is a circuit diagram of an automatic gain control device used in the embodiment,
Circuit diagram of a conventional automatic gain control device

FIG. 5 is a gain control characteristic diagram showing a gain control characteristic of the automatic gain control apparatus used in the embodiment and a gain control characteristic of a conventional automatic gain control apparatus.

FIG. 6 is a third-order intermodulation distortion suppression amount characteristic diagram showing the third-order intermodulation distortion suppression amount of the automatic gain control device used in the embodiment and the third-order intermodulation distortion suppression amount of the conventional automatic gain control device.

FIG. 7 is an input / output characteristic diagram showing the input / output characteristics of the automatic gain control device used in the embodiment and the input / output characteristics of the conventional automatic gain control device.

FIG. 8 is a circuit diagram of a π-type attenuator using a variable impedance element according to the present invention used in the second embodiment and a conventional π-type attenuator.
Type attenuator schematic

FIG. 9 is an attenuation-VSWR characteristic diagram of a π-type attenuator using a variable impedance element according to the present invention and a conventional π-type attenuator used in the second embodiment.

FIG. 10 is a diagram showing an attenuation amount-third-order intermodulation distortion characteristic diagram of a π-type attenuator using a variable impedance element according to the present invention and a conventional π-type attenuator used in the second embodiment.

[Explanation of symbols]

FETA Wg 400 μm, threshold-0.4 V GaAs
MESFET FET1 Wg 400 μm, threshold-0.4 V GaAs
MESFET FET2 Wg 400 μm, threshold-0.4 V GaAs
MESFET FET3 Wg 200 μm, threshold-0.4 V GaAs
MESFET L 1 μH coil C1 5 pF capacitor C2 5 pF capacitor CIN 100 pF capacitor CPASS 100 pF capacitor CGND 100 pF capacitor R1 2 kΩ resistance R2 2 kΩ resistance R3 2 kΩ resistance RG 2 kΩ resistance RB2 2 kΩ resistance RB2 IN k Characteristic impedance of signal source 50 Ω VIN Signal source VAGC Impedance control voltage source FET11 Wg 800 μm, threshold-1.0 V GaA
sMESFET FET12 Wg 800 μm, threshold-1.0 V GaA
sMESFET FET13 Wg 400 μm, threshold-1.0 V GaA
sMESFET FET14 Wg 400 μm, threshold-1.0 V GaA
sMESFET C11 100 pF capacitor C12 100 pF capacitor R11 3.3 kΩ resistance R12 3.3 kΩ resistance R13 3.3 kΩ resistance IN1 signal input terminal OUT1 signal output terminal V1 through element impedance control terminal voltage V2 shunt element impedance control terminal Voltage FET15 Wg 400 μm, threshold-1.0 V GaA
sMESFET FET16 Wg 400 μm, threshold-1.0 V GaA
sMESFET FET17 Wg 400 μm, threshold-1.0 V GaA
sMESFET R14 3.3 kΩ resistance R15 3.3 kΩ resistance R16 3.3 kΩ resistance IN2 Signal input terminal OUT2 Signal output terminal V3 Through element impedance control terminal voltage V4 Shunt element impedance control terminal voltage

Claims (2)

[Claims] 1. A first F comprising two FETs of the same polarity.
The drain and gate of the ET are short-circuited at high frequency and opened in DC, the drain and gate of the second FET are short-circuited at high frequency and opened in DC, and the source of the first FET and second
The source of the FET is short-circuited at high frequency, the gate of the first FET and the gate of the second FET are opened at high frequency, and the drain of the first FET and the drain of the second FET are DC.
The impedance between the drain of the first FET and the drain of the second FET is changed by applying a control voltage to the gate of the first FET and the gate of the second FET at the same time under the condition that no potential difference is generated. High frequency circuit to do. 2. A FET having two same polarity, two coupling capacitors and two resistors, the first coupling capacitor being connected between the drain and gate of the first FET, A second coupling capacitor between the drain and the gate of the FET, a source of the first FET and a source of the second FET, and a first resistor between the gate of the first FET and the impedance control terminal. And a second resistor connected between the gate of the second FET and the impedance control terminal,
Characterized in that the impedance between the drain of the first FET and the drain of the second FET is changed by the DC voltage of the impedance control terminal under the condition that a DC potential difference does not occur between the drain of the second FET and the drain of the second FET. High frequency semiconductor device.