WO2024100830A1

WO2024100830A1 - Power amplifier

Info

Publication number: WO2024100830A1
Application number: PCT/JP2022/041857
Authority: WO
Inventors: 和也山本; 美代宮下; 勝也嘉藤
Original assignee: 三菱電機株式会社
Priority date: 2022-11-10
Filing date: 2022-11-10
Publication date: 2024-05-16
Also published as: JP7384318B1

Abstract

This power amplifier comprises: a stack-type circuit (19) which has n FETs (n is an integer value of 2 or greater), wherein, when the number of FETs is from 1 to n and i is an integer from 2 to (n-1), a gate terminal of the first FET (12) receives an input of an input signal, a drain terminal is connected to a source terminal of the second FET, and a source terminal is connected to GND, a drain terminal of the i-th FET is connected to a source terminal of the (i+1)-th FET, and an out signal is output from a drain terminal, which is connected to power, of the n-th FET(18); resistors which are respectively connected to gate terminals of the second to n-th FETs of the stack-type circuit (19); capacitors which are respectively connected to electrodes, which are in a side opposite to the gate terminals, of the resistors; and first switches which are respectively connected to the resistors in parallel.

Description

Power Amplifiers

This disclosure relates to a stacked power amplifier.

Currently, power amplifiers for mobile devices mainly use GaAs HBTs (Heterojunction Bipolar Transistors). The reasons for this include the fact that they can operate from a single power supply in a normally-off mode, can operate from a 3.7V Li-ion battery voltage, and have a higher power density than GaAs FETs (Field Effect Transistors) in the output power range up to a few watts, so the chip area is smaller when made into an integrated circuit, and they can achieve a very high yield compared to GaAs-based FETs.

However, in recent years, power amplifiers, band changeover switches, and antenna switches have been equipped with CMOS (Complementary Metal-Oxide-Semiconductor) control circuits that enable digital control in addition to the GaAs HBTs in order to simplify control within the terminal. Furthermore, GaAs HBT chips, which are not Si-based, cannot be integrated with control circuits, and are more expensive to mass-produce than CMOS chips, so there has been a strong demand for CMOS power amplifiers.

The standard voltage of a CMOS FET is 1.2 V for a 65 nm process and 1.8 V for a 0.18 μm process, which is significantly lower than the battery voltage (3.7 V), so a power amplifier composed of a single stage CMOS FET cannot be used.

Against this background, stacked power amplifiers, which are effective in operating CMOS as a power amplifier at as high a power supply voltage as possible, are attracting attention (see, for example, Non-Patent Document 1).

Next, the issues will be explained using as an example a four-stage stacked power amplifier using a 65 nm CMOS process with a standard FET voltage of 1.2 V. In this example, assuming that each amplifying FET operates evenly, it can operate with a power supply voltage of up to 4.8 V. The standard voltage of a Li-ion battery is 3.7 V, but for high output power operation, it is boosted to 4.8 V by a DC-DC converter, and it is assumed to operate with an output power of 1 W.

In mobile communications, the output power of a terminal is often reduced depending on the distance between the base station and the terminal. In other words, if the distance is long, the output power is often switched to maximum, and if the distance is short, the output power is switched to low. For example, in urban areas, the distance between the base station and the terminal is relatively short, so the output power of the terminal is often low, around a few to a few tens of mW. This output power control is achieved by lowering the power supply voltage of the power amplifier. This is because if the output power is lowered by only reducing the input power while keeping the power supply voltage high, the efficiency of the power amplifier drops significantly.

However, if the power supply voltage of a stacked power amplifier is reduced from 4.8V to, for example, 2.4V, the load line of the FETs remains the same and only the power supply voltage drops, so the load line of the FETs in each stage will be significantly different from the optimal state, resulting in not only a drop in output power but also a significant drop in efficiency.

This disclosure has been made to solve the above problems, and aims to provide a power amplifier that can suppress a decrease in efficiency even when the power supply voltage is lowered.

The power amplifier disclosed herein is a stacked circuit having n (n is an integer of 2 or more) FETs, where the FETs are numbered 1 to n and i is an integer between 2 and (n-1), the first FET has a gate terminal to which an input signal is input, a drain terminal connected to the source terminal of the second FET, and a source terminal connected to GND, the i-th FET has a drain terminal connected to the source terminal of the (i+1)-th FET, and the n-th FET has a drain terminal from which an output signal is output, and a drain terminal connected to a power source; resistors connected to the gate terminals of the second to n-th FETs of the stacked circuit, respectively; capacitors connected to the electrodes of the resistors on the opposite side to the gate terminals; and first switches connected in parallel to the resistors.

This disclosure makes it possible to obtain a power amplifier that suppresses a decrease in efficiency even when the power supply voltage drops.

1 is a diagram illustrating a circuit configuration of a power amplifier according to a first embodiment; 4 is a diagram showing a load line of a FET of the power amplifier according to the first embodiment; 4 is a diagram showing a load line of a FET of the power amplifier according to the first embodiment; FIG. 11 is a diagram illustrating a circuit configuration of a power amplifier according to a second embodiment. FIG. 13 is a diagram illustrating a circuit configuration of a power amplifier according to a third embodiment.

Embodiment 1.
1 shows a circuit configuration of a power amplifier 10 according to a first embodiment. Assume that a 65 nm CMOS process is used to manufacture the power amplifier 10, and the maximum standard voltage of the FET is 1.2 V. Here, the maximum standard voltage refers to the maximum DC voltage that can be applied between the drain and source terminals of a FET having the finest gate length used in the CMOS process and that ensures long-term reliability of the FET.

FET 12 has a gate terminal to which an input signal is input from input terminal 22, and a drain terminal connected to the source terminal of FET 14, which is connected to GND. FET 14 has a drain terminal connected to the source terminal of FET 16. FET 16 has a drain terminal connected to the source terminal of FET 18. FET 18 outputs an output signal from its drain terminal, which is connected to a power supply (Vdd). A circuit consisting of these four FETs is called a stacked circuit 19. FET 12, FET 14, FET 16, and FET 18 are n-type FETs. Although not shown, an input matching circuit is connected to input terminal 22. An output matching circuit 20 is connected between output terminal 24 and the drain terminal of the third FET 18.

Bias terminal 50, bias terminal 52, bias terminal 54 are gate bias terminals of FET 14, FET 16, FET 18, respectively, and are connected to the gate terminals of FET 14, FET 16, FET 18 via

resistors

38, 40, 42 of about kΩ.

FET switches

32, 34, 36 are connected in parallel with

resistors

38, 40, 42, respectively. These FET switches function as switches that bypass the resistors.

FET switch

32, 34, 36 are turned on/off by

switch terminal

56, 58, 60, respectively.

Bias terminal 50, bias terminal 52, bias terminal 54 are terminals opposite the gate terminals of

resistors

38, 40, and 42, and

capacitors

44, 46, and 48 are connected between them and GND, respectively.

Capacitors

44, 46, and 48 are variable capacitors.

The number of FETs in a stacked circuit is not limited to four. Here, the number of FETs in a stacked circuit is assumed to be n (n is a number equal to or greater than 2). The FETs are numbered from 1 to n, and i is an integer equal to or greater than 2 and equal to or less than (n-1). The first FET corresponds to FET 12 in FIG. 1, and has a gate terminal to which an input signal is input, a drain terminal connected to the source terminal of the second FET, and a source terminal connected to GND. The i-th FET corresponds to FET 14 and FET 16 in FIG. 1, and has a drain terminal connected to the source terminal of the (i+1)-th FET. The n-th FET corresponds to FET 18 in FIG. 1, and has a drain terminal to which an output signal is output, and a drain terminal connected to a power supply (Vdd).

Let's go back to the case where the stacked circuit has four FETs and continue the explanation. Since the maximum standard voltage of a FET is 1.2V, the power supply voltage of the power amplifier 10 can be raised to 4.8V DC. The well of each FET is separated, and the backgate is connected to the source. If the FET is a fully depleted SOI (Silicon On Insulator) type, the backgate may be floating. Since the control FETs such as FET switch 32, FET switch 34, and FET switch 36 also need to withstand a maximum voltage of 4.8V, high-voltage FETs with a thick gate oxide film are used for the control FETs.

When the power supply voltage is the maximum 4.8V and there is no voltage drop, a voltage of 4.8V is applied to the drain terminal of FET 18. If there is a voltage drop, the applied voltage will decrease by that amount, but here we will explain it as if there is no voltage drop. When the power supply voltage is 4.8V, FET switch 32, FET switch 34, and FET switch 36 are all closed, bypassing

resistors

38, 40, and 42. In this way, a voltage of 1.2V is applied between the drain-source terminals of FET 12, FET 14, FET 16, and FET 18, and all of these FETs perform an amplifying operation.

Next, consider the case where the power supply voltage is lowered to 3.6V. In this case, FET switch 32 and FET switch 34 are closed, and FET switch 36 is open. Resistor 42 is therefore enabled, and FET 18 operates in switch mode. Switch mode here refers to an operating state in which the gate terminal of the FET is floated by the resistor, and the input to the source terminal is output from the drain terminal with almost no loss. The

remaining FETs

12, 14, and 16 perform amplification. This keeps the voltage drop between the drain and source terminals of FET 18 to a minimum, and a voltage of approximately 1.2V is applied between the drain and source terminals of

FETs

12, 14, and 16 performing amplification, achieving an optimal state for power amplification. In other words, the FETs operate in the saturation region so that the voltage amplitude and current amplitude during amplification can be made sufficiently large.

Next, consider the case where the power supply voltage is lowered to 2.4V. In this case, FET switch 32 is closed, and FET switch 34 and FET switch 36 are open. Therefore,

resistors

40 and 42 at the gate terminals of FET 16 and FET 18 are active, and FET 16 and FET 18 operate in switch mode. The

remaining FETs

12 and 14 perform an amplifying operation. In this way, the voltage drop between the drain and source terminals of FET 16 and FET 18 is kept to a minimum, and a voltage of approximately 1.2V is applied between the drain and source terminals of FET 12 and FET 14, which perform the amplifying operation, allowing sufficient amplifying operation.

Next, consider the case where the power supply voltage is lowered to 1.2V. In this case, FET switch 32, FET switch 34, and FET switch 36 are all open. Therefore,

resistors

38, 40, and 42 at the gate terminals of FET 14, FET 16, and FET 18 become active, and FET 14, FET 16, and FET 18 operate in switch mode. The remaining FET 12 performs an amplifying operation. In this way, the voltage drop between the drain and source terminals of FET 14, FET 16, and FET 18 is kept to a minimum, and a voltage of approximately 1.2V is applied between the drain and source terminals of FET 12, which performs the amplifying operation, allowing sufficient amplifying operation.

When the power supply voltage is lowered, the order in which the FET switches are opened does not have to start from the upper FET switch 36 as described above.

Let us generalize the explanation so far. Let the number of FETs in the stacked circuit be n (n is an integer equal to or greater than 2), and let the FETs be numbered as described above. Let the maximum standard voltage of all of these FETs be Vm, let the voltage applied to the drain terminal of the nth FET be Vd, and let j be an integer equal to or greater than 1 and equal to or less than n. If (j-1) x Vm < Vdd ≤ j x Vm, then (j-1) of the FET switches will be closed and the rest will be open.

Even if the power supply voltage is reduced in this way, by appropriately opening FET switch 32, FET switch 34, and FET switch 36 according to the level of the reduction in the power supply voltage, it is possible to apply a voltage sufficient for the FET to operate in the saturation region between the drain and source terminals of the FET performing the amplifying operation.

The capacitance values of the capacitors may be set so that the load lines of FET12, FET14, FET16, and FET18 are equal. Figure 2 shows a schematic of the load lines when all FETs are performing amplification. To equalize the load lines of each FET, if the input impedance of FET14, FET16, and FET18 is Zi (i = 1, 2, 3) and the optimal load resistance of one FET is Ropt, then Z1 = Ropt, Z2 = 2 x Ropt, and Z3 = 3 x Ropt should be set. 4 x Ropt should be set to be equal to the load impedance seen from the drain terminal of FET18. For example, if the impedance of the output matching circuit 20 is 50 Ω, Ropt is 12.5 Ω. This will equalize the load lines of FET12, FET14, FET16, and FET18.

To set Zi (i = 1, 2, 3) to the above value, the capacitance values of

capacitors

44, 46, and 48 can be set to predetermined values using formula 1 (see Non-Patent Document 1).

Here, Cgs is the gate-source capacitance of FET14, FET16, and FET18, Ci (i=1, 2, 3) is the capacitance value of capacitance 44, capacitance 46, and capacitance 48, and gm is the mutual conductance of FET14, FET16, and FET18. Note that here, the mutual conductance and gate-source capacitance of FET14, FET16, and FET18 are assumed to be equal, and the operating frequency is sufficiently lower than the cutoff frequency of these FETs.

If the power supply voltage is lowered, the load line of each FET will change if left as is. For example, suppose the power supply voltage is lowered to 3.6 V, and FET switch 36 is opened to operate FET 18 in switch mode. In this case, the input impedance Z3 of FET 18 becomes 4 x Ropt. As a result, the load line of FET 18 will deviate from the optimal load line drawn with a dashed line, as shown in Figure 3.

In order to reduce the change in the load line, it is advisable to change the capacitance values of the variable capacitances of

capacitors

44 and 46. Specifically, the capacitance value C1 of capacitor 44 is set so that Z1 = 1/3 x 4 x Ropt, and the capacitance value C2 of capacitor 46 is set so that Z2 = 2/3 x 4 x Ropt. In this way, the change in the load line of FET12, FET14, and FET16 can be suppressed.

Similarly, when the power supply voltage is lowered to 2.4 V and FET switch 34 and FET switch 36 are opened to operate FET 16 and FET 18 in switch mode, the capacitance value C1 of capacitor 44 is set to Z1 = 1/2 x 4 x Ropt.

　Generalizing the explanation so far. Let the number of FETs in the stacked circuit be n (n is an integer of 2 or more), and let the FETs be numbered as described above. Let the load impedance seen from the drain terminal of the nth FET be Z0. Let the number of FETs performing amplifying operation among the second to nth FETs be m, and let the numbers of the FETs performing amplifying operation be 1 to m, in order from the smallest FET number in the stacked circuit. If k is an integer of 1 or more and m or less, then the input impedance seen from the source terminal of the kth FET performing amplifying operation should be set within the range of (k-0.5)/(m+1)×Z0 to (k+0.5)/(m+1)×Z0. Ideally, the input impedance should be set to k/(m+1)×Z0, but it is also acceptable to have a range of the above mentioned range.

Even if the power supply voltage is lowered in this way, the load line of the FET performing the amplifying operation can be made equal by appropriately setting the input impedance of the FET.

As described above, according to this embodiment, even if the power supply voltage is lowered, it is possible to apply a voltage between the drain and source terminals of the FET performing the amplifying operation that is sufficient for the FET to operate in the saturation region. This prevents a decrease in the efficiency of the power amplifier.

In addition, even if the power supply voltage is lowered, the load line of the FET performing the amplifying operation can be made equal. This prevents the efficiency of the power amplifier from decreasing.

In addition, because switching is performed using FET switches, there is no need for additional paths such as high-frequency bypass circuits in the areas where high-frequency signals are transmitted. This allows the circuit area to be reduced.

Embodiment 2.
In the power amplifier according to the second embodiment, in addition to the capacitance 44, capacitance 46, and capacitance 48 of the power amplifier 10 according to the first embodiment, an additional capacitance whose connection can be turned on/off by an FET switch is added.

Here, an explanation will be given using Figure 4, which shows only the vicinity of the gate terminal of FET 14. As shown in Figure 4, in addition to capacitance 44, a FET switch 64, an additional capacitance 62, and a FET switch 70 and an additional capacitance 68 are added. The additional capacitance 62 can be turned on/off by the FET switch 64. The additional capacitance 68 can be turned on/off by the FET switch 70.

Similar to the power amplifier 10 according to the first embodiment, the power amplifier according to this embodiment also uses four FETs involved in amplification, so as can be seen from the explanation of the first embodiment, it is preferable that the capacitance value of the capacitance connected to the gate terminal of FET 14 can be set to one of three values. In this embodiment, the three capacitance values can be switched by turning on/off FET switch 64 and FET switch 70.

The above is applicable not only to FET 14, but also to FET 16 and FET 18.

As described above, in this embodiment, the capacitance value can be changed digitally using a normal FET. Therefore, compared to analog-variable capacitance, control is simpler and the circuit area can be reduced.

Embodiment 3.
As shown in Fig. 5, the power amplifier 110 according to the third embodiment is obtained by differentiating the circuit configuration of the power amplifier 10 according to the first embodiment. Accordingly, the input signal also becomes a differential signal, and this differential signal is input to the input terminal 122 and the input terminal 123. By differentiating, it is possible to significantly suppress the influence of gain reduction caused by GND inductance, which is often a problem in a single-phase amplifier mounted on a Si-based LSI. Also, the power amplifier according to the second embodiment may be differentiated.

In addition, in the power amplifiers according to all the embodiments, GaAs FETs, InP FETs, etc. can be used instead of CMOS. When GaAs or InP is used, the backgate is usually floating.

12, 14, 16, 18 FET, 38, 40, 42 Resistor, 44, 46, 48 Capacitor, 32, 34, 36, 64, 70 FET switch, 20 Output matching circuit, 62, 68 Additional capacitor, 19 Stacked circuit

Claims

A stacked circuit having n (n is an integer of 2 or more) FETs,
Let the FET numbers be 1 to n, and i be an integer between 2 and (n-1), inclusive.
The first FET has a gate terminal to which an input signal is input, a drain terminal connected to the source terminal of the second FET, and a source terminal connected to GND.
The drain terminal of the i-th FET is connected to the source terminal of the (i+1)-th FET,
a stacked circuit in which an output signal is output from a drain terminal of the n-th FET, the drain terminal being a terminal connected to a power supply;
resistors connected to gate terminals of the second to n-th FETs in the stacked circuit, respectively;
a capacitance connected to an electrode of each of the resistors on the opposite side to the gate terminal;
a first switch connected in parallel with each of the resistors;
A power amplifier comprising:
The power amplifier according to claim 1 , wherein the first switch is a FET switch.
The FETs in the stacked circuit all have a maximum standard voltage of Vm.
The voltage applied to the drain terminal of the n-th FET in the stacked circuit is Vd,
Let j be an integer greater than or equal to 1 and less than or equal to n.
3. The power amplifier according to claim 1, wherein if (j-1) x Vm < Vd ≦ j x Vm, then (j-1) of the switches are closed and the remaining switches are opened.
The load impedance seen from the drain terminal of the n-th FET in the stacked circuit is Z0,
The number of FETs performing an amplifying operation among the second to n-th FETs of the stacked circuit is defined as m,
The numbers of the FETs performing the amplifying operation are numbered from 1 to m in ascending order of the numbers of the FETs in the stacked circuit,
Let k be an integer greater than or equal to 1 and less than or equal to m.
The input impedance seen from the source terminal of the kth FET performing the amplifying operation is set within a range from (k-0.5)/(m+1)×Z0 to (k+0.5)/(m+1)×Z0. The power amplifier according to any one of claims 1 to 3.
an additional capacitance that can be turned on/off by a second switch is provided in parallel with the capacitance;
The power amplifier according to claim 4 , wherein the input impedance is set by turning on/off the second switch.
The power amplifier according to claim 5 , wherein the second switch is a FET switch.
the input signal is a differential signal;
The power amplifier according to claim 1 , wherein the circuit configuration is differentiated.