JP3469680B2 - Semiconductor switch circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch circuit, and more particularly to a semiconductor switch circuit for improving the characteristics of a semiconductor switch circuit for connecting and disconnecting a high frequency signal in the ultra-high frequency band to the quasi-microwave band.

[0002]

2. Description of the Related Art In a device such as various radio equipment which handles a high frequency signal, a semiconductor switch using a field effect transistor or the like in order to intermittently or switch the transmission of the high frequency signal in the circuit according to the operation of the device. Circuits are often used.

FIG. 5 shows an example of a circuit of such a semiconductor switch. Hereinafter, the semiconductor switch circuit will be schematically described with reference to FIG. This semiconductor switch circuit has an input terminal 1 to which a high frequency signal is applied.
And an output terminal 2 for outputting a high frequency signal, the first
The field effect transistor (hereinafter, referred to as the first FET) 3 is connected to the input terminal 1 at the drain and to the output terminal 2 at the source. As the first FET 3, specifically, for example, a MESFE made of GaAs is used.
T (Metal Semiconducctor Field Effect Transistor)
Those having good high frequency characteristics such as

A gate voltage is applied to the gate of the first FET 3 from the gate terminal 5 via the resistor 4. In addition, a second FET called a shunt FET
6, the drain is connected to the input terminal 1 and the source is connected to the ground, and the gate voltage applied to the gate terminal 8 is applied to the gate through the resistor 7. A capacitor 9 is connected between the drain and gate of the second FET 6.

In such a configuration, the first FET 3
In the depletion mode, when a voltage having the same potential as the voltage at the input terminal 1 and the output terminal 2 is applied to the gate terminal 5, the first FET 3 becomes conductive and is applied to the input terminal 1. While the signal is output to the output terminal 2, when a voltage below the so-called pinch-off voltage of the first FET 3 with respect to the potentials at the input terminal 1 and the output terminal 2 is applied to the gate terminal 5, the first F
The ET3 becomes non-conductive, and the signal applied to the input terminal 1 is not output to the output terminal 2.

On the other hand, the second FET 6 is the first FET 3
When becomes conductive, it becomes non-conductive,
Further, when the first FET 3 is in the non-conducting state, a predetermined gate voltage is applied to the gate terminal 8 so that the first FET 3 is in the conducting state.
The operation of ET6 is just the reverse operation of the operation of the first FET3. By operating the second FET 6 in this manner, particularly, the isolation characteristic between the input terminal 1 and the output terminal 2 when the first FET 3 is in the non-conducting state is improved.

Then, the capacitor 9 is connected between the drain and the gate of the second FET 6 and folded, and the capacitor 9 increases the electrostatic capacitance between the drain and the gate of the second FET 6, thereby It is responsible for expanding the pass frequency band of the switch circuit to the lower frequency side.

[0008]

However, in the semiconductor switch circuit described above, the capacitor 9 provided between the drain and the gate of the second FET 6 functions to expand the lower limit of the pass frequency in the switch circuit, When a signal having a relatively large amplitude is applied to the input terminal 1, there is a problem that the isolation characteristic of the switch circuit is deteriorated. That is, in the circuit shown in FIG. 5, the first FET 3 is non-conductive, the second FET 6 is conductive, and the second FET 6 functions as a so-called shunt for an input signal. In this state, when a large-amplitude signal is applied to the input terminal 1 and the amplitude is especially swung to the negative side, the negative-polarity signal is applied to the gate of the second FET 6 by the capacitor 9 and the second F
According to the voltage division ratio determined by the parasitic capacitance of ET6, it is superimposed on the gate voltage applied in advance to the gate terminal 8.

When the second FET 6 is in the so-called depletion mode, this negative voltage is
The voltage previously applied to the gate terminal 8 in order to bring the FET 6 into the conductive state is canceled. Therefore, since the voltage applied to the gate of the second FET 6 approaches the so-called pinch-off voltage, the conduction state of the second FET 6 begins to collapse, the function as the shunt deteriorates, and the voltage is applied to the input terminal 1. The leaking signal leaks to the output terminal 2 and deteriorates the isolation characteristic.

The present invention has been made in order to solve the above problems, and its purpose is to increase the lower limit frequency of the pass band and, at the same time, to improve the isolation characteristic between the input and output terminals in a large amplitude input. An object of the present invention is to provide a semiconductor switch circuit capable of suppressing a decrease.

[0011]

In order to achieve the above object, the present invention is provided with a first semiconductor switch element that opens and closes between input and output terminals, and the first semiconductor switch element is non-conductive. In the state, the second semiconductor switch element that is in a conductive state is connected between the input terminal and the ground, and the lower limit that can be passed between the input terminal and the terminal that performs the switching function of the second semiconductor switch element. In a semiconductor switch circuit provided with a capacitor for frequency expansion,
When the second semiconductor switch element is in the conductive state,
It is characterized in that a switch means is provided for disconnecting the capacitor from the input terminal or the terminal having a switching function of the second semiconductor switch element.
In particular, the semiconductor switch element and the switch circuit are field effect transistors, the drain of the first field effect transistor serving as the first semiconductor switch element is connected to the input terminal, and the source is connected to the output terminal. The drain of the second field effect transistor as a semiconductor switch element is connected to the input terminal and the source thereof is connected to the ground, respectively, and the drain of the third field effect transistor as the switch means is connected to the input terminal and the source thereof is one end of the capacitor. And the gate of the first field effect transistor and the gate of the third field effect transistor are connected together so that the same gate signal is input to the gate of the second field effect transistor. The other end of the capacitor is connected to the gate, and the gate is The gate signal inputted to the first gate of the field effect transistor is preferred that reverse logic of the signal is possible input.

[0012]

According to the above structure, when the first semiconductor switch element is in the conductive state and the high frequency signal applied to the input terminal is output to the output terminal through the first semiconductor switch element, the switch is performed. By connecting the capacitor between the input terminal and the ground by the means, the lower limit frequency of the passing signal between the input and the output can be increased, while the first semiconductor switch element is in the non-conducting state, that is, the second semiconductor switch element. When the semiconductor switch element is in the conducting state, the capacitor is disconnected from the input terminal or the ground by the switching means, so that the capacitor affects the conducting state of the second semiconductor switching element. Will be suppressed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor switch circuit according to the first embodiment, for example, one applied to a circuit for handling high frequency signals in the ultra-high frequency band to the quasi-microwave band. The configuration is the same as the conventional configuration shown in FIG. That is, as shown in the figure, between the input terminal 1 to which a high-frequency signal is applied and the output terminal 2 to which a high-frequency signal is output, the first FET 3 as the first semiconductor switch element, and its drain are A second FET 6 serving as a second semiconductor switching element that is provided so that the source is connected to the input terminal 1 and the output terminal 2 respectively and that functions as a so-called shunt is provided between the input terminal 1 and the ground. In, the drain is connected to the input terminal 1 and the source is connected to the ground.

Further, in the present embodiment, a third FET 10 as a switch means and a capacitor 9 are connected in series between the input terminal 1 and the gate of the second FET 6 to form a third FET. The drain of the FET 10 is connected to the input terminal 1, the source is connected to the capacitor 9, and the other end of the capacitor 9 is connected to the gate of the second FET 6, and the third FET 10 and the capacitor (electrostatic capacitance) are connected. Between the connection point with the value C1) 9 and the ground, the third
A resistor (resistance value R4) 11 for applying a bias voltage is connected to the source of the FET 10. The capacitor 9 and the third FET 10 may be replaced with each other.

A resistor (resistance value R1) 4 is provided between the gate terminal 5 and the gate of the first FET 3 and the gate terminal 5
Between the gate and the gate of the third FET 10 (resistance value R
3) 12 are connected to each other, and the first FET3
The same gate voltage is applied to the third FET 10 and the third FET 10. Further, the gate terminal 8 and the second F
A resistor (resistance value R2) 7 is connected between the gate of the ET 6 and a gate voltage having an inverse logic to the gate voltage applied to the gate terminal 5 is applied.
The resistors 4, 7 and 12 prevent leakage of high frequency signals and prevent an excessive current from flowing from the terminals 5 and 8 side.

According to the above construction, when a signal is first taken out from the output terminal 2 (the terminals 1 and 2 are closed),
A gate voltage having the same potential as that of the input terminal 1 and the output terminal 2 is applied to the gate terminal 5, while a gate voltage sufficient to maintain a complete pinch-off state between the gate and source of the second FET 6 is applied to the gate terminal 8. Is applied. As a result, the first FET 3 becomes conductive, and the signal applied to the input terminal 1 passes between the drain and source of the first FET 3 and appears at the output terminal 2. On the other hand, in this case, the second FET 6 becomes non-conductive, and the third FE
T10 becomes conductive, and the input terminal 1 and the second FET
Capacitor 9 via the third FET 10 between the gates of 6
Is connected.

In this case, since the drain-source of the first FET 3 is in a linear low resistance state, the signal loss in this portion is extremely small. Similarly, since the drain-source of the third FET 10 is also in a low resistance state, the capacitor 9 is connected between the input terminal 1 and the gate of the second FET 6 via the low resistance of the third FET 10. It is in a state of

Therefore, the capacitor 9 is the second FET 6
Since it is connected in parallel to the parasitic capacitance Cgd between the gate and drain of the switch circuit, the low-frequency side of the pass band of this switch circuit is expanded as in the conventional case, and when a large amplitude signal is applied. Passage loss is reduced. That is, the critical frequency f on the low frequency side where this characteristic improvement is obtained is f = 1 /
It is represented by (2π × R2 × C1), and the above-mentioned characteristic improvement can be obtained at a frequency higher than the critical frequency f. From this formula,
It is understood that if the capacitance value C1 of the capacitor 9 is made larger, the critical frequency f can be set lower.

On the other hand, when the signal output from the output terminal 2 is stopped (the terminals 1 and 2 are opened), the gates of the first FET 3 and the third FET 10 are connected via the gate terminal 5. A voltage sufficient to completely pinch off the gate and source of these two FETs 3 and 10 is applied, and a voltage of the same potential as the source potential is applied to the gate of the second FET 6. As a result, the FETs 3 and 10 are both non-conductive, and the conductive state between the input terminal 1 and the output terminal 2 is released, while the second FET 6 is conductive and serves as a shunt for the input signal. Will fulfill the function of.

In this case, since the third FET 10 is non-conductive, between the input terminal 1 and the gate of the second FET 6, that is, between the drain and the gate of the second FET 6,
As a characteristic of the second FET 6 in the conduction state between the drain and the source of the second FET 6, the coupling with the parasitic capacitance existing in each of the drain, the gate, and the source of the second FET 6 is the main characteristic. , The influence of the capacitor 9 is eliminated. Therefore, when a large amplitude signal is applied to the input terminal 1 while the second FET 6 is in the conducting state, the second FET 6 may be incompletely conducting due to the influence of the capacitor 9 as in the conventional case. Therefore, deterioration of the isolation characteristic between the input / output terminals 1 and 2 is suppressed.

Here, it will be described below with reference to the equivalent circuit diagram shown in FIG. 2 that the isolation characteristic deterioration can be suppressed. In FIG. 2, the first and third FETs 3 and 10 are in a non-conducting state, and the second FET is
The AC equivalent circuit is shown when 6 is in a conducting state, that is, when the second FET 6 performs the shunt function and the input terminal 1 and the output terminal 2 are cut off.
That is, in the circuit of FIG. 1, the resistor 13 represented by the resistance value Rds2 between the drain and the source when the second FET 6 is conducting is connected between the input terminal 1 and the ground, and between the input terminal 1 and the ground. , The capacitor 14 represented by the parasitic capacitance value Cgd3 between the gate and drain of the third FET 10, the capacitor 15 represented by the parasitic capacitance value Cgs3 between the gate and source, and the resistor (resistance value R4) 11 were connected in series. It is equivalent to the one.

A resistor (resistance value R3) 12 is connected between the connection point between the capacitors 14 and 15 and the ground, and the connection point between the capacitor 15 and the resistor 11 and the input terminal 1 are connected.
Is equivalent to the capacitor 16 represented by the parasitic capacitance value Cds3 between the drain and the source of the third FET 10 being connected between and. Further, a capacitor 17 represented by a parasitic capacitance value Cgd2 between the gate and drain of the second FET 6 and a capacitor 18 represented by a parasitic capacitance value Cgs2 between the gate and source of the second FET 6 are connected in series to both ends of the resistor 13. Things are equivalent to being connected in parallel. Furthermore, the connection point between these two capacitors 17 and 18 is grounded via a resistor (resistance value R2) 7, and
It is equivalent to one connected to the connection point between the capacitor 15 and the resistor 11 via the capacitor 9.

By the way, when the first FET 3 is in the non-conductive state, that is, when the input terminal 1 and the output terminal 2 are in the open state, the isolation characteristic between the input and output terminals is excellent. To achieve this, the impedance between the input terminal 1 and the ground must be kept as low as possible in the equivalent circuit shown in FIG. In the equivalent circuit of FIG. 2, the resistance value Rds2 of the resistor 13 is a so-called on-resistance value of the second FET 6, so that the value shows a low value when the second FET 6 is in a completely conductive state. Become.

On the other hand, the ratio of the high frequency signal applied to the input terminal 1 to the gate of the second FET 6 (the connection point between the capacitor 17 and the capacitor 18 in FIG. 2) mainly depends on the capacitance. It is determined by the composition of the values Cds3, C1, Cgd2 and Cgs2 and the partial pressure. In particular, when the amplitude of the high frequency signal applied to the input terminal 1 becomes excessive, the second FET
This results in biasing the gate of the MOSFET 6 to the negative side, which increases the so-called on-resistance of the second FET 6 and deteriorates the isolation characteristic.

Therefore, in order to prevent such an increase in on-resistance, it is necessary to reduce the high frequency signal component divided by the gate of the second FET 6, and for that purpose, the second F
The goal is to reduce the gate-drain capacitance of ET6 as much as possible. This is achieved in particular by eliminating the influence of the capacitance value C1 of the capacitor 9.

If the gate width of the third FET 10 is equal to or smaller than that of the second FET 6, the capacitance value Cds3 of the capacitor 16 is sufficiently lower than the capacitance value C1 of the capacitor 9. Can be
Under such a premise, the capacitance added externally between the gate and drain of the second FET 6 is as follows.

First, let Cgdx be the electrostatic capacitance value added externally between the gate and drain of the second FET 6, and Cj3 be the combined capacitance value of the capacitors 14, 15 and 16, and C
gdx is expressed by the following equation (1). Cgdx = 1 / {(1 / C1) + (1 / Cj3)} (1) However, Cj3 is represented by the following equation (2). Cj3 = Cds3 + 1 / {(1 / Cgs3) + (1 / Cgd3)} (2) Therefore, Cgdx <Cgd2 can be satisfied, and the second F
It is possible to reduce the influence of the superposition of the high frequency signal on the gate of the ET6.

FIG. 4 shows, as an example of the test results, a characteristic diagram showing the relationship between the magnitude of the input signal and the isolation. A high frequency signal of 100 MHz is applied to the input terminal 1 and its input power is increased. It shows the change in isolation between the input and output terminals with respect to the change in. As shown in this figure, in the conventional circuit shown by the dotted line, there is almost no change in the isolation with respect to the input power until the input power is around 10 dBm, but thereafter the input power is 26 dB.
Isolation deterioration of about 30 dBm is seen up to around m. On the other hand, in the circuit of the present invention shown by the solid line, when the input power is from 10 dBm to around 26 dBm,
The decrease in isolation was about 6 dBm, which can be seen to be much improved when a large amplitude input is applied.

Next, a second embodiment will be described with reference to FIG. The circuit of the second embodiment is basically the same as the circuit of the first embodiment described above, that is, two circuits, that is, a first switch section 20 and a second switch section 2.
1 is provided so that either one of the two types of signals can be selectively obtained at the output terminal 2. In addition, in the following description, each component of the first switch unit 20 will be denoted by the same reference numeral as in FIG. 1, and description thereof will be omitted.
The differences from the circuit of the embodiment will be mainly described.

In FIG. 3, the fourth FET 22 of the second switch section 21 is the first FET 3 and the fifth FET 23.
Is the second FET6, the sixth FET24 is the third FET
10 corresponds to each. The capacitor 25 is connected to the capacitor 9, the resistor 26 is connected to the resistor 4, and the resistor 2 is connected to the resistor 2.
Reference numeral 7 corresponds to resistance 7, resistance 28 corresponds to resistance 11, and resistance 29 corresponds to resistance 12, respectively.

In the second embodiment, one ends of the resistors 26 and 29 are both connected to the gate terminal 8 of the first switch section 20, while one end of the resistor 27 is the first.
It is connected to the gate terminal 5 of the switch section 20 so that the operation of the second switch section 21 and the operation of the first switch section 20 are just opposite. That is, for example, when 0 v is applied to the gate terminal 5 and −2 v is applied to the gate terminal 8, the first FET 3 of the first switch section 20 is applied.
Is turned on, while the fourth FET 22 of the second switch section 21 is turned off. Therefore, in this case, the high frequency signal applied to the input terminal 1 is obtained at the output terminal 2, and the output of the high frequency signal applied to the input terminal 30 to the output terminal 2 is cut off. Becomes

On the other hand, when -2v is applied to the gate terminal 5 and 0v is applied to the gate terminal 8, the first FET 3 of the first switch section 20 is turned off and the second FET 2 is turned off.
The fourth FET 22 of the switch section 21 becomes conductive. Therefore, in this case, the high frequency signal applied to the input terminal 30 is obtained at the output terminal 2.
The output of the high frequency signal applied to the input terminal 1 to the output terminal 2 is cut off.

In the second switch section 21, when the fifth FET 23 is in the conducting state, the capacitor 2
The effect that 5 has on the gate voltage of the fifth FET 23 is basically the same as that described using the equivalent circuit shown in FIG. 2, and therefore the detailed description thereof will be omitted here. It will be omitted.

In this embodiment, the FET is used as the semiconductor switching element, but the circuit may be constructed by using another semiconductor switching element as long as it has a switching characteristic similar to that of the FET. FET 10 of 3
A pin diode may be used instead of the sixth FET 24.

[0035]

As described above, according to the present invention,
When the semiconductor switch element provided in this semiconductor switch circuit and performing a so-called shunt function is in a conductive state, the capacitor provided between the input terminal and the ground provided to increase the pass frequency of the semiconductor switch circuit is That is, when the input and output terminals are in the open state, the capacitor is placed in a predetermined position only when the high frequency signal is passed by configuring the input terminal or the ground so as to be disconnected. Since they are connected, they function to expand the low frequency band of the passing signal as in the conventional case. On the other hand, when the input and output terminals are in the open state, the influence of the capacitor on the conduction state of the semiconductor switch that performs the shunt function is reduced,
In particular, it is possible to suppress the deterioration of the isolation characteristic when a signal of large amplitude is applied to the input terminal and improve the characteristic.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor switch circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the circuit shown in FIG. 1 for an AC signal.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment.

FIG. 4 is a characteristic diagram showing a change in isolation with respect to a change in input power in a conventional circuit and a semiconductor switch circuit according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional switch circuit.

[Explanation of symbols]

1,30 ... Input terminal, 2… Output terminal, 3 ... First FET, 5… Gate terminal, 6 ... the second FET, 9, 25 ... Capacitor, 10 ... Third FET, 22 ... Fourth FET, 23 ... Fifth FET, 24 ... 6th FET.

Claims (2)

(57) [Claims] 1. A first semiconductor switch element is provided which opens and closes between input and output terminals, and a second semiconductor switch element which becomes conductive when the first semiconductor switch element is non-conductive. In the semiconductor switch circuit, which is connected between the input terminal and the ground, and provided with a capacitor for expanding the lower limit frequency that can be passed between the input terminal and the terminal that carries out the switching function of the second semiconductor switching element, When the second semiconductor switch element is in the conductive state,
A semiconductor switch circuit comprising switch means for disconnecting the capacitor from the input terminal or a terminal having a switching function of the second semiconductor switch element. 2. The semiconductor switch element and the switch means are field effect transistors, the drain of the first field effect transistor as the first semiconductor switch element is connected to the input terminal, and the source is connected to the output terminal, respectively. The drain of the second field effect transistor as the second semiconductor switch element is connected to the input terminal and the source thereof is connected to the ground, respectively, and the drain of the third field effect transistor as the switch means is connected to the input terminal and the source is The second electric field is connected to one end of a capacitor, the gate of the first field effect transistor and the gate of the third field effect transistor are connected together, and the same gate signal is input to the gate of the second field effect transistor. The other end of the capacitor is connected to the gate of the effect transistor, and The semiconductor switching circuit of the first claim, wherein the inverse logic of the signal is possible input to the gate signal input to the gate of the first field effect transistor.