JPH0645646A - Infrared light-emitting diode provided with p-n heterojunction and its manufacture - Google Patents

Abstract

PURPOSE:To obtain an infrared light-emitting diode wherein its external light- emitting efficiency, its internal quantum efficiency and the like are excellent and its performance is high. CONSTITUTION:An n-type GaAs layer and a p-type GaAs layer 3 are epitaxially grown on a GaAs crystal substrate 1 by an ordinary method. The n-type GaAs layer can be omitted. In addition, an n-type Ga1-xAlxAs mixed crystal layer 7 is grown on the p-type GaAs layer 3 and a p-n heterojunction 8 is formed between it and the p-type GaAs layer 3. An n<+> type layer 9 may be grown additionally on the n-type mixed crystal layer 7. By the etching and removal of the n-type mixed crystal layer 7, by the conversion of the n-type mixed crystal layer 7 into a p-type layer by selectively diffusing Zn, by the breakdown of the p-n heterojunction 8 by applying an electric current in the reverse direction and the like, a nonrectifiable current passage 12 reaching the p-type layer 3 is formed, and ohmic electrodes 5, 6 corresponding to an n-type and a p-type are attached.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an infrared light emitting diode utilizing light emission having a wavelength longer than the absorption edge of GaAs and a method for manufacturing the same.

[0002]

2. Description of the Related Art Infrared light emitting diodes are manufactured from an epitaxial wafer having a homojunction pn junction manufactured by liquid phase epitaxy of GaAs. For liquid phase epitaxy, GaAs heavily doped with Si
A melt is used. In the GaAs layer crystallized from the melt at a high temperature of 850 to 900 ° C. or higher, most of heavily-doped Si replaces Ga lattice points to form a Chardonna. The temperature of the melt is lowered by the subsequent slow cooling. GaAs crystallized from a low temperature melt
In addition to the shallow donor, many of the layers replace the As lattice points to form a shallow acceptor. When the shallow donor and the shallow acceptor occupy the closest lattice point, a Si _Ga —Si _As pair is formed and a p-type layer portion of the deep acceptor level is formed.

In the formed epitaxial layer, a GaAs growth layer 2 crystallized at a high temperature is formed on a GaAs substrate crystal 1 as shown in the layer structure of FIG. The GaAs growth layer is an n-type layer of a Chardonnay made of silicon that replaces the Ga lattice points. n-type GaAs growth layer 2
The GaAs growth layer 3 formed on is a epitaxial layer crystallized from a melt at a relatively low temperature, and is a deep acceptor level p-type layer due to the Si _Ga —Si _As pair occupying the closest lattice point. Has become. As a result, in the same epitaxial growth process, pn is naturally formed in one layer of GaAs.
An epitaxial wafer having the junction 4 formed is obtained.
In this epitaxial wafer, a portion near the GaAs substrate crystal 1 becomes the n-type layer 2 and a portion near the surface becomes the p-type layer 3 due to the crystallization phenomenon in the growth process. p
When a forward current is applied to the -n junction 4, light emission having a wavelength longer than the absorption edge of GaAs due to the deep acceptor level is obtained. Utilizing the fact that the generated long-wavelength light passes through the GaAs substrate well, a light emitting diode is manufactured from the epitaxial wafer having the layer structure shown in FIG.

In the element of the light emitting diode, as shown in FIG. 2, the periphery of the p-type layer 3 is removed by etching to expose the n-type layer 2 on the inner layer side. The ohmic electrode 5 is formed on the exposed portion of the n-type layer 2, and the remaining p-type layer 3 is formed.
The ohmic electrode 6 is formed in the central portion of the. When a forward current is applied to the pn junction 4 via the ohmic electrodes 5 and 6, the deep acceptor of the p-type layer 3 causes 9
Light emission with a long wavelength of 20 to 940 nm is obtained. The long-wavelength light passes through the GaAs substrate crystal 1 with a high transmittance and is emitted to the outside of the chip. At this time, total reflection of the light generated from the inside of the chip can be prevented by polishing or etching the back surface and the side surface of the GaAs substrate 1 on which the epitaxial layer corresponding to the light emitting surface is not grown to be spherical. However, when the total reflection or its influence is not a problem, the chip cut out from the GaAs substrate crystal 1 may be used in the cubic shape without performing the spherical processing at all or completely.

[0005]

The light emitting diode having the chip structure shown in FIG. 2 has not been actually mass-produced although the external light emission efficiency is theoretically excellent. This is due to the following drawbacks. Since the outermost surface layer of the pn junction 4 is a p-type layer, the ohmic electrode 5 for the n-type layer 2 on the inner layer side may be a planar type in which the ohmic electrode 5 of the p-type layer 3 is provided on the same surface. Have difficulty. Therefore, the chip cannot be die-bonded on the stem or the lead frame with good reproducibility. If the outermost surface layer is n-type, a part of the outermost surface layer is changed to p-type by selective diffusion of Zn, and the internal p-type layer 3
A non-rectifying current path can be formed between and. However, Ga
As-based compound semiconductors do not have a practical diffusion source that changes p-type to n-type. Therefore, as a convenient method for providing non-rectifying conduction to the internal n-type layer 2, a part of the p-type layer 3 is removed by etching as shown in FIG. As a result, it becomes a mesa type, and ohmic electrodes 5 and 6 are formed.
There is a step between the two.

The n-type layer 2 and the p-type layer 3 forming the pn junction 4 are crystallized from the same GaAs melt, although they are different in high temperature and low temperature. Therefore, n
There is almost no difference in the photorefractive index between the mold layer 2 and the p-type layer 3, and the pn junction 4 itself cannot be used as a reflecting surface or the like in order to further enhance the external light emission efficiency. For example, in the chip structure of FIG. 2, of the light emitted near the pn junction 4, the p-type layer 3 passes through direct or indirect interface reflection or the like.
Most of those that have reached the surface of the ohmic electrode 6
It is absorbed by and is not released to the outside. The absorption of light by the ohmic electrode 6 is a non-negligible loss that lowers the luminous efficiency because the generated light is long-wavelength light that passes through GaAs well.

Since the pn junction 4 is a homojunction composed of the GaAs layers 2 and 3, minority carriers are injected into the n-type layer 2 as well as the p-type layer 4 when a forward current is applied. . As a result, long-wavelength light is generated by recombination of electrons injected into the p-type layer 3 in which the deep acceptor is present, and in addition, the shear drainer re-creates holes injected into the n-type layer 2 which is a majority carrier. Short wavelength emission due to the coupling also occurs. Therefore, the width of the emission spectrum is widened, and the half-value width may reach 70 to 80 nm. In this respect, the application as a monochromatic light source is restricted, or the effective wavelength component is insufficient.

The radiative recombination between the holes and the shallow donor in the n-type layer 2 has a time difference with respect to the radiative recombination between the electrons and the deep acceptor in the p-type layer 3. Therefore, when light emission is modulated by the drive current, the response speed of light intensity is extremely slow and the cutoff frequency is usually 300 kHz.
It remains about z. The present invention has been devised to solve such a problem, and by forming a pn heterojunction, the external emission efficiency and the internal quantum efficiency are excellent, the width of the emission spectrum is narrow, and the current modulation. It is an object of the present invention to provide an infrared light emitting diode which has a fast response speed to and is extremely easily assembled by a die bonding method.

[0009]

In order to achieve the object, an infrared light emitting diode of the present invention comprises a p-type GaAs layer provided on a GaAs substrate crystal and having a deep acceptor by heavy doping of Si, and An n-type mixed crystal layer formed of Ga _{1 -x} Al _x As, which is provided so as to overlap with the p-type GaAs layer and which is doped with a Chardonna such as Te, S, Se, or Sn other than Si, and the p-type GaAs layer. A pn heterojunction formed between the mixed crystal layer and a non-rectifying current path from the chip surface to the p-type layer formed by eliminating or destroying part of the pn heterojunction. It is characterized by having and.

In this infrared light emitting diode, a p-type layer of GaAs having a deep acceptor by heavy doping of Si is epitaxially grown on a GaAs substrate crystal, and a shallow drainer is used for Ga _1-x Al _x As.
An n-type mixed crystal layer is formed on the p-type layer and epitaxially grown to form a non-rectifying current path from the surface of the n-type mixed crystal layer to the p-type layer. And an ohmic electrode for the n-type mixed crystal layer is formed on the epitaxial growth layer side.
The non-rectifying current path is provided by etching away the n-type mixed crystal layer around the chip. Alternatively, Zn is selectively diffused from the surface side to the n-type mixed crystal layer, or p is applied by a reverse current.
A non-rectifying current path can also be formed by partially breaking down the -n heterojunction.

In the present invention, the p-type layer 3 having a deep acceptor by Si heavy doping is grown on the GaAs substrate crystal 1 as in the conventional case. But p
It is not always necessary to grow the n-type layer 2 inside the mold layer 3. For example, Si-heavy-doped Ga-
It is also possible to keep the GaAs melt at a low temperature of 800 ° C. or lower and crystallize the p-type layer 3 as the first layer on the GaAs substrate crystal 1 from the beginning. In FIG. 3, p is provided through the n-type layer 2.
The case where the mold layer 3 is grown on the GaAs substrate crystal 1 is shown, and FIG. 4 shows the case where the p-type layer 3 is grown directly on the GaAs substrate crystal 1. By growing a Ga _1-x Al _x As layer, which is the n-type mixed crystal layer 7, on the p-type layer 3,
-N form a heterojunction 8. Mixed crystal ratio x of n-type mixed crystal layer 7
Is usually about 0.3 to 0.4. Also,
The donor impurity with which the n-type mixed crystal layer 7 is doped is S
Te, S, Se, S forming a shear drainer other than i
n, etc. are used. With this layered structure, the p-type portion near the pn heterojunction 8 becomes the radiative recombination region.

A non-rectifying current path is formed inside the p-type GaAs layer 3 from the direction of the n-type mixed crystal layer 7 on the outermost surface forming the pn junction 8. To form a non-rectifying current path,
Various methods can be adopted. For example, by selectively diffusing Zn in a part of the n-type mixed crystal layer 7 on the outermost surface, that part is converted to p-type. Alternatively, after a part of the n-type mixed crystal layer 7 is separated by forming an etching groove having a depth reaching the pn junction 8 from the surface, a reverse current is applied to this part of the pn heterojunction 8. By p
-N Heterojunction 8 is partially broken down. Alternatively, although it becomes a mesa type, an internal n-type layer 2 is formed by etching.
It is also possible to expose. Next, ohmic electrodes for the p-type layer and the n-type layer are formed in the non-rectifying current path portion and the other portion, respectively. As a result, the main part of the device used for the light emitting diode is completed.

[0013]

[Operation] In the light emitting diode of the present invention, GaA
There is a p-type layer 3 on the side close to the s substrate crystal 1, an n-type mixed crystal layer 7 on the chip surface side, and a pn heterojunction 8 between the p-type layer 3 and the n-type mixed crystal layer 7. Has been formed. Due to this layer structure, it has the following advantages that cannot be obtained by the conventional light emitting diode. When Zn is selectively diffused in a part of the n-type mixed crystal layer 7 on the outermost surface, a non-rectifying current path to the inner p-type layer 3 is easily formed. Therefore, the p-type layer 3 is formed on the same plane.
An ohmic electrode can be formed for each of the n-type mixed crystal layer 7 and the n-type mixed crystal layer 7. Since there is no step between the respective ohmic electrodes, die assembly by die bonding becomes extremely easy.

The n-type mixed crystal layer 7 on the outer side of the p-type layer 3 serving as a light emitting region has a lower optical refractive index than GaAs. Of the light generated in the p-type layer 3, most of the light projected to the pn heterojunction 8 directly or by interfacial reflection from the chip surface portion is totally reflected to the GaAs substrate crystal 1. After entering, it is emitted to the outside. Therefore, the light absorption by the ohmic electrode is small, and the external light emission efficiency is improved.

The n-type mixed crystal layer 7 has a wider energy band gap than the p-type GaAs layer 3. Therefore, hole injection from the p-type layer 3 is blocked, and only electrons from the n-type layer are injected as minority carriers. As a result, radiative recombination occurs only in the p-type layer 3 in which the deep acceptor is present, the width of the emission spectrum is narrower and the time required for the radiative recombination is shorter than in the conventional device. Therefore, the performance as a monochromatic light source is excellent, and the response speed to current modulation is also improved. For example,
In the infrared light-emitting diode according to the present invention, the half-width of the emission spectrum is narrowed to about 60 nm, and the cut-off frequency of modulation is increased to 600 kHz or more, as is found from the experimental results. In this way, the light emitting diode of the present invention solves and improves upon the problems of the conventional type. Further, since the heterojunction is built in, the internal quantum efficiency of light emission is also improved.

[0016]

Example 1 (Epitaxial growth) As a GaAs substrate crystal 1, a thickness of 400 μm and a plane orientation (1
The wafer of (00) was used. The undoped crystal exhibits higher light transmittance than the doped crystal. In FIG. 3, an n-type layer 2 and a p-type layer 3 are formed on the GaAs substrate crystal 1 by Si.
Was grown from a heavy-doped melt, and in FIG. 4, only the p-type layer 3 was grown while maintaining the melt at a low temperature. In each case, a Ga melt containing 2 atomic% of Si was used as a source of liquid phase epitaxy in which GaAs was dissolved to a saturated concentration at a temperature 5 ° C. higher than the growth start temperature of each Ga melt.

In the case of FIG. 3, the growth start temperature is 870 ° C.
Set to. At this time, the n-type layer 2 made of Si in which Ga lattice points were replaced was first crystallized on the GaAs substrate crystal 1. Then, as the temperature of the melt becomes low, As
Si occupying the lattice point and S occupying the closest Ga lattice point
The deep acceptor by the pair with i increased, and the p-type layer 3 grew on the n-type layer 2. On the other hand, in the case of FIG. 4, the growth start temperature was set to 850 ° C. Since the melt is maintained at a low temperature, there is no growth of the n-type layer 2 and Ga
The p-type layer 3 was directly formed on the As substrate crystal 1.

In either case, the melt is gradually cooled from the temperature 10 ° C. higher than the respective growth start temperature at a cooling rate of 1 ° C./min, and the melt at the growth start temperature is transferred to the GaAs substrate crystal 1. The n-type layer 2 and the p-type layer 3 were grown by bringing them into contact with the surface and continuing slow cooling. The growth rate of the n-type layer 2 and the p-type layer 3 was 1.2 μm / min. p
The GaAs substrate crystal 1 on which the mold layer 3 has grown has a melt of 840
After the Ga-GaAs melt was removed when the temperature was lowered to ° C, it was brought into contact with the second melt. 84 as the second melt
Ga-G in which GaAs is dissolved to a saturation concentration at a temperature of 0 ° C.
Al equivalent to 0.07 wt% of Ga in the aAs-based melt
And the addition of Te corresponding to 0.017% by weight of Ga was used. Since GaAs is dissolved and saturated in Ga at about 20 atomic% at 900 ° C., about this amount of massive GaAs is added to the melt. The melt is 9
Since the supersaturated component crystallizes and floats as a solid in the upper layer of the melt in any state of being gradually cooled to any temperature of 00 ° C. or less, the saturated concentration is always maintained. Therefore, it is not necessary to precisely control the amount of GaAs added. In this respect, the Ga-GaAs melt for growing the n-type layer 2 and the p-type layer 3 is also the same.

The second melt is kept at a temperature of 840 ° C. and brought into contact with the surface of the p-type layer 3. The melt is gradually cooled and separated from the surface of the p-type layer 3 at a temperature of 836 ° C. In the meantime, a Ga _1-x Al _x As layer having a thickness of 2 μm is superposed on the p-type layer 3 as the n-type mixed crystal layer 7, and the pn heterojunction 8 is formed.
Was formed. Further, the third melt was brought into contact with the surface of the n-type mixed crystal layer 7, and the gradual cooling was further advanced to grow a GaAs layer as the n + type layer 9. As the third melt, Ga at which GaAs is saturated at 830 ° C.
A GaAs-based melt to which Te corresponding to 0.06 wt% of Ga was added was used. After gradually cooling to 834 ° C., this melt was separated from the surface of the n-type mixed crystal layer 7. G
The epitaxial wafer in which at least the p-type layer 3, the n-type mixed crystal layer 7, and the n + -type layer 9 were grown on the aAs substrate crystal 1 was allowed to cool to room temperature and then taken out of the growth furnace.

In the above liquid phase epitaxial growth,
The thickness of each crystallized layer grown on the GaAs substrate crystal 1 was as follows. First containing Si at a high concentration of 2 atomic%
In the example of FIG. 3, n-type layers 2 and 2 of 15 μm
A 1 μm p-type layer, in the example of FIG. 4, a 5 μm p-type layer 3 was formed. An n-type mixed crystal layer 7 having a thickness of 2 μm was formed from the second melt containing Al in both cases of FIGS. 3 and 4. Te
An n + -type layer 9 having a thickness of 2 μm was formed from the third melt containing Pd in both cases of FIG. 3 and FIG.

An infrared light emitting diode chip was manufactured from the epitaxial wafer having the pn junction 8 thus prepared. 5 to 7 show the structure of the chip portion in the obtained pn heterojunction type infrared light emitting diode. Using an epitaxial wafer having any of the layer structures shown in FIGS. 3 and 4, an infrared light emitting diode having substantially no difference can be obtained. That is, the n-type layer 2 formed on the GaAs substrate crystal 1 shown in FIG. 3 is naturally formed when crystallized from the high temperature melt, and as shown in FIG. Even if the layer structure lacks the layer 2, the chip structure of the infrared light emitting diode can be formed. Rather, n-type layer 2
It is more advantageous to form the chip structure of the infrared light emitting diode in the absence of the above. In FIG. 5, the n-type layer 2 is GaAs
FIG. 6 shows the case where the crystal is grown on the substrate crystal 1.
Also, FIG. 7 shows the case where the n-type layer 2 is omitted.

Example 2 (Formation of Non-rectifying Current Path by Etching) In the chip structure of FIG. 5, S is formed on the GaAs substrate crystal 1.
n-type layer 2 made of i-doped GaAs layer 2, p-type layer 3 having deep acceptor by Si doping, Al
N-type mixed crystal layer 7 composed of a doped Ga _1-x Al _x As layer
And an n + type layer 9 composed of a Te-doped GaAs layer are sequentially superposed. A pn heterojunction 8 is formed at the interface between the p-type layer 3 and the n-type mixed crystal layer 7.

The peripheral portion of the n + type layer 9 on the outermost surface side and the n type mixed crystal layer 7 on the lower side thereof was removed by etching. An etchant having a volume ratio of sulfuric acid: hydrogen peroxide: water of 2: 1: 1 was used for etching. In the peripheral portion of the etched chip, the p-type layer 3 having a deep acceptor due to heavy doping of Si was exposed. An Al layer was formed on the exposed part of the p-type layer 3 to form an ohmic electrode 6 for p-type. In addition, n + remaining in the center of the chip
On the mold layer 9, a multilayer vapor deposition film in which nickel and Au were superposed on an Au—Ge based eutectic alloy was provided to form the ohmic electrode 5 for n-type. The ohmic electrodes 5 and 6 can be formed by various methods using photolithography techniques such as ordinary vacuum deposition, photoetching, and liftoff.

In the example of FIG. 5, the ohmic electrode 6 is formed by the lift-off method. That is, after etching the peripheral portion of the chip, a negative photoresist is applied to the entire surface of the wafer by spinner and prebaked at 190 ° C. for 30 minutes.
Next, the Al electrode non-formed portion including the central portion of the chip was exposed. Further, after post-baking at 130 ° C. for 1 hour, development was carried out, and the resist was removed only from the Al electrode generating portion in the peripheral portion of the chip. Next, Al was vacuum-deposited on the entire surface of the wafer to a thickness of 1 μm, and Al deposited on the surface of the resist was peeled off together with the resist using a resist remover. Au-G
e / Ni / Au multilayer evaporation film (thickness 0.3 / 0.5 /
The same lift-off operation for 1.0 μm)
The ohmic electrode 5 for n-type was formed.

The wafer on which the ohmic electrodes 5 and 6 were formed was heated in a nitrogen stream at 400 ° C. for 3 minutes. By this heating, the contact resistance between the ohmic electrodes 5, 6 and the n + type layer 9 and the p type layer 3 could be reduced to about 0.08 mΩ / cm ² . The chip after the heat treatment was separated from the epitaxial wafer by a dicing saw. Next, as shown in FIG. 5, the p-type layer 3 and the n + -type layer 9 of each chip were connected to the plus lead 10 and the minus lead 11 of the lead frame, respectively, by die bonding.

Positive lead 10 and negative lead 11
When a forward current is passed through the pn heterojunction 8 via
P-type layer 3 having a deep acceptor from the type mixed crystal layer 7
Electrons were injected into the matrix with high injection efficiency, causing radiative recombination. As a result, infrared light having a long wavelength around 930 nm was emitted. This long-wavelength light was well transmitted through the GaAs substrate crystal 1, and part of it was emitted to the outside of the chip.
At this time, p near the pn heterojunction 8 which is a light emitting region
Most of the light that is reflected directly from the mold layer 3 or reflected at the interface between the GaAs substrate crystal 1 and the outside and indirectly returned to the p-type layer 3 and is incident on the pn heterojunction 8 has a refractive index. The light is totally reflected by the low n-type mixed crystal layer 7 and returns to the GaAs substrate crystal 1 again. Therefore, the external light emission efficiency showed a high value.

Further, in the n-type mixed crystal layer 7 having a wide energy forbidden band and the pn heterojunction 8 of the p-type layer having a relatively narrow energy forbidden band, the n-type mixed layer 3 to the n-type mixed layer are formed. The injection of holes into the crystal layer 7 is blocked, and p
Holes are confined in a high concentration in a portion close to the -n heterojunction 8. Therefore, the probability of radiative recombination with the electrons injected here is increased, and the internal luminous efficiency is also increased. Furthermore, when the surface of the GaAs substrate crystal 1 is processed into a hemispherical surface or the like to form a dome-shaped light emitting diode in which total reflection at the interface is prevented, the external light emission efficiency is further enhanced.

Example 3 (Formation of Non-rectifying Current Path by Selective Diffusion of Zn) The non-rectifying current path from the chip surface to the p-type layer 3 having a deep acceptor is part of the n-type mixed crystal layer 7. It can be formed by selectively diffusing Zn. Although the epitaxial wafer in which the p-type layer 3 is directly grown on the GaAs substrate crystal 1 is used in the example of FIG. 6, the p-type layer 3 is grown via the n-type layer 2 shown in FIG. Epitaxial wafers can also be used. On a GaAs substrate crystal 1 that has been polished into a hemispherical shape, a p-type layer 3 composed of a Si-doped GaAs growth layer having a deep acceptor crystallized at a relatively low temperature and a Ga _1-x Al _x As growth layer. The n-type mixed crystal layer 7 is sequentially superposed, and a pn heterojunction 8 is formed between the p-type layer 3 and the n-type mixed crystal layer 7.
Further, in order to reduce the contact resistance with the ohmic electrode 5, a n-type GaAs growth layer heavily doped with Te is used.
The + type layer 9 is formed on the n-type mixed crystal layer 7.

The n + type layer 9 in the peripheral portion of the chip and the n type mixed crystal layer 7 inside thereof are converted into p type by selectively diffusing Zn from the surface, and the non-rectifying current path 12 to the p type layer 3 is formed. Is formed. Non-rectifying current path 1
On the surface of 2, the ohmic electrode 6 is formed by Al vapor deposition. The ohmic electrodes 5 and 6 were formed by the lift-off method similar to that described in FIG. The non-rectifying current path 12 was formed by the following Zn selective diffusion method. First, a mixed gas containing ammonia and monosilane at a volume ratio of 1: 1 is flowed in a nitrogen gas atmosphere on the surface of the epitaxial growth layer of the wafer, the temperature of the substrate is set to 300 ° C., and plasma CVD is used to form a silicon nitride film having a thickness of 1500 Å. A film was formed. Since the silicon nitride film is used as a diffusion mask, the silicon nitride film formed around the chip was removed. At this time, after coating a negative photoresist with a spinner and prebaking at 90 ° C. for 30 minutes,
An etching solution in which 10 vol% ammonium fluoride is added to hydrofluoric acid is used as an etching mask using a post-baked resist in which the non-removed portion is exposed to light and developed and then heated at 190 ° C. for about 1 hour. The silicon nitride film was removed by etching.

The wafer on which the diffusion mask was formed was sealed in a quartz ampoule which was evacuated together with a small amount of Zn and a small amount of As. Then, Zn was selectively diffused by heating at 700 ° C. for 50 minutes. At this time, the amount of As enclosed was suitable such that the atmospheric pressure in the quartz ampoule was 0.8 atm at a diffusion temperature of 700 ° C. In the manufactured chip, p- was formed through the ohmic electrodes 5 and 6 shown in FIG.
When a forward current is applied to the n-heterojunction 8, p of the p-type layer 3
Infrared light having a long wavelength of about 930 nm was generated from a portion close to the -n heterojunction 8. Here, since the holes are confined in the heterojunction portion, the internal light emission efficiency is high, and a part of the generated light is totally reflected by the n-type mixed crystal layer 7 having a low refractive index and travels toward the GaAs substrate crystal 1. The external luminous efficiency was also high. Especially, since the surface of the GaAs substrate crystal 1 is processed into a hemispherical shape, the interface reflection at this part is small, and the value of 35% is good for those with good external quantum efficiency.
Also reached. In addition, the full width at half maximum of the emission spectrum is 59n, which is narrower than 70 nm of the conventional Si-doped light emitting diode.
m, and the cutoff frequency due to current modulation is 30
It was improved from 0 lHz to 700 lHz.

Example 4 (Formation of non-rectifying current path by partial breakdown breakdown of pn junction) Next, an example in which a pn heterojunction type infrared light emitting diode is manufactured by the minimum number of steps will be described. To do. In this example, the p-type layer 3 is formed of GaAs by the low temperature growth shown in FIG.
An epitaxial wafer grown directly on the substrate crystal 1 was used. As shown in FIG. 7, this epitaxial wafer is made of GaAs having a deep acceptor obtained by heavy doping of Si on a GaAs substrate crystal 1.
P-type layer 3 made of a layer 3, Ga _1-x Al _x As layer made of n
N comprising a mixed crystal layer 7 of the type and a GaAs layer doped with Te
The + type layers 9 are sequentially superposed. On the growth layer surface of the chip having this layer structure, first, a ring-like shape having a depth reaching the pn heterojunction 8 is formed by photoetching using a sulfuric acid-hydrogen peroxide-water system etchant having a capacity ratio of 2: 1: 1. The etching groove 13 was formed. The pn heterojunction 8 is
It is divided into a central part and a peripheral part by the etching groove 13,
An ohmic electrode 5 for n-type and an ohmic electrode 6 for p-type are formed in each.

A positive photoresist is spinner coated to a thickness of about 1.3 μm on the surface of the wafer on which the etching grooves 13 corresponding to the number of chips that can be obtained are formed, dried and then held at 90 ° C. for 5 minutes. Prebaking was performed to expose the surface portions where the ohmic electrodes 5 and 6 were not formed.
At this time, the ultraviolet rays used for the exposure are 300 to 400n.
Those having a wavelength of m were suitable. The exposed wafer was reverse-baked by heating at 117 ° C. for 5 minutes, and only the exposed surface portion was changed to a negative type. Next, after exposing the entire surface of the wafer on which the photoresist was applied, the wafer was developed to elute only the photoresist on the surface on which the ohmic electrodes 5 and 6 which were exposed first are provided. As a result, a hole having a wider bottom than the entrance surrounded by the overhanging wall was formed, and the surface of the n + type layer 9 was exposed at the bottom surface of the hole.

When the metal film is vapor-deposited from the surface of the resist film having the holes, the metal film is vapor-deposited only on the upper surface of the resist film and the bottom surface of the hole, and it is difficult for the metal film to adhere to the side wall of the hole. The ohmic electrodes 5 and 6 can be easily formed. Therefore, the Au-Ge eutectic alloy usually used for the n-type layer has a thickness of about 0.4 μm from the top surface direction of the developed photoresist, and Ni on this has a thickness of about 0.5 μm. Now, about 2 μm Au
Then, all the photoresist was removed with a resist remover. As a result, unnecessary portions of the metal multilayer vapor deposition film were lifted off together with the resist, leaving only the ohmic electrodes 5 and 6. Then, the wafer was heated in a nitrogen atmosphere at 400 ° C. for 3 minutes to make the ohmic electrodes 5 and 6 into ohmic contacts having a small contact resistance with respect to the underlying n + type layer 9.

Next, in the parts to be individual chips,
Out of the pn heterojunction 8 divided into the central portion and the peripheral portion by the ring-shaped etching groove 13, a reverse current is applied to the peripheral portion to break the pn junction in the peripheral portion. As a result, the non-rectifying current path reaches the lower p-type layer 3. The non-rectifying current path was formed as follows. The reverse breakdown voltage of the pn heterojunction 8 in this embodiment is 8
Since each chip was distributed up to -17 V, a 47 μF capacitor was charged with a DC voltage of 24 V, which was sufficiently higher than the reverse breakdown voltage. From this capacitor, through the series resistance of 50Ω, toward the ohmic electrodes 6 to 5 on the individual chip portions on the wafer, that is, the ohmic electrode 6 is biased to the positive side and the ohmic electrode 5 is biased to the negative side, and the discharge current Shed. Since only a forward current flows in the pn heterojunction 8 below the ohmic electrode 5, it is not destroyed at all and p for radiative recombination is not generated.
The -n heterojunction 8 remains intact. On the other hand, a reverse current flows through the pn heterojunction 8 below the ohmic electrode 6, so that the pn heterojunction 8 is instantaneously destroyed and becomes a pn junction trace 14.

Finally, individual chips were separated from the wafer by dicing or scribing. Also,
If necessary, the GaAs substrate crystal 1 was polished into a hemispherical shape to complete the structure shown in FIG. The completed chip was face-down bonded onto a lead frame, molded with a transparent resin, and assembled into an infrared light emitting diode. The infrared light emitting diode having such a structure has the n-type mixed crystal layer 7 having a wider energy forbidden band width and a smaller photorefractive index than that of the p-type GaAs layer 3, and therefore is biased in the forward direction to emit light. When this is done, holes are confined in the part of the p-type layer 3 adjacent to the pn heterojunction 8. Therefore, the radiative recombination of the injected electrons concentrates in this portion and occurs with high efficiency, the half width of the emission spectrum is narrow, and the response speed to current modulation is improved. Further, since the n-type mixed crystal layer 7 functions as a total reflection film, the outcoupling rate of the generated long-wavelength light also becomes high.

For example, in the device obtained by molding the manufactured hemispherical chip with a transparent epoxy resin having a refractive index of about 1.6, the half value width is 67 nm and the response speed to current modulation is 740 kHz at the cutoff frequency. It was extremely excellent in comparison. In addition, since the same type of metal film can be simultaneously deposited on the same surface of the wafer and the same heat treatment can be used to form the ohmic electrodes 5 and 6 for both n-type and p-type, the number of steps is reduced as compared with the conventional method. Significantly reduced and productivity improved.

In the above embodiment, n-type GaAs is used as the substrate crystal 1 and the ring-shaped etching groove 13 is used.
The case where the pn heterojunction 8 is divided by is explained. Also, the case where no anti-reflection coating is applied to the light emitting surface of the chip has been described. However, in the device structure according to the present invention, since almost no current flows in the substrate crystal 1, other substrate crystals such as p-type and semi-insulating GaAs can be used. Further, as a method of dividing the pn junction 8 into a plurality of divisions, it is also possible to adopt a division method of another shape such as dividing into two in a letter shape and dividing into three in an eye shape. Furthermore, the present invention can be practiced even if the tip surface is coated with antireflection coating or the like. The point is that at least a p-type layer having a deep acceptor by heavy doping of Si and an n-type Ga _1-x Al _x As mixed crystal layer are grown on a GaAs substrate crystal to grow the p-type layer and the n-type mixed crystal. Any structure may be used as long as it has a pn junction between the crystal layer and the positive electrode and the negative electrode on the side where these epitaxial growth layers are present.

[0038]

As described above, in the present invention, p is provided between the p-type GaAs layer on the GaAs substrate crystal side and the n-type Ga _1-x Al _x As mixed crystal layer superposed thereon. -N
A heterojunction is formed, and a non-rectifying current path from the chip surface to this pn heterojunction is formed. Since the optical refractive index of the n-type mixed crystal layer is smaller than that of the p-type layer, total reflection occurs at the pn heterojunction, and the long wavelength light generated inside the element is efficiently extracted to the outside. Also, the radiative recombination is pn
Since it is limited to the p-type layer portion near the heterojunction, the width of the emission spectrum becomes narrower and the response speed to the current modulation becomes faster than that of the conventional element. Moreover, since the n-type and p-type ohmic electrodes can be formed on the same plane, the die bonding method can also be adopted. Therefore, a high-performance infrared light emitting diode can be manufactured with high productivity.

[Brief description of drawings]

FIG. 1 Conventional epitaxial wafer for infrared light emitting diode

FIG. 2 Structure of a chip part made from the same epitaxial wafer

FIG. 3 is an epitaxial wafer according to an embodiment of the present invention.

FIG. 4 is an epitaxial wafer according to an embodiment of the present invention.

5 is a structure of a chip portion made from the epitaxial wafer of FIG.

6 is a structure of a chip portion made from the epitaxial wafer of FIG.

FIG. 7 is a structure of a chip portion in which a non-rectifying current path is formed by breakdown breakdown of a pn heterojunction.

[Explanation of symbols]

1 GaAs substrate crystal 2 n-type layer 3 p
Type layer 4 pn junction 5 Ohmic electrode for n-type 6 Ohmic electrode 7 n for p-type
Type mixed crystal layer 8 pn heterojunction 9 n + type layer 10
Positive lead 11 Negative lead 12 Non-rectifying current path 13 Ring-shaped etching groove 14
pn junction trace

Claims (2)

[Claims] 1. A Si provided on a GaAs substrate crystal.
And a p-type GaAs layer having a deep acceptor by heavy doping, and being provided so as to overlap with the p-type GaAs layer,
An n-type mixed crystal layer made of Ga _1-x Al _x As doped with a Chardonna of Te, S, Se, Sn, etc. other than Si;
P formed between the p-type GaAs layer and the mixed crystal layer
A p-n heterojunction and a non-rectifying current path extending from the chip surface to the p-type layer formed by extinguishing or destroying a part of the pn heterojunction.
An infrared light emitting diode having an n-heterojunction. 2. A p-type layer of GaAs having a deep acceptor by heavy doping of Si is epitaxially grown on a GaAs substrate crystal, and an n-type mixed crystal layer made of Ga _1-x Al _x As with deep Chardonna is formed. Epitaxially growing on the p-type layer,
A non-rectifying current path reaching the p-type layer from the surface of the type mixed crystal layer is formed, and an ohmic electrode for the non-rectifying current path and the n-type mixed crystal layer is formed on the epitaxial growth layer side. Method of manufacturing external light emitting diode.