JPS5987881A - Manufacture of optical semiconductor device - Google Patents

Manufacture of optical semiconductor device

Info

Publication number
JPS5987881A
JPS5987881A JP57198196A JP19819682A JPS5987881A JP S5987881 A JPS5987881 A JP S5987881A JP 57198196 A JP57198196 A JP 57198196A JP 19819682 A JP19819682 A JP 19819682A JP S5987881 A JPS5987881 A JP S5987881A
Authority
JP
Japan
Prior art keywords
type
added
silicon
growth layer
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57198196A
Other languages
Japanese (ja)
Inventor
Tetsuo Sekiwa
関和 哲男
Yoshio Iizuka
飯塚 佳男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57198196A priority Critical patent/JPS5987881A/en
Publication of JPS5987881A publication Critical patent/JPS5987881A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds

Abstract

PURPOSE:To make thickness to the degree of 300mum, and to enhance yield of the progress of manufacturing work of a light emitting element by a method wherein after an N type Ga1-xAlxAs epitaxial growth layer added with tellurium or silicon is grown on an N type GaAs substrate, an N type and a P type Ga1-yAlyAs (x>y) epitaxial growth layers added with silicon and added with the small quantity of Al are grown in order. CONSTITUTION:An epitaxial growth solution of Ga1-xAlxAs added with tellurium is made to come in contact with the upper part of a GaAs substrate 1 added with N type silicon at the temperature of 950 deg.C to be cooled to 850 deg.C by the rate of 1 deg.C every one minute, and an N type Ga1-xAlxAs growth layer 2 is grown. Then the temperature is risen again up to 920 deg.C in the condition that the used epitaxial growth solution is removed from the upper part of the GaAlAs growth layer 2, and it is held as it is till the temeprature is stabilized. Then an N type Ga1-xAlyAs growth layer 3 added with silicon and a P type Ga1-yAlyAs layer 4 are grown on the N type Ga1-xAlxAs growth layer 2 cooling the Ga1-yAlyAs (x>y) epitaxial growth solution added with silicon to 700 deg.C, and P- N junction is formed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はGaAtAsを用い竹に赤外領域で高出力の発
光ダイオードとして使用する場合に適した光半導体装置
の製造方法に関する。 〔発明の技術的背景とその問題点〕 フォトカプラ、光通信用センサ等に使用される発光ダイ
オードは、主にN型のGaAs基板上に、液相エピタキ
シャル徐冷成長法により両性不純物であるシリコンを添
加してN型、P型GaAs成長層を成長させ、PN接合
を形成する。 この場合シリコンによる発、光中心はGaAsの禁制帯
幅より低いエネルギであるが、発光はGaAs層中で光
吸収が大きく、実際発光素子外部へ取り出される光は少
なくなる。 一方、内部で発光した光を有効に外部に取り出す素子と
して、第1図に示す如きGaAtAsを用いたものがあ
る。この場合、第2図に示す温度グログラムでN型Ga
As基板上に、GaAtAsを液相エピタキシャル徐冷
法により、両性不純物であるシリコンを添加してN型+
 P R’i−GaAtAs成長層を成長させ、PN接
合を形成する。但し第2図においてaはGaAs基板と
エピタキシャル溶液の接触時点である。しかしながら上
記のように形成されたものにあっては、高温ではAtの
偏析係数が大きく低温では小さくなるため、成長層中の
AtAaの混晶比は第1図に示す如く成長層表面に向っ
て極端に小さくなる。このためPN接合で発光した光は
、GaAs基板、AtAsの混晶比の低い成長層表面で
ほとんど吸収され、側面からの光のみが素子外部へ取り
出されるため、極めて低いものとなる。 そこで一般にはGaAs基板を取り除いて、液相エピタ
キシャル成長層のみを用いた第1図の発光領域のAtA
s混晶比よりも光吸収の少ないAtAs混晶比の高いN
型成長層側より外部へ有効に光を取り出すことにより、
GaAs発光素子に比べて数倍の高出力素子を得ている
。なお発光波長は成長開始温度及びエピタキシャル成長
されて決定する。また従来の多層成長は、徐冷中に成長
溶液を何回も入れ替えて行なうが、実質的に成長層を厚
くすることができない。この方法は、薄層を精度よく成
長させるものである。 しかしながら従来のシリコン添加のG aAtA s素
子は、高出力の素手が得られるが、製造技術上に欠点が
あった。それは1、第2図のよ゛うに発光素子特性上、
禁制帯幅の広い側から外部へ有効に発光を取り出すため
、GaAs基板を除去する必要がある。従来の徐冷法に
よる液相エピタキシャル技術では、成、多層の厚さは2
00μ前後が限界である。一般に発光素子の製造では3
00μ程度が必要であるため、200μ前後の成長層で
は大面積で処理することができず、発光素子製造工程で
の歩留が極端に低くなってしまうものであった。 〔発明の目的〕 本発明は上記実情に鑑みてなされたもので、上記の徐冷
法による液相エピタキシャル成長層の厚さを増加させ、
該厚さを300μ程度にすることが可能となって発光素
子製造工程の歩留を著しく向上することができ、しかも
発光素子特性を損なうことのない光半導体装置の製造方
法を提供しようとするものである。 〔発明の概要〕 本発明は1回の液相エピタキシャル成長法で、N型のG
aAs基板上に、テルル或いはシリコン添加のN型Ga
I XAtXAl+エピタキシャル成長層を成長後、前
記テルル或いはシリコンを含有するエピタキシャル成長
溶液を排除し、その状態で再度昇温し、前記N型Ga 
1−2ALzA s成長層上に、シリコン添加のN 、
 P m Ga1 yA2yAs (x)y)エピタキ
シャル成長層を順次成長させて、発光素子製造工程に必
要な成長層が肖られ、かつ発光素子特性も同等以上のも
のが得られるようにしたものでおる。 〔発明の実施例〕 以下図面を参照して本発明の一実施例を説明する。第3
図、第4図は同実施例の構造図、第5図は同構造を得る
工程の温度プロ、ンラムである。即ち(ioo)面を有
するN型シリコン添加のGaAs基板1上に、950℃
からテルル添加のGa1−XAtXA8のエピタキシャ
ル溶液(Ga 、GaAs *At)を接触させて、8
50℃まで1分間に1℃の割合で冷却し、N型Ga1□
AtxA s成長層2を成長させる。第5図においてb
は、GaAs基板1とシリコン添加のGaAtABエピ
タキシャル溶液との接触時点を示す。しかる後、上記使
用したエピタキシャル溶液をGaAAAs成長層2上か
ら、第5図のcAそ排除する。その状態で再度920℃
まで昇温し、温度が安定するまで1時間保持する。次に
シリコンを添加したGa1’−yAtyAs(x>y)
のエピタキシャル成長溶液(Qa 、GaAs *At
)を第5図のdの時点で接触させて、700℃まで1分
間に1℃の□割合で冷却させながら、上記N型Ga 1
−1ALzAs成長rfA 2上にシリコン添加のN型
G a 1−yAtyA−s成長層3、P型Ga1−y
A/yAs(x>y )成長N4を成長させて、PNN
接合形成する。AtAs混晶比分布は第4図に示される
ようになり、第1成長層2の終予時のAtAs混晶比は
第2成長層3開始のAtAs混晶比より高くなっている
。この成長によって、エビクキシャル成長層の厚さが3
50μのものが再現性よく得られた。 他の実施例として、上記テルル添加をシリコン添加とし
たGaAtAs成長層を950℃から850℃tで成長
させた方法でも、成長層の厚さが350μのものが得ら
れた。この時のAtAs混晶比分布、温度プログラムは
前実施例の場合と同じである。 上記実施例によれば、成長層厚さが300μ以上のもの
が安定して得られ、発光素子製造の問題点となっていた
GaAs基板1除去後の厚さが充分なものとなり、製造
歩留が向上する。即ち従来技術での製造歩留は20%位
であったものが、本発明により80%位まで改善された
。 また第5図に順方向に100 mA通電し、発光出力の
変化を調べたところ、発光出力に大きな相違が見られた
。これは従来技術では、発光効率とSt濃度との相関で
N型GaAtAs層の表面ドナー濃度を畠くすることが
できないため、GaAtAa層表面と電接と6間の抵抗
が高くなり、通電中に素子発熱が多く、熱(ソよる劣化
が多くなると考えられるためである。これに対し本発明
では、第1層のN IJI GaAtA、s層2のTe
或いはStの添加拓、を変えることによって表面ドナー
濃度を高娘度にすることができ、表面と電極との抵抗を
低くできる。このため素子発熱による劣化か非常に少な
い。      更に従来技術では発光素子の厚さが薄いため、マウント
・ボンディン−グによ不4電性ペーストのは゛い上がり
によるPN接合への悪影響及び衝撃による応力歪が通電
中にPNJg合近傍に多くの欠陥が発生し、通電劣化を
招いている。従って本発明では素子厚が厚いため、通電
劣化についても効果があることが判明した。 〔発明の効果〕 以上説明した如く本発明によれば、素子厚が厚くなるた
め、製造門留が向上し、通電劣化もないなどの利点を有
した光半導体装置の製造方法が提供できるものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an optical semiconductor device made of GaAtAs and made of bamboo suitable for use as a high-output light emitting diode in the infrared region. [Technical background of the invention and its problems] Light-emitting diodes used in photocouplers, optical communication sensors, etc. are mainly made of silicon, which is an amphoteric impurity, on an N-type GaAs substrate by a liquid phase epitaxial slow cooling growth method. is added to grow N-type and P-type GaAs growth layers to form a PN junction. In this case, although the energy of the light emitted from silicon is lower than the forbidden band width of GaAs, the emitted light is largely absorbed in the GaAs layer, and the amount of light actually extracted to the outside of the light emitting element is small. On the other hand, as an element for effectively extracting light emitted inside to the outside, there is an element using GaAtAs as shown in FIG. In this case, the temperature grogram shown in Figure 2 shows that N-type Ga
On the As substrate, silicon, which is an amphoteric impurity, is added to GaAtAs using a liquid phase epitaxial slow cooling method to form N-type +
A P R'i-GaAtAs growth layer is grown to form a PN junction. However, in FIG. 2, a indicates the point of contact between the GaAs substrate and the epitaxial solution. However, in the case of the structure formed as described above, the segregation coefficient of At is large at high temperatures and becomes small at low temperatures, so the mixed crystal ratio of AtAa in the growth layer increases toward the surface of the growth layer as shown in Figure 1. becomes extremely small. Therefore, most of the light emitted from the PN junction is absorbed on the surface of the GaAs substrate and the growth layer of AtAs with a low mixed crystal ratio, and only the light from the sides is extracted to the outside of the device, resulting in an extremely low level of light. Therefore, in general, the GaAs substrate is removed and the AtA layer in the light emitting region shown in Fig. 1 is grown using only a liquid phase epitaxial growth layer.
N with a high AtAs mixed crystal ratio that absorbs less light than the s mixed crystal ratio
By effectively extracting light from the mold growth layer side to the outside,
A high output device several times higher than that of a GaAs light emitting device is obtained. Note that the emission wavelength is determined by the growth start temperature and epitaxial growth. Furthermore, in conventional multilayer growth, the growth solution is replaced many times during slow cooling, but it is not possible to substantially increase the thickness of the growth layer. This method allows thin layers to be grown with precision. However, although the conventional silicon-doped GaAtAs element can provide high output power, it has drawbacks in terms of manufacturing technology. This is due to the characteristics of the light emitting device as shown in Figure 1 and Figure 2.
In order to effectively extract light from the side where the forbidden band width is wide, it is necessary to remove the GaAs substrate. In the conventional liquid phase epitaxial technology using slow cooling method, the thickness of the multilayer is 2.
The limit is around 00μ. In general, in the manufacture of light emitting devices, 3
Since a growth layer of around 200 μm is required, a large area cannot be treated with a grown layer of around 200 μm, resulting in extremely low yield in the light emitting device manufacturing process. [Object of the invention] The present invention has been made in view of the above-mentioned circumstances, and includes increasing the thickness of the liquid phase epitaxial growth layer by the above-mentioned slow cooling method,
It is an object of the present invention to provide a method for manufacturing an optical semiconductor device that can reduce the thickness to about 300 μm, significantly improve the yield of the light emitting device manufacturing process, and without impairing the characteristics of the light emitting device. It is. [Summary of the invention] The present invention uses a one-time liquid phase epitaxial growth method to grow N-type G
N-type Ga doped with tellurium or silicon on an aAs substrate.
After growing the I
1-2 On the ALzAs growth layer, silicon-added N,
P m Ga1 yA2yAs (x) y) The epitaxial growth layers are sequentially grown so that the growth layers necessary for the light emitting device manufacturing process are formed, and the light emitting device characteristics are also equivalent or better. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. Third
4 is a structural diagram of the same example, and FIG. 5 is a temperature program of the process of obtaining the same structure. That is, on a GaAs substrate 1 doped with N-type silicon having an (ioo) plane, a temperature of 950° C.
A tellurium-added Ga1-XAtXA8 epitaxial solution (Ga, GaAs *At) was brought into contact with the 8
Cool to 50°C at a rate of 1°C per minute to form N-type Ga1□
AtxAs growth layer 2 is grown. In Figure 5, b
indicates the point of contact between the GaAs substrate 1 and the silicon-added GaAtAB epitaxial solution. Thereafter, the epitaxial solution used above is removed from above the GaAAAs growth layer 2 as shown in FIG. In that state, 920℃ again
and hold for 1 hour until the temperature stabilizes. Next, Ga1'-yAtyAs (x>y) with silicon added
epitaxial growth solution (Qa, GaAs *At
) at point d in Figure 5, and while cooling to 700°C at a rate of 1°C per minute, the N-type Ga 1
-1ALzAs growth rfA 2 N-type Ga 1-yAtyAs growth layer 3 with silicon added, P-type Ga1-y
A/yAs(x>y) Growth N4 is grown to form PNN
Form a junction. The AtAs mixed crystal ratio distribution is as shown in FIG. 4, and the AtAs mixed crystal ratio at the end of the first grown layer 2 is higher than the AtAs mixed crystal ratio at the beginning of the second grown layer 3. Due to this growth, the thickness of the eviaxial growth layer is 3
A sample of 50μ was obtained with good reproducibility. As another example, a GaAtAs growth layer with silicon added instead of tellurium was grown at 950° C. to 850° C., and a grown layer with a thickness of 350 μm was obtained. At this time, the AtAs mixed crystal ratio distribution and temperature program are the same as in the previous embodiment. According to the above embodiment, a growth layer with a thickness of 300 μm or more can be stably obtained, and the thickness after removing the GaAs substrate 1, which has been a problem in the production of light emitting devices, is sufficient, and the production yield can be improved. will improve. That is, the production yield in the conventional technology was about 20%, but it was improved to about 80% by the present invention. Further, as shown in FIG. 5, when a current of 100 mA was applied in the forward direction and changes in the light emission output were examined, a large difference in the light emission output was observed. This is because in the conventional technology, it is not possible to increase the surface donor concentration of the N-type GaAtAs layer due to the correlation between the luminous efficiency and the St concentration, so the resistance between the surface of the GaAtAa layer and the electrical contact becomes high. This is because the element generates a lot of heat and is thought to cause more deterioration due to heat.In contrast, in the present invention, the first layer of N IJI GaAtA and the s layer 2 of Te
Alternatively, by changing the amount of St added, the surface donor concentration can be made high, and the resistance between the surface and the electrode can be lowered. Therefore, there is very little deterioration due to element heat generation. Furthermore, in the conventional technology, since the thickness of the light emitting element is thin, the rise of the non-quaternary conductive paste due to mount bonding has an adverse effect on the PN junction, and the stress and strain caused by the impact can cause many defects near the PNJg during energization. occurs, causing deterioration in current flow. Therefore, it has been found that the present invention has an effect on deterioration caused by current conduction because the element thickness is large. [Effects of the Invention] As explained above, according to the present invention, it is possible to provide a method for manufacturing an optical semiconductor device which has advantages such as an increase in element thickness, improved manufacturing efficiency, and no deterioration due to electrical conduction. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の光半導体装置の構成及び特性説明図、第
2図は同構成を得る工程の温度グログラムを示す図、第
3図は本発明の一実施例の素子構成説明図、第4図は同
構成の特性説明図、第5図は同構成を得る工程の温度プ
ログラムを示す図、第6図は同構成の発光特性図である
。 1 ・N型GaAs基板、2 ・N型G a 1−、X
AtzA s層、3−−− N m Ga1 、Aty
As層、4 ・P型Ga1 、AtyAs層。 出願人代理人  弁理士 鈴 江 武 彦舘1図 第2図 v1開 第3図。 第4図 第5図 第6図 通を椅聞
FIG. 1 is an explanatory diagram of the configuration and characteristics of a conventional optical semiconductor device, FIG. 2 is a diagram showing a temperature grogram of the process of obtaining the same configuration, FIG. 5 is a diagram illustrating the characteristics of the same configuration, FIG. 5 is a diagram showing a temperature program in the process of obtaining the same configuration, and FIG. 6 is a diagram showing the light emission characteristics of the same configuration. 1 ・N-type GaAs substrate, 2 ・N-type Ga 1-, X
AtzAs layer, 3--- N m Ga1 , Aty
As layer, 4.P-type Ga1, AtyAs layer. Applicant's agent Patent attorney Takeshi Suzue Hikodate Figure 1 Figure 2 v1 Open Figure 3. Fig. 4 Fig. 5 Fig. 6 Listen to the crowd

Claims (2)

【特許請求の範囲】[Claims] (1)徐冷法による液相エピタキシャル成長でN型Ga
As基板上に、テルル或いはシリコン添加のN型Ga1
 zALzjJ1成長層を成長後、前記テルル或いはシ
リコンを含有する液相エピタキシャル成長溶液を排除し
、その状態で再度昇温し、前記N型Ga 1− XAt
XA!+成長層上にシリコン添加のN型Ga1 、At
yAs成長層及成長層層上にシリコン添加のP型G a
 1−yALyA s成長層を成長させてなり、前記X
とyとの関係はx>yとなすことを特徴とする光半導体
装置の製造方法。
(1) N-type Ga is grown by liquid phase epitaxial growth using slow cooling method.
N-type Ga1 doped with tellurium or silicon on an As substrate
After growing the zALzzjJ1 growth layer, the liquid phase epitaxial growth solution containing tellurium or silicon is removed, and the temperature is raised again in that state to form the N-type Ga 1-
XA! +N-type Ga1 with silicon added on the growth layer, At
yAs growth layer and silicon-added P-type Ga on the growth layer
1-yALyAs growth layer is grown, and the X
A method for manufacturing an optical semiconductor device, characterized in that the relationship between and y is x>y.
(2)前記シリコン添加のP型G a 1−yALyA
 s成長層を形成後:前記N型GaAs基板を除去する
ことを特徴とする特許請求の範囲第1項に記載の光半導
体装置の製造方法。
(2) Said silicon-added P-type Ga 1-yALyA
2. The method of manufacturing an optical semiconductor device according to claim 1, wherein after forming the s-growth layer: the N-type GaAs substrate is removed.
JP57198196A 1982-11-11 1982-11-11 Manufacture of optical semiconductor device Pending JPS5987881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57198196A JPS5987881A (en) 1982-11-11 1982-11-11 Manufacture of optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57198196A JPS5987881A (en) 1982-11-11 1982-11-11 Manufacture of optical semiconductor device

Publications (1)

Publication Number Publication Date
JPS5987881A true JPS5987881A (en) 1984-05-21

Family

ID=16387064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57198196A Pending JPS5987881A (en) 1982-11-11 1982-11-11 Manufacture of optical semiconductor device

Country Status (1)

Country Link
JP (1) JPS5987881A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652178A (en) * 1989-04-28 1997-07-29 Sharp Kabushiki Kaisha Method of manufacturing a light emitting diode using LPE at different temperatures
US5707891A (en) * 1989-04-28 1998-01-13 Sharp Kabushiki Kaisha Method of manufacturing a light emitting diode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652178A (en) * 1989-04-28 1997-07-29 Sharp Kabushiki Kaisha Method of manufacturing a light emitting diode using LPE at different temperatures
US5707891A (en) * 1989-04-28 1998-01-13 Sharp Kabushiki Kaisha Method of manufacturing a light emitting diode

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